CN103066988A - Interface circuit and achievement method for limiting output port voltage slew rate - Google Patents
Interface circuit and achievement method for limiting output port voltage slew rate Download PDFInfo
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Abstract
The invention discloses an interface circuit and achievement method for limiting output port voltage slew rate. The interface circuit and achievement method for limiting output port voltage slew rate comprise a first switch and a second switch respectively connected with a current source and a current sink in series, a first P-channel Metal Oxide Semiconductor (PMOS) pipe and a first N-channel metal oxide semiconductor (NMOS) pipe which are sequentially in series connection and arranged between a power and ground, a third switch connected with a gate electrode of the first PMOS pipe and a fourth switch connected with a gate electrode of the first NMOS pipe, wherein the connection point of the first PMOS pipe and the first NMOS pipe acts as an output port of the interface circuit; a current source branch and a current sink branch are connected on the position of a public port, and the public port is connected with the other end of the third switch and the fourth switch; an in-chip capacitor is connected between the public port and the output end. The interface circuit limiting output port voltage slew rate and achievement method further comprise a logic control unit respectively connected with control electrodes of the first switch, the second switch, the third switch and the fourth switch to control on-off of the control electrodes. The interface circuit and achievement method for limiting output port voltage slew rate can effectively limit voltage slew rates and output current of the output port of the interface circuit, and play roles of decreasing electro-magnetic interference (EMI), protecting the interface circuit and improving transmission rates of the interface circuit.
Description
Technical field
The present invention relates to the interface circuit of the transmission of data, relate in particular to a kind of interface circuit and its implementation that limits the output end voltage Slew Rate.
Background technology
Interface circuit is vitals indispensable in the transfer of data, in the application of interface circuit, if with traditional inverter drive output port, when high-low level switches, exists the excessive situation of output transient current.If without restriction, such current break can worsen the EMI characteristic of interface circuit, and excessive electric current also may damage the output device of interface circuit.Common restriction way is resistive device of series connection in output device; Perhaps only adopt the resistance of leaving behind on one as output device, draw on plaing a part or drop-down, play simultaneously the effect of current limliting and deboost Slew Rate.But connect resistive device or the signal when only adopting upper pull down resistor then can affect the interface circuit the transmission of data rise or fall off rate, are unfavorable for being used in the occasion that transmission rate is had higher requirements.
Summary of the invention
The present invention will solve the demand that the existing interface circuit can not be taken into account deboost Slew Rate and high transfer rate, propose a kind of can deboost Slew Rate and output current, have again the circuit of high data rate.
For solving the problems of the technologies described above, the technical scheme that the present invention proposes is a kind of interface circuit that limits the output end voltage Slew Rate of design, it comprises: a current source I1, the heavy I2 of electric current, the first switch S 1, the second switch S2 that connect with current source I1, the heavy I2 of electric current respectively, be serially connected in successively PMOS pipe T1 and NMOS pipe T2 between power supply and the ground, the 3rd switch S 3 that connects PMOS pipe T1 grid, the 4th switch S 4, the one PMOS pipe T1 and the NMOS that connect NMOS pipe T2 grid manage the tie point of T2 as the interface circuit output; Current source I1 branch road is connected at the common port place with the heavy I2 branch road of electric current, and this common port connects the other end of the 3rd switch S 3 and the 4th switch S 4; Be connected capacitor C in the sheet between this common port and the output; Also comprise respectively being connected with the first switch S 1, second switch S2, the 3rd switch S 3 and the 4th switch S 4 control utmost points, to control the logic control element of its break-make.
The type of described interior capacitor C in includes but not limited to the capacitor that CMOS capacitor, metal-dielectric metal capacitor, polycrystalline-medium-based semiconductor integrated circuit technologies such as polycrystalline capacitor realize.
The order that described the first switch S 1 is connected with current source I1 is arbitrarily, and current source I1 can be connected on any end at the first switch S 1 two ends; The order that the heavy I2 of second switch S2 and electric current connect is that electric current sinks I2 and can be connected on any end at second switch S2 two ends arbitrarily.
Described the first switch S 1 adopts the PMOS pipe, and second switch S2 adopts the NMOS pipe, and the 3rd switch S 3 and the 4th switch S 4 adopt cmos transmission gate; The grid of the first switch S 1 and the 4th switch S 4 links together, and the grid of second switch S2 and the 3rd switch S 3 links together.
Interface circuit comprises that also electric current is heavy in the interior current source of sheet and the sheet, is serially connected in the pull-up resistor between power supply and the output; Described current source I1 is made of the second and the 3rd PMOS pipe, and the 2nd PMOS pipe is serially connected between the first switch S 1 and the common port, and electric current is heavy in its drain electrode contact pin; The 3rd PMOS pipe be serially connected in the first switch S 1 and the sheet electric current heavy between, electric current is heavy in its drain electrode contact pin; The 3rd PMOS pipe connects power supply with the tie point of the first switch S 1; The heavy I2 of described electric current is made of the second and the 3rd NMOS pipe, and the 2nd NMOS pipe is serially connected between second switch S2 and the common port, current source in its drain electrode contact pin; The 3rd NMOS pipe is serially connected between second switch S2 and the interior current source of sheet, current source in its drain electrode contact pin; The tie point ground connection of the 3rd NMOS pipe and second switch S2.
Described logic control element comprises: data-signal end, the first control end that connects the first switch S 1 and the 4th switch S 4 grids, the second control end, the 4th, the 5th that connects second switch S2 and the 3rd switch S 3 grids, the 6th NMOS pipe, the 4th PMOS pipe, wherein the 4th NMOS tube grid connects first and gate output terminal, drain electrode connects second, third and input of door and an end of latch, source ground; The 5th NMOS tube grid connects the data-signal end, and drain electrode connects the other end of latch, source ground; The 6th NMOS tube grid connects the second control end, and drain electrode connects second switch grid, source ground; The 4th gate pmos utmost point connects the first control end, and drain electrode connects power end, and source electrode connects the first switch gate; The data-signal end connect the 3rd with another input of door, also connect the input of the second not gate; The output of the second not gate connect second with another input of door, also connect first with an input of door; First is connected the output of the first not gate with another input of door, and the input of the first not gate connects described common port; Second with the door described the first control end of output termination; The 3rd with the input of output termination the 3rd not gate of door, described the second control end of the output termination of the 3rd not gate.
The present invention also proposes a kind of method that limits interface circuit output end voltage Slew Rate: first switch S 1 of connecting with current source I1, the 4th switch S 4 that connects PMOS pipe T1 grid, the second switch S2 that connects with the heavy I2 of electric current, and the on off operating mode that connects the 3rd switch S 3 of NMOS pipe T2 grid is controlled by a logic control element, this logic control element control switch produces three states: low state, control the first switch S 1 and 4 conductings of the 4th switch S, second switch S2 and 3 cut-offs of the 3rd switch S, so that PMOS pipe T1 cut-off, the one NMOS pipe T2 conducting, the interface circuit output end voltage is drop-down; High state is controlled the first switch S 1 and 4 cut-offs of the 4th switch S, second switch S2 and 3 conductings of the 3rd switch S, so that PMOS pipe T1 conducting, NMOS pipe T2 cut-off is drawn on the interface circuit output end voltage; High-impedance state is controlled the first switch S 1, second switch S2, the 3rd switch S 3,4 cut-offs of the 4th switch S, so that PMOS pipe T1 and NMOS pipe T2 cut-off, the interface circuit output is kept high potential.
Compared with prior art, the present invention limits the voltage Slew Rate of interface circuit output port simply and effectively, plays the effect that reduces EMI and protection interface circuit and raising interface circuit transmission rate; The voltage Slew Rate of interface circuit output and the electric current of output driver spare can be set, select simultaneously to have three kinds of state of switch control logics, can when satisfying the half-duplex operation needs, improve the interface circuit transmission rate.
Description of drawings
Below in conjunction with drawings and Examples the present invention is made detailed explanation, wherein:
Fig. 1 is circuit theory diagrams of the present invention;
Fig. 2 is the comparison of the voltage waveform that pull-down is transmitted on voltage waveform and resistive device current limliting or the resistance of output of the present invention output;
Fig. 3 is the circuit diagram of preferred embodiment major loop of the present invention;
Fig. 4 is the circuit diagram of preferred embodiment logic control element of the present invention;
Fig. 5 is the flow chart of the transmission of data of the present invention.
Embodiment
A kind of interface circuit that limits the output end voltage Slew Rate, referring to the circuit theory shown in Fig. 1, it comprises: a current source I1, the heavy I2 of electric current, the first switch S 1, the second switch S2 that connect with current source I1, the heavy I2 of electric current respectively, be serially connected in successively PMOS pipe T1 and NMOS pipe T2 between power supply and the ground, the 3rd switch S 3 that connects PMOS pipe T1 grid, the 4th switch S 4, the one PMOS pipe T1 and the NMOS that connect NMOS pipe T2 grid manage the tie point of T2 as the interface circuit output; Current source I1 branch road is connected at common port A place with the heavy I2 branch road of electric current, and this common port connects the other end of the 3rd switch S 3 and the 4th switch S 4; Be connected capacitor C in the sheet between this common port and the output; Also comprise respectively being connected with the first switch S 1, second switch S2, the 3rd switch S 3 and the 4th switch S 4 control utmost points, to control the logic control element of its break-make.
In the upper example, current source I1, the first switch S 1, the 4th switch S 4, NMOS pipe T2 consist of current source branch, and S1, S4, T2 action are synchronously; Electric current sinks I2, second switch S2, the 3rd switch S 3, PMOS pipe T1 and consists of the heavy branch road of electric current, and S2, S3, T1 action are synchronously.The action of logic control element 101 control S1 to S4, logic control element can control switch at three kinds of states.Output B(also claims output port among Fig. 1), carry out understanding the outer electric capacity Cout of brace after plug is pegged graft, Cout comprises all electric capacity on the output port.When the transmission high level, logic control element control switch S2 and S3 conducting, make the T2 conducting, VDD charges to output port B, but because the existence of internal capacitance Cin, the Slew Rate that the voltage of output port rises is restricted to I1/Cin, and when not being very large, the current value that flows out PMOS pipe T1 equals I1*Cout/Cin at Cout.When the transmission low level, logic control element control switch S1 and S4 conducting make the T2 conducting, and output port discharges over the ground, and the Slew Rate of the voltage drop of output port is restricted to I2/Cin, and the current value of inflow T2 equals I2*Cout/Cin.
Prior art adopts the method for the resistive device current limliting of series connection, and the resistance sum of establishing series resistance and output device is R, and supply voltage is VDD, and then the maximum current of output device is VDD/R; Maximum Slew Rate is VDD/ (R*Cout), and voltage Slew Rate after this reduces gradually with time constant R*Cout.For the interface circuit that draws in the common directly employing or pull down resistor is realized, identical conclusion is arranged.And when adopting the method that the present invention proposes, the maximum voltage Slew Rate is determined by I1/Cin (or I2/Cin), if this value is taken as with above-mentioned VDD/ (R*Cout) unanimously, then this value can keep certain always before T1 (or T2) enter linear zone.This means that than the former, this method can realize faster voltage rising (or decline) speed, thereby can realize faster interface circuit message transmission rate.
When realizing half-duplex operation, interface circuit transmission high level needs a pull-up resistor usually, transmission high level and keep the state of interface end and don't affect the reception of the other side's handshake.Can have influence on the speed of interface communication according to the such method of above-mentioned analysis.Adopt when of the present invention, by the on off state control logic control unit 101 of a three-state, the needs that satisfy half-duplex operation guarantee again the transmission rate of interface.
Slew Rate to the output voltage of the present invention and available circuit among Fig. 2 is contrasted.The upper part waveform is the output waveform of interface circuit of the present invention, and climbing speed and fall off rate are fixing approx.And lower part adopts the interface end voltage waveform of drop-down realization on resistive device current limliting or the resistance.In the maximum climbing speed situation the same with fall off rate, the rise time 201 is shorter than the rise time 202, and fall time 203 is shorter than fall time 204.Namely in the maximum climbing speed situation the same with fall off rate, the interface circuit that adopts the present invention to realize can improve message transmission rate.
It may be noted that the order that the first switch S 1 is connected with current source I1 is arbitrarily, current source I1 is above S1 among Fig. 1, and in other embodiments, current source I1 is below S1.Second switch S2 also is arbitrarily with the order that the heavy I2 of electric current connects, and the heavy I2 of electric current is below S2 among Fig. 1, and in other embodiments, the heavy I2 of electric current is above S2.
In preferred embodiment, the first switch S 1 adopts the PMOS pipe, and second switch S2 adopts the NMOS pipe, and the 3rd switch S 3 and the 4th switch S 4 adopt cmos transmission gate; The grid of the first switch S 1 and the 4th switch S 4 links together, and the grid of second switch S2 and the 3rd switch S 3 links together.In the present embodiment, a control pin of logic control element connects the grid of S1 and S4, S1 and S4 synchronization action; Another control pin of logic control element connects S2 and S3, S2 and S3 synchronization action.
Referring to Fig. 3, interface comprises also in the sheet in the current source 320 and sheet that electric current is heavy 321, is serially connected in the pull-up resistor 307 between power vd D and the output B in preferred embodiment; Described current source I1 is made of the second and the 3rd PMOS pipe 304, and the 2nd PMOS pipe 302 is serially connected between the first switch S 1 and the common port A, electric current heavy 321 in its drain electrode contact pin; The 3rd PMOS pipe 304 is serially connected between the first switch S 1 and the interior electric current heavy 320 of sheet, electric current heavy 321 in its drain electrode contact pin; The tie point of the 3rd PMOS pipe the 304 and first switch S 1 connects power supply.The heavy I2 of described electric current is made of the second and the 3rd NMOS pipe 305, and the 2nd NMOS pipe 303 is serially connected between second switch S2 and the common port A, current source 320 in its drain electrode contact pin; The 3rd NMOS pipe 305 is serially connected between second switch S2 and the interior current source 320 of sheet, current source 320 in its drain electrode contact pin; The tie point ground connection of the 3rd NMOS pipe 305 and second switch S2.The 2nd PMOS pipe the 302 and the 3rd PMOS pipe 304 current mirror efferent duct that partners, 302 as current source, and the image current size is I1.The 2nd NMOS pipe the 303 and the 3rd NMOS pipe 305 forms another to the current mirror efferent duct, and 303 is heavy as electric current, and the image current size is A for the tie point of I2 current source and the heavy branch road of electric current; The CMOS electric capacity of electric capacity employing source-drain electrode short circuit in the sheet in this example is because can keep again the stable of electric capacity simultaneously by saving chip area in change in voltage.Capacitor type includes but not limited to that the capacitor that CMOS capacitor, metal-dielectric metal capacitor, polycrystalline-medium-based semiconductor integrated circuit technologies such as polycrystalline capacitor realize all can.
Below in conjunction with Fig. 3 the transmission course of preferred embodiment is further described: when the transmission low level, PHASE-L is low, PHASE-H is low, S1 and S4 conducting, current source charges to Cin, the T2 conducting is drop-down with the output current potential, but the highest I1/Cin that is restricted to of voltage drop speed, the electric current that flows through T2 is I1*Cout/Cin.When the transmission high level, PHASE-H is high, and PHASE-L is high, S2 and S3 conducting, and electric current is heavy, and the T1 conducting will be drawn on the output current potential to the Cin charging, but the highest I2/Cin that is restricted to of climbing speed, the electric current that flows through T1 is I2*Cout/Cin; Finish draw after, reverted to lowly by logic control element control PHASE-H, PHASE-L be high, this moment, T1 and T2 were high-impedance state, by pull-up resistor 307 maintenance output high level; So in fact, realized the quick active pull up of output.
Fig. 4 shows the circuit diagram of logic control element in the preferred embodiment, it comprises: the second control end PHASE-L, the 4th NMOS pipe the 409, the 5th NMOS pipe the 410, the 6th NMOS pipe the 411, the 4th PMOS pipe 402 of data-signal end Data, the first control end PHASE-H that connects the first switch S 1 and the 4th switch S 4 grids, connection second switch S2 and the 3rd switch S 3 grids, wherein the 4th NMOS manage 409 grids connect first with the door 406 outputs, drain electrode connects second, third and input of door and an end of latch 403, source ground; The 5th NMOS tube grid 410 meets data-signal end Data, and drain electrode connects the other end of latch 403, source ground; The 6th NMOS tube grid meets the second control end PHASE-L, and drain electrode connects second switch grid, source ground; The 4th PMOS manages 402 grids and meets the first control end PHASE-H, and drain electrode connects power end, and source electrode connects the first switch T1 grid; Data-signal end Data connect the 3rd with door another input of 407, also connect the input of the second not gate 404; The output of the second not gate 404 connect second with another input of door 408, also connect first with an input of door 406; First is connected the output of the first not gate 401 with another input of door, and the input of the first not gate 401 connects described common port A; Second with door 408 described the first control end PHASE-H of output termination; The 3rd with the input of door 407 output termination the 3rd not gate 405, described the second control end PHASE-L of the output termination of the 3rd not gate 405.
Below in conjunction with Fig. 4 the course of work of logic control element is further described: logic control element produces switch controlling signal PHASE-H, PHASE-L according to the state of data-signal Data and common port A.When the transmission low level, Data receives high level, and PHASE-H, PHASE-L are low level; When the transmission high level, Data receives low level, because latch 403 keeps original state, PHASE-H, PHASE-L all are converted to high level, and T1 finished and was pulled through journey this moment.In finishing the process of drawing, A point current potential can reduce gradually, when being lower than certain value, draw on can thinking and finish, pull on judging by the inverter 401 of a lower threshold level, when 401 outputs are high, the conversion of latch 403 states, it is low putting PHASE-H, PHASE-L is high.And PHASE-H is when low, and the 4th PMOS manages 402 conductings, and the T1 grid potential is raise, and the T1 cut-off keeps high-impedance state; When PHASE-L was high, the 6th NMOS managed 411 conductings, and the T2 grid potential is reduced, and the T2 cut-off keeps high-impedance state.The " high " state that has drawn on so just having finished is to the conversion of high-impedance state.
The present invention has also disclosed a kind of method that limits interface circuit output end voltage Slew Rate: with the first switch S 1 of current source I1 series connection, is connected the 4th switch S 4 of PMOS pipe T1 grid, the second switch S2 that connects with the heavy I2 of electric current and be connected the on off operating mode that a NMOS manages the 3rd switch S 3 of T2 grid and controlled by a logic control element.Referring to the transmission of data flow process figure shown in Fig. 5, the logic control element control switch produces three states:
At first the interface circuit output is in high-impedance state, can receive data or send data, determined by a control signal;
When being in accepting state, transmitting portion continues to keep high-impedance state, and namely output keeps high-impedance state;
When being in the transmission state, need the transmission low level, logic control element sends low state, control the first switch S 1 and 4 conductings of the 4th switch S, second switch S2 and 3 cut-offs of the 3rd switch S, so that PMOS pipe T1 cut-off, the one NMOS pipe T2 conducting, the interface circuit output end voltage is drop-down, and it is drop-down namely to limit Slew Rate;
When being in the transmission state, need the transmission high level, logic control element sends high state, control the first switch S 1 and 4 cut-offs of the 4th switch S, second switch S2 and 3 conductings of the 3rd switch S, so that PMOS pipe T1 conducting, the one NMOS pipe T2 cut-off is drawn on the interface circuit output end voltage, namely limits on the Slew Rate and draws;
Logic control element detects and pulls into, sends high-impedance state, controls the first switch S 1, second switch S2, the 3rd switch S 3,4 cut-offs of the 4th switch S, so that PMOS pipe T1 and NMOS pipe T2 cut-off, the interface circuit output is kept high potential.
Judge according to the communications protocol of interface whether transmission is finished later on, decision is reception or continues to send data.Can see that by this process this state is controlled at the transmission rate that the demand that satisfies the interface circuit half-duplex operation has improved interface simultaneously.
Above embodiment is only for illustrating non-providing constraints.Anyly do not break away from the application's spirit and category, and to its equivalent modifications of carrying out or change, all should be contained among the application's the claim scope.
Claims (7)
1. interface circuit that limits the output end voltage Slew Rate, it is characterized in that comprising: a current source I1, the heavy I2 of electric current, the first switch S 1, the second switch S2 that connect with current source I1, the heavy I2 of electric current respectively, be serially connected in successively PMOS pipe T1 and NMOS pipe T2 between power supply and the ground, the 3rd switch S 3 that connects PMOS pipe T1 grid, the 4th switch S 4, the one PMOS pipe T1 and the NMOS that connect NMOS pipe T2 grid manage the tie point of T2 as the interface circuit output; Current source I1 branch road is connected at the common port place with the heavy I2 branch road of electric current, and this common port connects the other end of the 3rd switch S 3 and the 4th switch S 4; Be connected capacitor C in the sheet between this common port and the output; Also comprise respectively being connected with the first switch S 1, second switch S2, the 3rd switch S 3 and the 4th switch S 4 control utmost points, to control the logic control element of its break-make.
2. interface circuit as claimed in claim 1, it is characterized in that the type of described interior capacitor C in includes but not limited to the capacitor that CMOS capacitor, metal-dielectric metal capacitor, polycrystalline-medium-based semiconductor integrated circuit technologies such as polycrystalline capacitor realize.
3. interface circuit as claimed in claim 1 is characterized in that, the order that described the first switch S 1 is connected with current source I1 is arbitrarily, and second switch S2 is arbitrarily with the order that the heavy I2 of electric current connects.
4. interface circuit as claimed in claim 1 is characterized in that, described the first switch S 1 adopts the PMOS pipe, and second switch S2 adopts the NMOS pipe, and the 3rd switch S 3 and the 4th switch S 4 adopt cmos transmission gate; The grid of the first switch S 1 and the 4th switch S 4 links together, and the grid of second switch S2 and the 3rd switch S 3 links together.
5. interface circuit as claimed in claim 4 is characterized in that, comprises that also electric current is heavy in the interior current source of sheet and the sheet, is serially connected in the pull-up resistor between power supply and the output;
Described current source I1 is made of the second and the 3rd PMOS pipe, and the 2nd PMOS pipe is serially connected between the first switch S 1 and the common port, and electric current is heavy in its drain electrode contact pin; The 3rd PMOS pipe be serially connected in the first switch S 1 and the sheet electric current heavy between, electric current is heavy in its drain electrode contact pin; The 3rd PMOS pipe connects power supply with the tie point of the first switch S 1;
The heavy I2 of described electric current is made of the second and the 3rd NMOS pipe, and the 2nd NMOS pipe is serially connected between second switch S2 and the common port, current source in its drain electrode contact pin; The 3rd NMOS pipe is serially connected between second switch S2 and the interior current source of sheet, current source in its drain electrode contact pin; The tie point ground connection of the 3rd NMOS pipe and second switch S2.
6. interface circuit as claimed in claim 5, it is characterized in that, described logic control element comprises: data-signal end, the first control end that connects the first switch S 1 and the 4th switch S 4 grids, the second control end, the 4th, the 5th that connects second switch S2 and the 3rd switch S 3 grids, the 6th NMOS pipe, the 4th PMOS pipe, wherein
The 4th NMOS tube grid connects first and gate output terminal, and drain electrode connects second, third and input of door and an end of latch, source ground;
The 5th NMOS tube grid connects the data-signal end, and drain electrode connects the other end of latch, source ground;
The 6th NMOS tube grid connects the second control end, and drain electrode connects second switch grid, source ground;
The 4th gate pmos utmost point connects the first control end, and drain electrode connects power end, and source electrode connects the first switch gate;
The data-signal end connect the 3rd with another input of door, also connect the input of the second not gate;
The output of the second not gate connect second with another input of door, also connect first with an input of door;
First is connected the output of the first not gate with another input of door, and the input of the first not gate connects described common port;
Second with the door described the first control end of output termination;
The 3rd with the input of output termination the 3rd not gate of door, described the second control end of the output termination of the 3rd not gate.
7. method that limits interface circuit output end voltage Slew Rate, it is characterized in that: with the first switch S 1 of current source I1 series connection, is connected the 4th switch S 4 of PMOS pipe T1 grid, with the second switch S2 of the heavy I2 series connection of electric current and be connected the on off operating mode that a NMOS manages the 3rd switch S 3 of T2 grid and controlled three states of this logic control element control switch generation by a logic control element:
Low state is controlled the first switch S 1 and 4 conductings of the 4th switch S, second switch S2 and 3 cut-offs of the 3rd switch S, so that PMOS pipe T1 cut-off, NMOS pipe T2 conducting, the interface circuit output end voltage is drop-down;
High state is controlled the first switch S 1 and 4 cut-offs of the 4th switch S, second switch S2 and 3 conductings of the 3rd switch S, so that PMOS pipe T1 conducting, NMOS pipe T2 cut-off is drawn on the interface circuit output end voltage;
High-impedance state is controlled the first switch S 1, second switch S2, the 3rd switch S 3,4 cut-offs of the 4th switch S, so that PMOS pipe T1 and NMOS pipe T2 cut-off, the interface circuit output is kept high potential.
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| CN104467796A (en) * | 2014-11-07 | 2015-03-25 | 深圳市国微电子有限公司 | Slew-rate-limited driver |
| CN104980140A (en) * | 2015-03-04 | 2015-10-14 | 广东顺德中山大学卡内基梅隆大学国际联合研究院 | Analog multipurpose multiplexer |
| CN106844274A (en) * | 2016-12-26 | 2017-06-13 | 龙迅半导体（合肥）股份有限公司 | A kind of auxiliary circuit of I2C buses |
| CN108132903A (en) * | 2018-01-19 | 2018-06-08 | 杭州士兰微电子股份有限公司 | Universal input/output interface circuit and its control method |
| CN109756223A (en) * | 2017-11-03 | 2019-05-14 | 三星电子株式会社 | Interface circuit and interface arrangement |
| WO2020047722A1 (en) * | 2018-09-03 | 2020-03-12 | 深圳市汇顶科技股份有限公司 | Data interface, chip and chip system |
| CN111936949A (en) * | 2020-03-25 | 2020-11-13 | 深圳市汇顶科技股份有限公司 | Driving circuit and related chip |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101114421A (en) * | 2006-07-26 | 2008-01-30 | 松下电器产业株式会社 | Output driver and diplay device |
| CN101662271A (en) * | 2008-06-17 | 2010-03-03 | 成都芯源系统有限公司 | Switched capacitor circuit and negative feedback circuit thereof |
| CN102034540A (en) * | 2009-09-27 | 2011-04-27 | 上海宏力半导体制造有限公司 | Slew rate control device and method |
| CN102035371A (en) * | 2009-10-02 | 2011-04-27 | 电力集成公司 | Method and apparatus for implementing slew rate control using bypass capacitor |
| CN102186130A (en) * | 2011-02-23 | 2011-09-14 | 启攀微电子（上海）有限公司 | Slew rate control driving circuit |
| CN102385410A (en) * | 2011-11-22 | 2012-03-21 | 电子科技大学 | Slew-rate enhancement circuit and LDO integrating same |
| CN102420522A (en) * | 2010-09-28 | 2012-04-18 | 英特赛尔美国股份有限公司 | System and method for open loop modulation to detect narrow PWM pulse |
-
2012
- 2012-12-18 CN CN201210549722.3A patent/CN103066988B/en not_active Expired - Fee Related
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101114421A (en) * | 2006-07-26 | 2008-01-30 | 松下电器产业株式会社 | Output driver and diplay device |
| CN101662271A (en) * | 2008-06-17 | 2010-03-03 | 成都芯源系统有限公司 | Switched capacitor circuit and negative feedback circuit thereof |
| CN102034540A (en) * | 2009-09-27 | 2011-04-27 | 上海宏力半导体制造有限公司 | Slew rate control device and method |
| CN102035371A (en) * | 2009-10-02 | 2011-04-27 | 电力集成公司 | Method and apparatus for implementing slew rate control using bypass capacitor |
| CN102420522A (en) * | 2010-09-28 | 2012-04-18 | 英特赛尔美国股份有限公司 | System and method for open loop modulation to detect narrow PWM pulse |
| CN102186130A (en) * | 2011-02-23 | 2011-09-14 | 启攀微电子（上海）有限公司 | Slew rate control driving circuit |
| CN102385410A (en) * | 2011-11-22 | 2012-03-21 | 电子科技大学 | Slew-rate enhancement circuit and LDO integrating same |
Cited By (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104009462A (en) * | 2014-06-10 | 2014-08-27 | 福建师范大学 | Communication interface adaptive circuit of self-adaptation level |
| CN104467796A (en) * | 2014-11-07 | 2015-03-25 | 深圳市国微电子有限公司 | Slew-rate-limited driver |
| CN104980140A (en) * | 2015-03-04 | 2015-10-14 | 广东顺德中山大学卡内基梅隆大学国际联合研究院 | Analog multipurpose multiplexer |
| CN104980140B (en) * | 2015-03-04 | 2018-03-13 | 广东顺德中山大学卡内基梅隆大学国际联合研究院 | The multi-purpose multiplexer of one kind simulation |
| CN106844274A (en) * | 2016-12-26 | 2017-06-13 | 龙迅半导体（合肥）股份有限公司 | A kind of auxiliary circuit of I2C buses |
| CN106844274B (en) * | 2016-12-26 | 2019-08-30 | 龙迅半导体（合肥）股份有限公司 | A kind of auxiliary circuit of I2C bus |
| CN109756223A (en) * | 2017-11-03 | 2019-05-14 | 三星电子株式会社 | Interface circuit and interface arrangement |
| CN109756223B (en) * | 2017-11-03 | 2023-06-27 | 三星电子株式会社 | Interface circuit and interface device |
| CN108132903A (en) * | 2018-01-19 | 2018-06-08 | 杭州士兰微电子股份有限公司 | Universal input/output interface circuit and its control method |
| WO2020047722A1 (en) * | 2018-09-03 | 2020-03-12 | 深圳市汇顶科技股份有限公司 | Data interface, chip and chip system |
| CN111936949A (en) * | 2020-03-25 | 2020-11-13 | 深圳市汇顶科技股份有限公司 | Driving circuit and related chip |
| WO2021189282A1 (en) * | 2020-03-25 | 2021-09-30 | 深圳市汇顶科技股份有限公司 | Drive circuit and related chip |
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