CN103066988B - Interface circuit and achievement method for limiting output port voltage slew rate - Google Patents
Interface circuit and achievement method for limiting output port voltage slew rate Download PDFInfo
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Abstract
The invention discloses an interface circuit and achievement method for limiting output port voltage slew rate. The interface circuit and achievement method for limiting output port voltage slew rate comprise a first switch and a second switch respectively connected with a current source and a current sink in series, a first P-channel Metal Oxide Semiconductor (PMOS) pipe and a first N-channel metal oxide semiconductor (NMOS) pipe which are sequentially in series connection and arranged between a power and ground, a third switch connected with a gate electrode of the first PMOS pipe and a fourth switch connected with a gate electrode of the first NMOS pipe, wherein the connection point of the first PMOS pipe and the first NMOS pipe acts as an output port of the interface circuit; a current source branch and a current sink branch are connected on the position of a public port, and the public port is connected with the other end of the third switch and the fourth switch; an in-chip capacitor is connected between the public port and the output end. The interface circuit limiting output port voltage slew rate and achievement method further comprise a logic control unit respectively connected with control electrodes of the first switch, the second switch, the third switch and the fourth switch to control on-off of the control electrodes. The interface circuit and achievement method for limiting output port voltage slew rate can effectively limit voltage slew rates and output current of the output port of the interface circuit, and play roles of decreasing electro-magnetic interference (EMI), protecting the interface circuit and improving transmission rates of the interface circuit.
Description
Technical field
The present invention relates to the interface circuit of transmission data, particularly relate to a kind of interface circuit and its implementation of limiting output end voltage Slew Rate.
Background technology
Interface circuit is vitals indispensable in transfer of data, in the application of interface circuit, if with traditional inverter drive output port, when low and high level switches, also exists and exports the excessive situation of transient current.If without restriction, such current break can worsen the EMI characteristic of interface circuit, and excessive electric current also may damage the output device of interface circuit.Common restriction way is a resistive elements of connecting in output device; Or only adopt a pull-up pull down resistor as output device, play pullup or pulldown, play the effect of current limliting and deboost Slew Rate simultaneously.But series connection resistive elements or signal when only adopting upper pull down resistor then can affect interface circuit transmission data rise or fall off rate, are unfavorable for being used in the occasion had higher requirements to transmission rate.
Summary of the invention
The present invention will solve the demand that existing interface circuit can not take into account deboost Slew Rate and high transfer rate, and proposing one can deboost Slew Rate and output current, has again the circuit of high data rate.
For solving the problems of the technologies described above, the technical scheme that the present invention proposes is a kind of interface circuit limiting output end voltage Slew Rate of design, it comprises: a current source I1, an electric current sinks I2, the first switch S 1, second switch S2 that the I2 that sinks with current source I1, electric current respectively connects, be serially connected in the first PMOS T1 between power supply and ground and the first NMOS tube T2 successively, connect the 3rd switch S 3 of the first PMOS T1 grid, connect the tie point of the 4th switch S 4, first PMOS T1 and the first NMOS tube T2 of the first NMOS tube T2 grid as interface circuit output; Current source I1 branch road and electric current sink I2 branch road and are connected at common port place, and this common port connects the other end of the 3rd switch S 3 and the 4th switch S 4; Electric capacity Cin in a sheet is connected between this common port with output; Also comprise and control that pole is connected, to control the logic control element of its break-make respectively with the first switch S 1, second switch S2, the 3rd switch S 3 and the 4th switch S 4.
The type of described interior electric capacity Cin includes but not limited to the capacitor that the based semiconductor integrated circuit technology such as CMOS capacitor, metal-dielectric metal capacitor, polycrystalline-medium-polycrystalline capacitor realizes.
The order that described first switch S 1 is connected with current source I1 is arbitrary, and current source I1 can be connected on any one end at the first switch S 1 two ends; It is that arbitrary electric current sinks I2 and can be connected on any one end at second switch S2 two ends that second switch S2 and electric current sink order that I2 connects.
Described first switch S 1 adopts PMOS, and second switch S2 adopts NMOS tube, and the 3rd switch S 3 and the 4th switch S 4 adopt cmos transmission gate; The grid of the first switch S 1 and the 4th switch S 4 links together, and the grid of second switch S2 and the 3rd switch S 3 links together.
Interface circuit also to comprise in sheet electric current in current source and sheet and sinks, and is serially connected in the pull-up resistor between power supply and output; Described current source I1 by second and the 3rd PMOS form, the second PMOS is serially connected between the first switch S 1 and common port, in its grid contact pin electric current sink; 3rd PMOS to be serially connected in the first switch S 1 and sheet electric current heavy between, in its grid contact pin, electric current sinks; The tie point of the 3rd PMOS and the first switch S 1 connects power supply; Described electric current sink I2 by second and the 3rd NMOS tube form, the second NMOS tube is serially connected between second switch S2 and common port, current source in its grid contact pin; 3rd NMOS tube is serially connected in second switch S2 and sheet between current source, current source in its grid contact pin; The tie point ground connection of the 3rd NMOS tube and second switch S2.
Described logic control element comprises: data signal end, connect the first switch S 1 and the 4th switch S 4 grid the first control end, be connected second switch S2 and the 3rd switch S 3 grid the second control end, the 4th, the 5th, the 6th NMOS tube, the 4th PMOS, wherein the 4th NMOS tube grid connects first and gate output terminal, drain electrode connects second, third and an input of door and one end of latch, source ground; 5th NMOS tube grid connects data signal end, and drain electrode connects the other end of latch, source ground; 6th NMOS tube grid connects the second control end, and drain electrode connects second switch grid, source ground; 4th PMOS grid connects the first control end, and drain electrode connects power end, and source electrode connects the first switch gate; Data signal end connects another input of the 3rd and door, also connects the input of the second not gate; The output of the second not gate connects another input of second and door, also connects an input of first and door; First is connected the output of the first not gate with another input of door, and the input of the first not gate connects described common port; Second with the first control end described in the output termination of door; 3rd with the input of output termination the 3rd not gate of door, the second control end described in the output termination of the 3rd not gate.
The present invention also proposes a kind of method limiting interface circuit output end voltage Slew Rate: first switch S 1 of connecting with current source I1, connect the 3rd switch S 3 of the first PMOS T1 grid, the second switch S2 that I2 connects is sunk with electric current, and the on off operating mode of the 4th switch S 4 connecting the first NMOS tube T2 grid is controlled by a logic control element, this logic control element control switch produces three states: low state, control the first switch S 1 and the 4th switch S 4 conducting, second switch S2 and the 3rd switch S 3 are ended, make the first PMOS T1 cut-off, first NMOS tube T2 conducting, interface circuit output end voltage is drop-down, high state, controls the first switch S 1 and the 4th switch S 4 is ended, second switch S2 and the 3rd switch S 3 conducting, makes the first PMOS T1 conducting, the first NMOS tube T2 cut-off, interface circuit output end voltage pull-up, high-impedance state, control the first switch S 1, second switch S2, the 3rd switch S 3, the 4th switch S 4 end, the first PMOS T1 and the first NMOS tube T2 is ended, and interface circuit output maintains high potential.
Compared with prior art, the present invention limits the voltage Slew Rate of interface circuit output port simply and effectively, plays the effect reducing EMI and protection interface circuit and raising interface circuit transmission rate; The voltage Slew Rate of interface circuit output and the electric current of output driver part can be set, select that there are three kinds of state of switch control logics simultaneously, interface circuit transmission rate can be improved while meeting half-duplex operation needs.
Accompanying drawing explanation
Below in conjunction with drawings and Examples, the present invention is described in detail, wherein:
Fig. 1 is circuit theory diagrams of the present invention;
Fig. 2 is comparing of the voltage waveform of voltage waveform and the drop-down device transmission on resistive elements current limliting or resistance that output of the present invention exports;
Fig. 3 is the circuit diagram of present pre-ferred embodiments major loop;
Fig. 4 is the circuit diagram of present pre-ferred embodiments logic control element;
Fig. 5 is the flow chart that data are transmitted in the present invention.
Embodiment
A kind of interface circuit limiting output end voltage Slew Rate, referring to the circuit theory shown in Fig. 1, it comprises: a current source I1, an electric current sinks I2, the first switch S 1, second switch S2 that the I2 that sinks with current source I1, electric current respectively connects, be serially connected in the first PMOS T1 between power supply and ground and the first NMOS tube T2 successively, connect the 3rd switch S 3 of the first PMOS T1 grid, connect the tie point of the 4th switch S 4, first PMOS T1 and the first NMOS tube T2 of the first NMOS tube T2 grid as interface circuit output; Current source I1 branch road and electric current sink I2 branch road and are connected at common port A place, and this common port connects the other end of the 3rd switch S 3 and the 4th switch S 4; Electric capacity Cin in a sheet is connected between this common port with output; Also comprise and control that pole is connected, to control the logic control element of its break-make respectively with the first switch S 1, second switch S2, the 3rd switch S 3 and the 4th switch S 4.
In upper example, current source I1, the first switch S 1, the 4th switch S 4, first NMOS tube T2 form current source branch, and S1, S4, T2 action is synchronous; Electric current sinks I2, second switch S2, the 3rd switch S 3, first PMOS T1 and forms electric current and sink branch road, and S2, S3, T1 action is synchronous.The action of logic control element 101 control S1 to S4, logic control element can control switch three kinds of states.In Fig. 1, output B(also claims output port), after carrying out plug grafting, meeting brace outer electric capacity Cout, Cout comprises all electric capacity on output port.When transmitting high level, logic control element control switch S2 and S3 conducting, make T2 conducting, VDD charges to output port B, but due to the existence of internal capacitance Cin, the Slew Rate of the voltage rise of output port is restricted to I1/Cin, and when Cout is not very large, the current value flowing out PMOS T1 equals I1*Cout/Cin.When transmitting low level, logic control element control switch S1 and S4 conducting, make T2 conducting, output port discharges over the ground, and the Slew Rate of the voltage drop of output port is restricted to I2/Cin, and the current value flowing into T2 equals I2*Cout/Cin.
Prior art adopts the method for series connection resistive elements current limliting, if the resistance sum of series resistance and output device is R, supply voltage is VDD, then the maximum current of output device is VDD/R; Maximum Slew Rate is VDD/ (R*Cout), and voltage Slew Rate after this reduces gradually with time constant R*Cout.The interface circuit realized for usually directly adopting pullup or pulldown resistance, has identical conclusion.And during the method adopting the present invention to propose, maximum voltage Slew Rate is determined by I1/Cin (or I2/Cin), if this value be taken as with above-mentioned VDD/ (R*Cout) consistent, then this value can keep certain before T1 (or T2) enters linear zone always.This means, compared to the former, this method can realize voltage rise (or decline) speed faster, thus can realize interface circuit message transmission rate faster.
When realizing half-duplex operation, usual interface circuit transmission high level needs a pull-up resistor, transmission high level and keep the state of interface end and don't affect the reception of the other side's handshake.The speed of interface communication can be had influence on according to the method that above-mentioned analysis is such.When adopting of the present invention, by the on off state control logic control unit 101 of a tri-state, the needs meeting half-duplex operation ensure again the transmission rate of interface.
In Fig. 2, the Slew Rate of the output voltage of the present invention and available circuit is contrasted.Upper part waveform is the output waveform of interface circuit of the present invention, and climbing speed and fall off rate are fixed approx.And lower part adopts the interface end voltage waveform of drop-down realization on resistive elements current limliting or resistance.When maximum climbing speed is the same with fall off rate, the rise time 201 is shorter than the rise time 202, and fall time 203 is shorter than fall time 204.Namely, when maximum climbing speed is the same with fall off rate, the interface circuit adopting the present invention to realize can improve message transmission rate.
It may be noted that the order that the first switch S 1 is connected with current source I1 is arbitrary, in Fig. 1, current source I1 is above S1, and in other embodiments, current source I1 is in the below of S1.It is also arbitrary that second switch S2 and electric current sink the order that I2 connects, and in Fig. 1, electric current sinks the below of I2 at S2, and in other embodiments, electric current sinks I2 above S2.
In the preferred embodiment, the first switch S 1 adopts PMOS, and second switch S2 adopts NMOS tube, and the 3rd switch S 3 and the 4th switch S 4 adopt cmos transmission gate; The grid of the first switch S 1 and the 4th switch S 4 links together, and the grid of second switch S2 and the 3rd switch S 3 links together.In the present embodiment, a grid controlling pin and connect S1 and S4 of logic control element, S1 and S4 synchronization action; Another of logic control element controls pin connection S2 and S3, S2 and S3 synchronization action.
Referring to Fig. 3, interface also to comprise in sheet electric current heavy 321 in current source 320 and sheet in the preferred embodiment, is serially connected in the pull-up resistor 307 between power vd D and output B; Described current source I1 by second and the 3rd PMOS 304 form, the second PMOS 302 is serially connected between the first switch S 1 and common port A, electric current heavy 321 in its grid contact pin; 3rd PMOS 304 is serially connected in the first switch S 1 and sheet between electric current heavy 321, electric current heavy 321 in its grid contact pin; The tie point of the 3rd PMOS 304 and the first switch S 1 connects power supply.Described electric current sink I2 by second and the 3rd NMOS tube 305 form, the second NMOS tube 303 is serially connected between second switch S2 and common port A, current source 320 in its grid contact pin; 3rd NMOS tube 305 is serially connected in second switch S2 and sheet between current source 320, current source 320 in its grid contact pin; The tie point ground connection of the 3rd NMOS tube 305 and second switch S2.Second PMOS 302 and the 3rd PMOS 304 partner current mirror efferent duct, and 302 as current source, and image current size is I1.Second NMOS tube 303 and the 3rd NMOS tube 305 form another to current mirror efferent duct, and 303 sink as electric current, and image current size is that to sink the tie point of branch road be A for I2 current source and electric current; In this example, in sheet, electric capacity adopts the CMOS electric capacity of source-drain electrode short circuit because can saving chip area simultaneously again can when change in voltage holding capacitor stable.Capacitor type includes but not limited to that the capacitor that the based semiconductor integrated circuit technology such as CMOS capacitor, metal-dielectric metal capacitor, polycrystalline-medium-polycrystalline capacitor realizes all can.
Below in conjunction with Fig. 3, the transmitting procedure of preferred embodiment is further described: when transmitting low level, PHASE-L is low, PHASE-H is low, S1 and S4 conducting, current source charges to Cin, T2 conducting is by drop-down for output current potential, but the highest I1/Cin that is restricted to of voltage decreasing rate, the electric current flowing through T2 is I1*Cout/Cin.When transmitting high level, PHASE-H is high, and PHASE-L is high, S2 and S3 conducting, and electric current is heavy, and to Cin charging, T1 conducting is by output current potential pull-up, but the highest I2/Cin that is restricted to of climbing speed, the electric current flowing through T1 is I2*Cout/Cin; After completing pull-up, revert to low by logic control element control PHASE-H, PHASE-L is high, and now T1 and T2 is high-impedance state, keeps output high level by pull-up resistor 307; Indeed achieve the quick active pull up of output like this.
Fig. 4 shows the circuit diagram of logic control element in preferred embodiment, it comprises: data signal end Data, connect the first switch S 1 and the first control end PHASE-L of the 4th switch S 4 grid, the second control end PHASE-H being connected second switch S2 and the 3rd switch S 3 grid, the 4th NMOS tube 409, the 5th NMOS tube 410, the 6th NMOS tube 411, the 4th PMOS 402, wherein the 4th NMOS tube 409 grid connects first and door 406 output, drain electrode connects second, third and an input of door and one end of latch 403, source ground; 5th NMOS tube grid 410 meets data signal end Data, and drain electrode connects the other end of latch 403, source ground; 6th NMOS tube grid meets the second control end PHASE-L, and drain electrode connects second switch grid, source ground; 4th PMOS 402 grid meets the first control end PHASE-H, and drain electrode connects power end, and source electrode connects the first switch T1 grid; Data signal end Data connects another input of the 3rd and door 407, also connects the input of the second not gate 404; The output of the second not gate 404 connects another input of second and door 408, also connects an input of first and door 406; First is connected the output of the first not gate 401 with another input of door, and the input of the first not gate 401 connects described common port A; Second with the first control end PHASE-H described in the output termination of door 408; 3rd with the input of output termination the 3rd not gate 405 of door 407, the second control end PHASE-L described in the output termination of the 3rd not gate 405.
Below in conjunction with Fig. 4, the course of work of logic control element is further described: logic control element, according to the state of data-signal Data and common port A, produces switch controlling signal PHASE-H, PHASE-L.When transmitting low level, Data receives high level, and PHASE-H, PHASE-L are low level; When transmitting high level, Data receives low level, and because latch 403 keeps original state, PHASE-H, PHASE-L are all converted to high level, and now T1 completes pull-up process.In the process completing pull-up, A point current potential can reduce gradually, during lower than certain value, can think that pull-up completes, judge that pull-up completes by the inverter 401 of a lower threshold level, when 401 export high, latch 403 State Transferring, it is low for putting PHASE-H, and PHASE-L is high.And PHASE-H is when being low, the 4th PMOS 402 conducting, makes T1 grid potential raise, and T1 cut-off keeps high-impedance state; When PHASE-L is high, the 6th NMOS tube 411 conducting, makes T2 grid potential reduce, and T2 cut-off keeps high-impedance state.This completes the conversion of " high " state to high-impedance state of pull-up.
Present invention further teaches a kind of method limiting interface circuit output end voltage Slew Rate: the on off operating mode of first switch S 1 of connecting with current source I1, the 3rd switch S 3 being connected the first PMOS T1 grid, second switch S2 that the I2 that to sink with electric current connects and the 4th switch S 4 that is connected the first NMOS tube T2 grid is controlled by a logic control element.Referring to the transmitting data stream journey figure shown in Fig. 5, logic control element control switch produces three states:
First interface circuit output is in high-impedance state, can receive data or send data, being determined by a control signal;
When being in accepting state, transmitting portion continues to keep high-impedance state, and namely output keeps high-impedance state;
When being in transmission state, need to transmit low level, logic control element sends low state, control the first switch S 1 and the 4th switch S 4 conducting, second switch S2 and the 3rd switch S 3 are ended, make the first PMOS T1 cut-off, first NMOS tube T2 conducting, interface circuit output end voltage is drop-down, namely limits Slew Rate drop-down;
When being in transmission state, need to transmit high level, logic control element sends high state, control the first switch S 1 and the 4th switch S 4 is ended, second switch S2 and the 3rd switch S 3 conducting, make the first PMOS T1 conducting, first NMOS tube T2 cut-off, interface circuit output end voltage pull-up, namely limits Slew Rate pull-up;
Logic control element detects that pull-up completes, and sends high-impedance state, and control the first switch S 1, second switch S2, the 3rd switch S 3, the 4th switch S 4 end, the first PMOS T1 and the first NMOS tube T2 is ended, and interface circuit output maintains high potential.
Judge whether transmission completes according to the communications protocol of interface, decision receives or continue to send data later.Can see that this state controls to improve in the demand meeting interface circuit half-duplex operation the transmission rate of interface simultaneously by this process.
Above embodiment is only and illustrates, non-ly provides constraints.Anyly do not depart from the application's spirit and category, and to its equivalent modifications of carrying out or change, among the right that all should be contained in the application.
Claims (6)
1. one kind limits the interface circuit of output end voltage Slew Rate, it is characterized in that comprising: a current source I1, an electric current sinks I2, the first switch S 1, second switch S2 that the I2 that sinks with current source I1, electric current respectively connects, be serially connected in the first PMOS T1 between power supply and ground and the first NMOS tube T2 successively, connect the 3rd switch S 3 of the first PMOS T1 grid, connect the tie point of the 4th switch S 4, first PMOS T1 and the first NMOS tube T2 of the first NMOS tube T2 grid as interface circuit output; Current source I1 branch road and electric current sink I2 branch road and are connected at common port place, and this common port connects the other end of the 3rd switch S 3 and the 4th switch S 4; Electric capacity Cin in a sheet is connected between this common port with output; Also comprise and control that pole is connected, to control the logic control element of its break-make respectively with the first switch S 1, second switch S2, the 3rd switch S 3 and the 4th switch S 4;
Described first switch S 1 adopts PMOS, and second switch S2 adopts NMOS tube, and the 3rd switch S 3 and the 4th switch S 4 adopt cmos transmission gate; The grid of the first switch S 1 and the 4th switch S 4 links together, and the grid of second switch S2 and the 3rd switch S 3 links together.
2. interface circuit as claimed in claim 1, it is characterized in that, the capacitor that type includes but not limited to CMOS capacitor, metal-dielectric metal capacitor, polycrystalline-medium-polycrystalline capacitor based semiconductor integrated circuit technology realizes of described interior electric capacity Cin.
3. interface circuit as claimed in claim 1, it is characterized in that, the order that described first switch S 1 is connected with current source I1 is arbitrary, and it is arbitrary that second switch S2 and electric current sink the order that I2 connects.
4. interface circuit as claimed in claim 1, is characterized in that, also to comprise in sheet electric current in current source and sheet and sinks, be serially connected in the pull-up resistor between power supply and output;
Described current source I1 by second and the 3rd PMOS form, the second PMOS is serially connected between the first switch S 1 and common port, in its grid contact pin electric current sink; 3rd PMOS to be serially connected in the first switch S 1 and sheet electric current heavy between, in its grid contact pin, electric current sinks; The tie point of the 3rd PMOS and the first switch S 1 connects power supply;
Described electric current sink I2 by second and the 3rd NMOS tube form, the second NMOS tube is serially connected between second switch S2 and common port, current source in its grid contact pin; 3rd NMOS tube is serially connected in second switch S2 and sheet between current source, current source in its grid contact pin; The tie point ground connection of the 3rd NMOS tube and second switch S2.
5. interface circuit as claimed in claim 4, it is characterized in that, described logic control element comprises: data signal end, connect the first switch S 1 and the 4th switch S 4 grid the first control end, be connected second switch S2 and the 3rd switch S 3 grid the second control end, the 4th, the 5th, the 6th NMOS tube, the 4th PMOS, wherein
4th NMOS tube grid connects first and gate output terminal, and drain electrode connects second, third and an input of door and one end of latch, source ground;
5th NMOS tube grid connects data signal end, and drain electrode connects the other end of latch, source ground;
6th NMOS tube grid connects the second control end, and drain electrode connects second switch grid, source ground;
4th PMOS grid connects the first control end, and drain electrode connects power end, and source electrode connects the first switch gate;
Data signal end connects another input of the 3rd and door, also connects the input of the second not gate;
The output of the second not gate connects another input of second and door, also connects an input of first and door;
First is connected the output of the first not gate with another input of door, and the input of the first not gate connects described common port;
Second with the first control end described in the output termination of door;
3rd with the input of output termination the 3rd not gate of door, the second control end described in the output termination of the 3rd not gate.
6. one kind limits the method for interface circuit output end voltage Slew Rate, it is characterized in that: the on off operating mode of first switch S 1 of connecting with current source I1, the 3rd switch S 3 being connected the first PMOS T1 grid, second switch S2 that the I2 that to sink with electric current connects and the 4th switch S 4 that is connected the first NMOS tube T2 grid is controlled by a logic control element, and this logic control element control switch produces three states:
Low state, controls the first switch S 1 and the 4th switch S 4 conducting, second switch S2 and the 3rd switch S 3 are ended, and make the first PMOS T1 cut-off, the first NMOS tube T2 conducting, interface circuit output end voltage is drop-down;
High state, controls the first switch S 1 and the 4th switch S 4 is ended, second switch S2 and the 3rd switch S 3 conducting, makes the first PMOS T1 conducting, the first NMOS tube T2 cut-off, interface circuit output end voltage pull-up;
High-impedance state, control the first switch S 1, second switch S2, the 3rd switch S 3, the 4th switch S 4 end, the first PMOS T1 and the first NMOS tube T2 is ended, and interface circuit output maintains high potential.
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| CN104009462B (en) * | 2014-06-10 | 2016-08-31 | 福建师范大学 | A kind of communication interface adapter circuit of self-adaptive level |
| CN104467796B (en) * | 2014-11-07 | 2017-09-08 | 深圳市国微电子有限公司 | One kind limit Slew Rate driver |
| CN104980140B (en) * | 2015-03-04 | 2018-03-13 | 广东顺德中山大学卡内基梅隆大学国际联合研究院 | The multi-purpose multiplexer of one kind simulation |
| CN106844274B (en) * | 2016-12-26 | 2019-08-30 | 龙迅半导体（合肥）股份有限公司 | A kind of auxiliary circuit of I2C bus |
| US10516389B2 (en) * | 2017-11-03 | 2019-12-24 | Samsung Electronics Co., Ltd. | Interface circuit and interface device |
| CN108132903B (en) * | 2018-01-19 | 2024-08-06 | 杭州士兰微电子股份有限公司 | General input/output interface circuit and control method thereof |
| CN109314515A (en) * | 2018-09-03 | 2019-02-05 | 深圳市汇顶科技股份有限公司 | Data-interface, chip and chip system |
| CN111936949A (en) * | 2020-03-25 | 2020-11-13 | 深圳市汇顶科技股份有限公司 | Driving circuit and related chip |
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| CN102035371A (en) * | 2009-10-02 | 2011-04-27 | 电力集成公司 | Method and apparatus for implementing slew rate control using bypass capacitor |
| CN102186130A (en) * | 2011-02-23 | 2011-09-14 | 启攀微电子（上海）有限公司 | Slew rate control driving circuit |
| CN102385410A (en) * | 2011-11-22 | 2012-03-21 | 电子科技大学 | Slew-rate enhancement circuit and LDO integrating same |
| CN102420522A (en) * | 2010-09-28 | 2012-04-18 | 英特赛尔美国股份有限公司 | System and method for open loop modulation to detect narrow PWM pulse |
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2012
- 2012-12-18 CN CN201210549722.3A patent/CN103066988B/en not_active Expired - Fee Related
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| CN101114421A (en) * | 2006-07-26 | 2008-01-30 | 松下电器产业株式会社 | Output driver and diplay device |
| CN101662271A (en) * | 2008-06-17 | 2010-03-03 | 成都芯源系统有限公司 | Switched capacitor circuit and negative feedback circuit thereof |
| CN102034540A (en) * | 2009-09-27 | 2011-04-27 | 上海宏力半导体制造有限公司 | Slew rate control device and method |
| CN102035371A (en) * | 2009-10-02 | 2011-04-27 | 电力集成公司 | Method and apparatus for implementing slew rate control using bypass capacitor |
| CN102420522A (en) * | 2010-09-28 | 2012-04-18 | 英特赛尔美国股份有限公司 | System and method for open loop modulation to detect narrow PWM pulse |
| CN102186130A (en) * | 2011-02-23 | 2011-09-14 | 启攀微电子（上海）有限公司 | Slew rate control driving circuit |
| CN102385410A (en) * | 2011-11-22 | 2012-03-21 | 电子科技大学 | Slew-rate enhancement circuit and LDO integrating same |
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| CN103066988A (en) | 2013-04-24 |
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