CN104716938A - Grating following input and output circuit - Google Patents
Grating following input and output circuit Download PDFInfo
- Publication number
- CN104716938A CN104716938A CN201310689170.0A CN201310689170A CN104716938A CN 104716938 A CN104716938 A CN 104716938A CN 201310689170 A CN201310689170 A CN 201310689170A CN 104716938 A CN104716938 A CN 104716938A
- Authority
- CN
- China
- Prior art keywords
- pmos
- nmos tube
- grid
- output
- circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000000758 substrate Substances 0.000 claims abstract description 53
- 238000007667 floating Methods 0.000 claims abstract description 25
- 239000004065 semiconductor Substances 0.000 claims description 34
- 230000003068 static effect Effects 0.000 claims description 11
- 230000008859 change Effects 0.000 abstract description 13
- 238000000034 method Methods 0.000 description 8
- 102100037224 Noncompact myelin-associated protein Human genes 0.000 description 6
- 101710184695 Noncompact myelin-associated protein Proteins 0.000 description 6
- 238000005516 engineering process Methods 0.000 description 5
- 230000015572 biosynthetic process Effects 0.000 description 4
- 230000002093 peripheral effect Effects 0.000 description 4
- 238000013461 design Methods 0.000 description 3
- 238000007599 discharging Methods 0.000 description 3
- 230000015556 catabolic process Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000003071 parasitic effect Effects 0.000 description 2
- 230000004044 response Effects 0.000 description 2
- 230000001133 acceleration Effects 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000006731 degradation reaction Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000037361 pathway Effects 0.000 description 1
- 230000002265 prevention Effects 0.000 description 1
- 230000008569 process Effects 0.000 description 1
- 230000001105 regulatory effect Effects 0.000 description 1
- 238000012546 transfer Methods 0.000 description 1
Landscapes
- Logic Circuits (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
The invention belongs to the field of integrated circuits and provides a grating following input and output circuit. The grating following input and output circuit is provided with an input and output end, comprises an output pre-stage drive circuit, an output level circuit, an input level circuit and an electrostatic discharge circuit, and further comprises a floating biasing circuit and a grating following circuit. Thus, when an integrated chip is in a receiving mode, the grating following circuit tracks voltage change of the input and output end in real time and adjusts control signals output towards the floating biasing circuit, then, the floating biasing circuit adjusts the voltage of a substrate of an MOS transistor, and therefore the duration of leakage current is effectively shortened.
Description
Technical field
The invention belongs to integrated circuit fields, particularly relate to a kind of grid and follow imput output circuit.
Background technology
Along with the develop rapidly of integrated circuit, the size of space between components and parts reduces gradually, and meanwhile, the operating voltage of integrated circuit also constantly reduces, and reduces the power consumption of integrated chip.But the peripheral circuit of the integrated chip of some low voltage operating or peripheral chip need to work at higher voltages; In order to can proper communication between the chip of satisfied different voltage power supply and circuit, the integrated chip under CMOS technology must solve the voltage compatibility problem of input and output (Input/Output, I/O) pin.The I/O circuit that traditional CMOS technology makes no longer is applicable to mixed voltage system, when the external voltage at I/O pin place is higher than chip internal voltage, can cause reliability of the gate oxide problem, hot carrier degradation and leakage current etc.
As shown in Figure 1, wherein, pre-driver circuitry comprises Enable Pin EN, exports incoming end Dout, the first output PO1 and the second output PO2 the I/O circuit that the integrated chip that traditional CMOS technology is made comprises; Wherein, I/O circuit is at the power vd D operating at voltages of 3.3V, when the I/O circuit that integrated chip comprises is in receiving mode, in order to close pull-up PMOS and pull-down NMOS pipe, pre-driver circuitry must produce bias voltage as shown in Figure 1, namely the first output PO1 of pre-driver circuitry provides 3.3V voltage to the grid of pull-up PMOS, and the grid that the second output PO2 of pre-driver circuitry pulls down NMOS tube provides 0V voltage.Meanwhile, if when the voltage (such as 5V) of the input signal on input/output terminal PAD is higher than 3.3V, PN junction positively biased parasitic between the drain terminal of pull-up PMOS and substrate, forms leakage current path, forms the leakage current Ileak of input/output terminal PAD to substrate; Meanwhile, the voltage difference between the substrate of pull-up PMOS and the power vd D of 3.3V is 1.7V, forms the reverse channel leakage stream of substrate to the power vd D of 3.3V, and then the leakage current of the power vd D of formation input/output terminal PAD to 3.3V.Meanwhile, in pull-down NMOS pipe and input stage circuit MOS device to produce leakage current because its grid voltage is too high even breakdown.
In prior art, providing two kinds of methods for solving the problem, comprising: the first, adopt thick grid technique; The second, the method that N trap sheet is biased outward.For first method, because thick gate device can bear higher gate voltage, by providing higher N trap bias voltage outside sheet, effectively can guarantee that between the drain terminal of pull-up PMOS and substrate, parasitic PN junction is reverse-biased, although method for designing is simple, its design cost is higher.For second method, by increasing extra chip pin outward to provide bias voltage at N trap sheet, keeping this bias voltage higher than the supply voltage in sheet, effectively can improve the bias voltage threshold value of PMOS.
Therefore, the I/O circuit that existing above-mentioned two kinds of methods provide all does not consider that input/output terminal PAD change in voltage is instantaneously on the impact that integrated chip and peripheral circuit cause; Thus the speed that N trap potential follows input/output terminal PAD change in voltage is slow, and needed rise to the voltage of input/output terminal PAD at N trap potential before through longer a period of time, this I/O circuit still exists the problems such as current leakage.Especially, when the change in voltage frequency on input/output terminal PAD is higher, this problem shows even more serious.
Summary of the invention
The object of the present invention is to provide a kind of grid to follow imput output circuit, do not consider that the change in voltage of input/output terminal PAD is instantaneously to the current leakage problem that integrated chip and peripheral circuit cause to solve prior art.
On the one hand, the invention provides a kind of grid and follow imput output circuit, there is input/output terminal, comprise and export pre-driver circuitry, output-stage circuit, input stage circuit and static release circuit 4, also comprise:
Floating bias circuit, the substrate of the metal-oxide-semiconductor comprised with output-stage circuit is connected, and when described input/output terminal is receiving mode, adjusts the voltage of the substrate of described metal-oxide-semiconductor to prevent the leakage current of described input/output terminal to the substrate of described metal-oxide-semiconductor;
Grid follow circuit, the output of input termination output-stage circuit and described input/output terminal, first control end and the second control end connect the controlled end of described floating bias circuit and the controlled end of described output-stage circuit respectively, output and guard signal end connect the input of described input stage circuit and the controlled end of described static release circuit 4 respectively, when described input/output terminal is receiving mode, and the signal of telecommunication of described input/output terminal access is when being changed to low-voltage from high voltage, described input/output terminal is accessed, there is the high-tension signal of telecommunication discharge, according to the voltage control of signal of telecommunication during electric discharge or after electric discharge, floating bias circuit adjusts the voltage of the substrate of described metal-oxide-semiconductor.
Beneficial effect of the present invention: by adding grid follow circuit and floating bias circuit in integrated chip, when integrated chip is in receiving mode, the change in voltage of grid follow circuit real-time tracking input/output terminal, adjust the control signal exported to floating bias circuit, and then floating bias circuit adjusts the voltage of the substrate of described metal-oxide-semiconductor; Wherein, when the voltage of input/output terminal is low-voltage from high-voltage variable, improve grid follow circuit and provide discharge circuit with repid discharge, and then follow the change in voltage of input/output terminal, adjust to floating bias circuit export control signal to adjust the voltage of the substrate of described metal-oxide-semiconductor, effectively reduce the duration of leakage current.
Accompanying drawing explanation
In order to be illustrated more clearly in the technical scheme in the embodiment of the present invention, be briefly described to the accompanying drawing used required in embodiment or description of the prior art below, apparently, accompanying drawing in the following describes is only some embodiments of the present invention, for those of ordinary skill in the art, under the prerequisite not paying creative work, other accompanying drawing can also be obtained according to these accompanying drawings.
Fig. 1 is the schematic diagram comprising the integrated chip of I/O circuit that background technology of the present invention provides;
Fig. 2 is the composition structure chart that grid that the embodiment of the present invention provides follow imput output circuit;
Fig. 3 is the circuit diagram that grid that the embodiment of the present invention provides follow imput output circuit.
Embodiment
In order to make object of the present invention, technical scheme and advantage clearly understand, below in conjunction with drawings and Examples, the present invention is further elaborated.Should be appreciated that specific embodiment described herein only in order to explain the present invention, be not intended to limit the present invention.
In order to technical solutions according to the invention are described, be described below by specific embodiment.
The grid that Fig. 2 shows the embodiment of the present invention to be provided follow the composition structure of imput output circuit, and for convenience of explanation, illustrate only the part relevant to the embodiment of the present invention, details are as follows.
A kind of grid follow imput output circuit, have input/output terminal, comprise and export pre-driver circuitry, output-stage circuit 3, input stage circuit and static release circuit 4, also comprise:
Floating bias circuit 2, the substrate of the metal-oxide-semiconductor comprised with output-stage circuit 3 is connected, and when described input/output terminal is receiving mode, adjusts the voltage of the substrate of described metal-oxide-semiconductor to prevent the leakage current of described input/output terminal to the substrate of described metal-oxide-semiconductor;
Grid follow circuit 1, the output of input termination output-stage circuit 3 and described input/output terminal, first control end and the second control end connect the controlled end of described floating bias circuit 2 and the controlled end of described output-stage circuit 3 respectively, output and guard signal end connect the input of described input stage circuit and the controlled end of described static release circuit 4 respectively, when described input/output terminal is receiving mode, and the signal of telecommunication of described input/output terminal access is when being changed to low-voltage from high voltage, described input/output terminal is accessed, there is the high-tension signal of telecommunication discharge, according to the voltage control of signal of telecommunication during electric discharge or after electric discharge, floating bias circuit 2 adjusts the voltage of the substrate of described metal-oxide-semiconductor.
It should be noted that, described integrated chip comprises input/output terminal PAD, Enable Pin EN, output signal receiving terminal Dout and signal output part (being included in input stage circuit, not shown).When needs export data by integrated chip with electrical signal format, output mode is entered to make the input/output terminal PAD of integrated chip to Enable Pin EN input low level signal, integrated chip is from output signal receiving terminal Dout Received signal strength, this signal, after exporting pre-driver circuitry and output-stage circuit 3, is exported to load circuit by described input/output terminal PAD.
In the present embodiment, only for Enable Pin EN input high level signal, and then export pre-driver circuitry first output PO1 and export high level and (determine according to the design of integrated chip, such as: 3.3V), second output PO2 output low level of described output pre-driver circuitry (determining according to the design of integrated chip, such as: 0V); And then the second PMOS MP2 in input stage circuit and the second NMOS tube MN2 all ends, the described input/output terminal PAD of described integrated chip enters receiving mode.
In the receiving mode, voltage due to the signal of telecommunication inputted from described input/output terminal PAD may be greater than the supply voltage (voltage of power supply OVDD) of powering for described integrated chip, for avoiding the formation of the leakage current of the substrate of the metal-oxide-semiconductor that described input/output terminal PAD comprises in described output-stage circuit 3 (especially: PN junction positively biased, the described input/output terminal PAD formed is to the leakage current of the N trap of PMOS), adopt the voltage detecting the signal of telecommunication that described input/output terminal PAD inputs during grid follow circuit 1 in real time; And then grid follow circuit 1 is according to the voltage swing of the signal of telecommunication detected, the control signal that in real time adjustment is exported to floating bias circuit 2 by the first control end is to adjust the voltage of the substrate of described metal-oxide-semiconductor in real time; Thus, voltage difference between the voltage of the substrate of the voltage of the signal of telecommunication that described input/output terminal PAD inputs and the described metal-oxide-semiconductor after adjusting is not enough to the PN junction forward conduction making to exist between described input/output terminal PAD and the substrate of described metal-oxide-semiconductor, efficiently avoid and form the leakage current of described input/output terminal PAD to the substrate of described metal-oxide-semiconductor, and then input/output terminal PAD can not be formed through the leakage current of this PN junction to power supply (OVDD).
What deserves to be explained is, grid follow circuit 1 includes quick discharging circuit, and then when the voltage (voltage from the signal of telecommunication that input/output terminal PAD inputs) of input/output terminal PAD is very fast more frequent to the change of small voltage from large voltage, the voltage discharging to follow input/output terminal PAD is carried out by this quick discharging circuit, and then the voltage of following input/output terminal PAD produces control signal, and control by this control signal the voltage that floating bias circuit 2 adjusts the substrate of described metal-oxide-semiconductor; Thus the voltage of the substrate of metal-oxide-semiconductor described in the Voltage Cortrol realizing following input/output terminal PAD, further increase regulating the speed of the leakage current stoping the described input/output terminal PAD of formation to the substrate of described metal-oxide-semiconductor, and then improve prevention formation input/output terminal PAD through the response speed of this PN junction to the leakage current of power supply OVDD.
The grid that Fig. 3 shows the embodiment of the present invention to be provided follow the circuit of imput output circuit, and for convenience of explanation, illustrate only the part relevant to the embodiment of the present invention, details are as follows.
Wherein, preferably, described grid follow circuit 1 comprises:
First PMOS MP1, the 3rd NMOS tube MN3, the 4th NMOS tube MN4, the 5th NMOS tube MN5, the 6th NMOS tube MN6, the 7th NMOS tube MN7, the 8th NMOS tube MN8, the 9th NMOS tube MN9, the 14 NMOS tube MN14, the 9th inverter XI9, tenth inverter XI10, the 11 inverter XI11 and the first resistance R1;
The source electrode of described first PMOS MP1 is the input of described grid follow circuit 1, the grid of described first PMOS MP1 and drain electrode connect the grid of power supply and described 4th NMOS tube MN4 respectively, the substrate of described metal-oxide-semiconductor comprises the substrate of described first PMOS MP1, the drain electrode of described first PMOS MP1 is the first control end of described grid follow circuit 1, second control end and guard signal end, the source electrode of described 4th NMOS tube MN4 and drain electrode connect the input of power supply and described 9th inverter XI9 respectively, the source electrode of described 3rd NMOS tube MN3, grid and drain electrode connect the drain electrode of described first PMOS MP1 respectively, the input of power supply and described 9th inverter XI9, the drain electrode of described 5th NMOS tube MN5, grid and source electrode connect the drain electrode of described first PMOS MP1 respectively, the output of described 9th inverter XI9 and the drain electrode of described 7th NMOS tube MN7, the drain electrode of described 6th NMOS tube MN6, grid and source electrode connect the drain electrode of described first PMOS MP1 respectively, the drain electrode of power supply and described 7th NMOS tube MN7, grid and the source electrode of described 7th NMOS tube MN7 connect VDD-to-VSS respectively, the input of described tenth inverter XI10 and output connect the output of described 9th inverter XI9 and the grid of described 8th NMOS tube MN8 respectively, the drain electrode of described 8th NMOS tube MN8 and source electrode connect the drain electrode of described first PMOS MP1 and the drain electrode of described 9th NMOS tube MN9 respectively, the grid of described 9th NMOS tube MN9 and source electrode connect output and the ground of described 11 inverter XI11 respectively, the drain electrode of described 14 NMOS tube MN14, grid and source electrode connect the input of described 11 inverter XI11 respectively, the first end of power supply and described first resistance R1, the drain electrode of described 14 NMOS tube MN14 is the output of described grid follow circuit 1, the source electrode of the first PMOS MP1 described in second termination of described first resistance R1.
In addition, the drain electrode of described first PMOS MP1 connects TG node.The substrate of described metal-oxide-semiconductor connects F node.
Wherein, preferably, described floating bias circuit 2 comprises:
8th PMOS MP8 and the 9th PMOS MP9;
The grid of described 8th PMOS MP8 is the controlled end of described floating bias circuit 2, the drain electrode of described 8th PMOS MP8 and source electrode connect the source electrode of power supply and described 9th PMOS MP9 respectively, the source electrode of described 8th PMOS MP8 and the source electrode of described 9th PMOS MP9 all connect the substrate of described metal-oxide-semiconductor, the substrate of described 8th PMOS MP8 connects the source electrode of described 8th PMOS MP8, the substrate of described 9th PMOS MP9 connects the source electrode of described 9th PMOS MP9, the drain and gate of described 9th PMOS MP9 connects grid and the power supply of described 8th PMOS MP8 respectively.
Wherein, preferably, described static release circuit 4 comprises:
Tenth PMOS MP10, the 11 PMOS MP11, the 12 PMOS MP12, the 15 NMOS tube MN15, the 16 NMOS tube MN16 and the 17 NMOS tube MN17;
Source electrode and the substrate of described 12 PMOS MP12 all connect power supply, the grid of described 12 PMOS MP12 and the grid of drain electrode difference ground connection and described 11 PMOS MP11, the source electrode of described 11 PMOS MP11 and drain electrode connect the source electrode of power supply and the tenth PMOS MP10 respectively, the substrate of described metal-oxide-semiconductor comprises the substrate of described 11 PMOS MP11 and the substrate of described tenth PMOS MP10, the grid of described tenth PMOS MP10 is the controlled end of described static release circuit 4, the drain electrode of described tenth PMOS MP10 connects described input/output terminal, the drain electrode of described 17 NMOS tube MN17, grid and source electrode connect the drain electrode of described tenth PMOS MP10 respectively, the drain electrode of power supply and described 16 NMOS tube MN16, the drain electrode of described 15 NMOS tube MN15, grid and source electrode connect the source electrode of described 16 NMOS tube MN16 respectively, power supply and ground, the source ground of described 16 NMOS tube MN16.
Wherein, preferably, described output-stage circuit 3 comprises:
Second PMOS MP2, the 3rd PMOS MP3, the first NMOS tube MN1 and the second NMOS tube MN2;
The source electrode of described second PMOS MP2, grid and drain electrode connect power supply, first output (PO1) of described output pre-driver circuitry and the source electrode of described 3rd PMOS MP3 respectively, the grid of described 3rd PMOS MP3 is the controlled end of described output-stage circuit 3, the drain electrode of described first NMOS tube MN1, grid and source electrode connect the drain electrode of the drain electrode of described 3rd PMOS MP3, power supply and described second NMOS tube MN2 respectively, and the grid of described second NMOS tube MN2 and source electrode connect the second output PO2 and the ground of described output pre-driver circuitry respectively.
The operation principle of the present embodiment is described below in conjunction with Fig. 2:
When the I/O circuit working of described integrated chip is at input pattern, output enable signal EN is the logic high of 3.3V; And then export the high level that pre-driver circuitry first output PO1 exports 3.3V, the second output PO2 of described output pre-driver circuitry exports the low level of 0V.The second PMOS MP2 in input stage circuit and the second NMOS tube MN2 all ends, and export pre-driver circuitry and make input/output terminal PAD be high-impedance state, the described input/output terminal PAD of described integrated chip enters receiving mode.
Under described input/output terminal PAD is in receiving mode, if input the signal of telecommunication of 5V from input/output terminal PAD, therefore the signal of telecommunication inputted obtains voltage: voltage 3.3V), because the grid of the first PMOS MP1 in grid tracking circuit and source electrode meet power supply OVDD and input/output terminal PAD, the first PMOS MP1 conducting respectively; Meanwhile, because the grid of the 6th NMOS tube MN and the 7th NMOS tube MN7 all meets power supply OVDD, therefore, six NMOS tube MN and the 7th NMOS tube MN7 are in conducting state always; And then the 3rd NMOS tube MN3, the 6th NMOS tube MN6 and the 7th NMOS tube MN7 carry out dividing potential drop to input/output terminal PAD, the voltage on TG node is the voltage after the 6th NMOS tube MN6 and the 7th NMOS tube MN7 connect; It should be noted that, the 6th NMOS tube MN6 and the 7th NMOS tube MN7 all adopts the NMOS tube of long raceway groove (resistance during conducting is still larger), and therefore, TG current potential can be similar to and reach 5V.And then, the tenth PMOS MP10 in output-stage circuit 3 in the 3rd PMOS MP3 and static release circuit 4 all ends, even if the voltage of the signal of telecommunication of input/output terminal PAD is greater than the voltage of power supply OVDD, effectively prevent input/output terminal PAD to form the current path with power supply OVDD through the 3rd PMOS MP3 and/or the tenth PMOS MP10, avoid and produce the leakage current of input/output terminal PAD refluence to power supply OVDD.Meanwhile, the TG node of 5V is connected with the grid of described 8th PMOS MP8, make the 8th PMOS MP8 cut-off in floating bias circuit 2,9th PMOS MP9 conducting, and then charged to F node by TG node, namely TG node by the drain electrode of the 9th PMOS MP9 to the charging of F node, and then the N trap of PMOS (being connected with F node) current potential approximate be also 5V.Wherein, the PMOS such as the 3rd PMOS MP3, the second PMOS MP2, the first PMOS MP1, the tenth PMOS MP10 and the 11 PMOS MP11 are all made in N trap, due to the N trap binding place F of PMOS made at metal-oxide-semiconductor substrate, the high-tension signal of telecommunication on input/output terminal PAD can not make the PN junction forward conduction between the drain electrode of PMOS (meeting input/output terminal PAD) and substrate, prevents and forms the leakage current (namely input/output terminal PAD flows to the leakage current of metal-oxide-semiconductor substrate) that input/output terminal PAD flows to the N trap of PMOS.Meanwhile, TG node is 5V, the 4th NMOS tube MN4 conducting in grid tracking circuit; And then, the input input high level signal (3.3V) of the 9th inverter XI9, output is low level signal; And then the 5th NMOS tube MN5 cut-off, does not impact the current potential of TG node; And then the tenth inverter XI10 exports high level signal; And then the grid of the 8th NMOS tube MN8 is the high level signal of 3.3V, but whether the 8th NMOS tube MN8 conducting also will depend on the 9th NMOS tube MN9 whether conducting.Simultaneously, because input/output terminal is the high level of 5V, and the 14 the grid of NMOS tube MN14 meet power supply OVDD, the input input high level signal of the 11 inverter XI11, output output low level signal, 8th NMOS tube MN9 cut-off, thus MN8 is ended, the current potential of TG node is not impacted.
When voltage less than or equal to power supply OVDD of the voltage of the signal of telecommunication inputted from input/output terminal PAD, the first PMOS MP1 by, the 6th NMOS tube MN6 and the 7th NMOS tube MN7 of conducting are always pulled down to 0V the current potential of TG node; Now, the 9th PMOS MP9 cut-off in floating bias circuit 2, the 8th PMOS MP8 conducting, charges to the magnitude of voltage of power supply OVDD by the N trap potential of the PMOS made on the substrate of metal-oxide-semiconductor, namely F node level is 3.3V; And then the drain electrode of the second NMOS tube MP2, the 3rd NMOS tube MN3, the tenth NMOS tube MP10 or the 11 NMOS tube MP11 all can not to the substrate leakage of metal-oxide-semiconductor.Thus, when the voltage of input/output terminal PAD is less than or equal to power supply OVDD voltage, the second NMOS tube MP2 grid simultaneously in output-stage circuit 3 connects and exports pre-driver circuitry first output PO1 (current potential is 3.3V), second NMOS tube MP2 remain off, whole output-stage circuit 3 is still high-impedance state for PAD.In addition, because the voltage of input/output terminal PAD is less than or equal to power supply OVDD voltage, the conducting of the 14 NMOS tube MN14, can transfer to the signal output part of input stage circuit from the data (signal of telecommunication) of input/output terminal PAD input.
What deserves to be explained is, when the voltage of input/output terminal PAD drops to the process of 0V from 5V, first PMOS MP1 from conducting switch by time, 6th NMOS tube MN6 of long raceway groove and the 7th NMOS tube MN7 needs the level of TG node to be pulled down to 0V, thus produce larger pull-down current, cause the power consumption of whole I/O circuit to raise.For head it off, the drain electrode of the 5th NMOS tube MN5 and source electrode are connected with the drain electrode of the 6th NMOS tube MN6 and source electrode respectively, and then TG node becomes low spot at ordinary times from high level, 3rd NMOS tube MN3 conducting, 9th inverter XI9 receives low level from input and exports high level, and then the 5th NMOS tube MN5 become conducting from cut-off, form TG node to low big current path (electric pathway through the 5th NMOS tube MN5 and the 7th NMOS tube MN7), the decline of acceleration TG node potential.
Separately what deserves to be explained is, for the pull-down circuit that the 8th NMOS tube MN8 and the 9th NMOS tube MN9 is formed, when the voltage constant of input/output terminal PAD, the grid of the 8th NMOS tube MN8 and the grid of the 9th NMOS tube MN9 remain contrary logic level, and pull-down circuit does not work; But, because the grid of input/output terminal PAD to the 8th NMOS tube MN8 is than to grid many Primary Transmit door of the 9th NMOS tube and one-level inverter, and then when input/output terminal PAD level drops to 0V by 5V, potential change time of the grid of the 8th NMOS tube MN8 is than the time of potential change time in recent years Primary Transmit door and the time delay of one-level inverter of the grid of MN9; Within this period of time of delay, the grid of the 8th NMOS tube MN8 and the 9th NMOS tube MN9 is high level simultaneously, and the 8th NMOS tube MN8 and the 9th NMOS tube MN9 conducting simultaneously, pulls down to 0V by the current potential of TG node fast.Therefore, comprise the grid tracking circuit of three road pull-down circuits of the 5th NMOS tube MN5, the 6th NMOS tube MN6, the 7th NMOS tube MN7, the 8th NMOS tube MN8 and the 9th NMOS tube MN9 composition, greatly can improve and TG node is pulled down to low level change slope from high level, then improve the response speed that floating bias circuit 2 follows the change in voltage of described input/output terminal PAD, instant realization, to the level (level of the substrate of metal-oxide-semiconductor) of adjustment F node, effectively prevent the leakage current brought from the change in voltage of the signal of telecommunication of input/output terminal PAD input.
Above content is in conjunction with concrete preferred implementation further description made for the present invention, can not assert that specific embodiment of the invention is confined to these explanations.For general technical staff of the technical field of the invention; make some equivalent alternative or obvious modification without departing from the inventive concept of the premise; and performance or purposes identical, all should be considered as belonging to the scope of patent protection that the present invention is determined by submitted to claims.
Claims (5)
1. grid follow an imput output circuit, have input/output terminal, comprise and export pre-driver circuitry, output-stage circuit, input stage circuit and static release circuit, it is characterized in that, also comprise:
Floating bias circuit, the substrate of the metal-oxide-semiconductor comprised with output-stage circuit is connected, and when described input/output terminal is receiving mode, adjusts the voltage of the substrate of described metal-oxide-semiconductor to prevent the leakage current of described input/output terminal to the substrate of described metal-oxide-semiconductor;
Grid follow circuit, the output of input termination output-stage circuit and described input/output terminal, first control end and the second control end connect the controlled end of described floating bias circuit and the controlled end of described output-stage circuit respectively, output and guard signal end connect the input of described input stage circuit and the controlled end of described static release circuit respectively, when described input/output terminal is receiving mode, and the signal of telecommunication of described input/output terminal access is when being changed to low-voltage from high voltage, described input/output terminal is accessed, there is the high-tension signal of telecommunication discharge, according to the voltage control of signal of telecommunication during electric discharge or after electric discharge, floating bias circuit adjusts the voltage of the substrate of described metal-oxide-semiconductor.
2. grid as claimed in claim 1 follow imput output circuit, and it is characterized in that, described grid follow circuit comprises:
First PMOS, the 3rd NMOS tube, the 4th NMOS tube, the 5th NMOS tube, the 6th NMOS tube, the 7th NMOS tube, the 8th NMOS tube, the 9th NMOS tube, the 14 NMOS tube, the 9th inverter, the tenth inverter, the 11 inverter and the first resistance;
The source electrode of described first PMOS is the input of described grid follow circuit, the grid of described first PMOS and drain electrode connect the grid of power supply and described 4th NMOS tube respectively, the substrate of described metal-oxide-semiconductor comprises the substrate of described first PMOS, the drain electrode of described first PMOS is the first control end of described grid follow circuit, second control end and guard signal end, the source electrode of described 4th NMOS tube and drain electrode connect the input of power supply and described 9th inverter respectively, the source electrode of described 3rd NMOS tube, grid and drain electrode connect the drain electrode of described first PMOS respectively, the input of power supply and described 9th inverter, the drain electrode of described 5th NMOS tube, grid and source electrode connect the drain electrode of described first PMOS respectively, the output of described 9th inverter and the drain electrode of described 7th NMOS tube, the drain electrode of described 6th NMOS tube, grid and source electrode connect the drain electrode of described first PMOS respectively, the drain electrode of power supply and described 7th NMOS tube, grid and the source electrode of described 7th NMOS tube connect VDD-to-VSS respectively, the input of described tenth inverter and output connect the output of described 9th inverter and the grid of described 8th NMOS tube respectively, the drain electrode of described 8th NMOS tube and source electrode connect the drain electrode of described first PMOS and the drain electrode of described 9th NMOS tube respectively, the grid of described 9th NMOS tube and source electrode connect output and the ground of described 11 inverter respectively, the drain electrode of described 14 NMOS tube, grid and source electrode connect the input of described 11 inverter respectively, the first end of power supply and described first resistance, the drain electrode of described 14 NMOS tube is the output of described grid follow circuit, the source electrode of the first PMOS described in second termination of described first resistance.
3. grid as claimed in claim 1 follow imput output circuit, and it is characterized in that, described floating bias circuit comprises:
8th PMOS and the 9th PMOS;
The grid of described 8th PMOS is the controlled end of described floating bias circuit, the drain electrode of described 8th PMOS and source electrode connect the source electrode of power supply and described 9th PMOS respectively, the source electrode of described 8th PMOS and the source electrode of described 9th PMOS all connect the substrate of described metal-oxide-semiconductor, the substrate of described 8th PMOS connects the source electrode of described 8th PMOS, the substrate of described 9th PMOS connects the source electrode of described 9th PMOS, and the drain and gate of described 9th PMOS connects grid and the power supply of described 8th PMOS respectively.
4. grid as claimed in claim 1 follow imput output circuit, and it is characterized in that, described static release circuit comprises:
Tenth PMOS, the 11 PMOS, the 12 PMOS, the 15 NMOS tube, the 16 NMOS tube and the 17 NMOS tube;
Source electrode and the substrate of described 12 PMOS all connect power supply, the grid of described 12 PMOS and the grid of drain electrode difference ground connection and described 11 PMOS, the source electrode of described 11 PMOS and drain electrode connect the source electrode of power supply and the tenth PMOS respectively, the substrate of described metal-oxide-semiconductor comprises the substrate of described 11 PMOS and the substrate of described tenth PMOS, the grid of described tenth PMOS is the controlled end of described static release circuit, the drain electrode of described tenth PMOS connects described input/output terminal, the drain electrode of described 17 NMOS tube, grid and source electrode connect the drain electrode of described tenth PMOS respectively, the drain electrode of power supply and described 16 NMOS tube, the drain electrode of described 15 NMOS tube, grid and source electrode connect the source electrode of described 16 NMOS tube respectively, power supply and ground, the source ground of described 16 NMOS tube.
5. grid as claimed in claim 1 follow imput output circuit, and it is characterized in that, described output-stage circuit comprises:
Second PMOS, the 3rd PMOS, the first NMOS tube and the second NMOS tube;
The source electrode of described second PMOS, grid and drain electrode connect power supply, first output (PO1) of described output pre-driver circuitry and the source electrode of described 3rd PMOS respectively, the grid of described 3rd PMOS is the controlled end of described output-stage circuit, the drain electrode of described first NMOS tube, grid and source electrode connect the drain electrode of the drain electrode of described 3rd PMOS, power supply and described second NMOS tube respectively, and the grid of described second NMOS tube and source electrode connect the second output (PO2) and the ground of described output pre-driver circuitry respectively.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310689170.0A CN104716938B (en) | 2013-12-16 | 2013-12-16 | A kind of grid follow imput output circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310689170.0A CN104716938B (en) | 2013-12-16 | 2013-12-16 | A kind of grid follow imput output circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN104716938A true CN104716938A (en) | 2015-06-17 |
| CN104716938B CN104716938B (en) | 2018-03-30 |
Family
ID=53415959
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201310689170.0A Expired - Fee Related CN104716938B (en) | 2013-12-16 | 2013-12-16 | A kind of grid follow imput output circuit |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN104716938B (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106374907A (en) * | 2015-07-21 | 2017-02-01 | 炬芯（珠海）科技有限公司 | Circuit employing push-pull output |
| CN114690823A (en) * | 2020-12-25 | 2022-07-01 | 圣邦微电子（北京）股份有限公司 | Output stage circuit of power supply monitoring chip |
| CN115903986A (en) * | 2023-02-08 | 2023-04-04 | 上海海栎创科技股份有限公司 | Input/output circuit |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4956691A (en) * | 1989-03-24 | 1990-09-11 | Delco Electronics Corporation | NMOS driver circuit for CMOS circuitry |
| CN2562502Y (en) * | 2002-06-25 | 2003-07-23 | 威盛电子股份有限公司 | Overvoltage protecting circuit with buffered output |
| CN101510774A (en) * | 2009-03-03 | 2009-08-19 | 中国航天时代电子公司第七七一研究所 | Mixing voltage output circuit |
-
2013
- 2013-12-16 CN CN201310689170.0A patent/CN104716938B/en not_active Expired - Fee Related
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4956691A (en) * | 1989-03-24 | 1990-09-11 | Delco Electronics Corporation | NMOS driver circuit for CMOS circuitry |
| CN2562502Y (en) * | 2002-06-25 | 2003-07-23 | 威盛电子股份有限公司 | Overvoltage protecting circuit with buffered output |
| CN101510774A (en) * | 2009-03-03 | 2009-08-19 | 中国航天时代电子公司第七七一研究所 | Mixing voltage output circuit |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106374907A (en) * | 2015-07-21 | 2017-02-01 | 炬芯（珠海）科技有限公司 | Circuit employing push-pull output |
| CN106374907B (en) * | 2015-07-21 | 2019-04-12 | 炬芯（珠海）科技有限公司 | A kind of circuit exported using push-pull type |
| CN114690823A (en) * | 2020-12-25 | 2022-07-01 | 圣邦微电子（北京）股份有限公司 | Output stage circuit of power supply monitoring chip |
| CN115903986A (en) * | 2023-02-08 | 2023-04-04 | 上海海栎创科技股份有限公司 | Input/output circuit |
Also Published As
| Publication number | Publication date |
|---|---|
| CN104716938B (en) | 2018-03-30 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN102386898B (en) | Reset circuit | |
| CN107947784A (en) | A kind of high-performance output driving circuit | |
| US7969191B2 (en) | Low-swing CMOS input circuit | |
| CN104319275A (en) | Electrostatic discharge protection circuit | |
| US9768768B2 (en) | Failsafe interface circuit and related method | |
| CN102487240B (en) | Control circuit of voltage switching rate and output circuit | |
| US8847658B2 (en) | Overdrive circuits and related method | |
| CN102521176B (en) | Input output (IO) interface output circuit in microprocessor | |
| CN104052454A (en) | Level shifter for high density integrated circuits | |
| CN104716938A (en) | Grating following input and output circuit | |
| CN102064818A (en) | Complementary metal oxide semiconductor (CMOS) input/output interface circuit | |
| KR20180028005A (en) | Level shift circuit and semiconductor device | |
| CN104270138B (en) | Input/output buffer of multiple voltage domains | |
| CN106411303A (en) | Anti-creeping MOS switch structure applicable to integrated circuit | |
| CN107251434A (en) | The output driver prevented with reverse power supply | |
| CN103051325B (en) | Pull-up resistance circuit for preventing reverse current filling | |
| CN103312313B (en) | A kind of control method of rail-to-rail enable signal, circuit and level shifting circuit | |
| WO2023035513A1 (en) | Level conversion circuit and chip | |
| CN102638254B (en) | Low leakage power detection device, system and method | |
| CN101944903B (en) | Cmos input buffer circuit | |
| CN210273824U (en) | High-speed drive circuit of field control type power electronic device | |
| CN107342280B (en) | Output circuit with electrostatic discharge protection function | |
| Tsai et al. | Design of 2× VDD-tolerant I/O buffer with considerations of gate-oxide reliability and hot-carrier degradation | |
| CN101227181B (en) | Electric potential switching device | |
| CN105187045A (en) | Dynamic latch with pull-up PMOS (P-channel Metal Oxide Semiconductor) transistor of high-speed circuit |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20180330 |
|
| CF01 | Termination of patent right due to non-payment of annual fee |