CN2562502Y - Overvoltage protecting circuit with buffered output - Google Patents
Overvoltage protecting circuit with buffered output Download PDFInfo
- Publication number
- CN2562502Y CN2562502Y CN 02239507 CN02239507U CN2562502Y CN 2562502 Y CN2562502 Y CN 2562502Y CN 02239507 CN02239507 CN 02239507 CN 02239507 U CN02239507 U CN 02239507U CN 2562502 Y CN2562502 Y CN 2562502Y
- Authority
- CN
- China
- Prior art keywords
- output
- transistor
- connects
- gate
- input
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Images
Landscapes
- Logic Circuits (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
An over-voltage protection circuit with out buffer is arranged between a data output element and an input/output node connected with an input/output pin. The utility model is characterized in that the over-voltage protection circuit also comprises a pull up transistor with the drain electrode connected with an external operating potential, the source electrode thereof connected with the input/output node, and the gate connected thereof with the data output element through a voltage boosting node; a voltage boosting transistor with the drain electrode thereof connected with the external operating potential, and the source electrode thereof connected with the input/output node; and a voltage boosting control circuit with the input end thereof connected with the input/output node and the output end thereof connected with the gate of the voltage boosting transistor. When the input/output node is at over-voltage state, the input end of the voltage boosting transistor senses and transmits a signal at the output end thereof, then the voltage boosting transistor is conducted, and the pull up transistor pulls up the potential of the gate at closing state to reduce voltage difference between the gate and source electrode, so as to prevent electrical leakage and prevent element damage due to the breakdown of the oxidizing layer of the gate of the pull up transistor. The utility model is very practical.
Description
Technical field
The utility model relates to a kind of protective circuit, particularly a kind of excess voltage protection of exporting buffering.
Background technology
In recent years, because the high development and the various product of electronics and information related industry move towards compact epoch trend, people are inclined to increasing electronic component are integrated in the chip, cause that component density significantly improves in the chip, the arithmetic speed of information product also constantly promotes along with people's demand simultaneously.For highly dense intensity and arithmetic speed at a high speed in response to element in the chip; must in chip, use voltage to come work than known specification was low in the past; the operation voltage that usually causes chip internal and outside operating voltage be difference to some extent; so must buffer circuit be set in the core circuit and the external circuit junction of chip, can not come to harm because of the operate outside overtension with the core circuit of protecting chip.
The present known output buffer of industry, be as shown in Figure 1, it mainly is to be provided with an output buffer between data output line 161 and output and input pins (I/Opad) 145, wherein a data output line 161 and an output control signal 163 are connected one and two inputs of lock (AND gate) 141 respectively, and the output of lock 141 then is connected on one by a node (node) 181 and draws (pull-up) circuit and one drop-down (pull-down) circuit, again by drawing on this with pull-down circuit the data transmission of chip core (core) circuit generation to output and input pins 145.Include 121 and one protective transistor 123 that pulls up transistor in its pull-up circuit; this drain electrode (drain) of 121 of pulling up transistor connects an operate outside current potential VPP; source electrode (source) connects the drain electrode of protective transistor 123, and gate (gate) is connected node 181 then.The source electrode of protective transistor 123 connects output and input pins 145 by a node 183, and gate then connects the operate outside current potential, forms a protection component.This pulls up transistor 121 can be according to the output signal of data and conducting or close, and draws on the current potential with node 183 and transmits the signal of high potential.
Pull-down circuit includes an inverter (inverter) 143, a pull-down transistor 127 and a protective transistor 125; the drain electrode connected node 183 of protective transistor 125 wherein; source electrode connects the drain electrode of pull-down transistor 127, and gate then connects the operate outside current potential, forms a protection component.The source electrode of pull-down transistor 127 connects an earth potential VGG, and the input of inverter 143 is connected node 181 then, and output is connected to the gate of pull-down transistor 127.So, when the output data signal was electronegative potential, the current potential of node 181 was an electronegative potential, and inverter 143 will be exported a high potential and make pull-down transistor 127 conductings, and the current potential of node 183 is drop-down, to transmit the signal of electronegative potential.
Above-mentioned known output buffer, though can reach the effect of chip internal operating voltage and operate outside voltage buffering, it is right because it is to utilize the transistor of two series connection to operate, under identical channel length, as will have the current driving ability identical the time with an independent transistor, the width of its channel must significantly increase, and so will take area bigger in the chip.
In addition, when producing static discharge (Electrostatic Discharge; ESD) during effect, pull up transistor and pull-down transistor also can provide the discharge path of being held VPP or VGG by IO.At this moment, by two circuit that transistor series constituted, its transistor is not easy conducting and helps discharge as above-mentioned.
Again, because the manufacture of semiconductor technology is showing improvement or progress day by day now, component size is dwindled day by day, in the chip of high component density, the transistor of two vicinities is easy to generate the parasitic antenna of the two-carrier junction transistor (BJT) of p-n-p, and this parasitic antenna is easy to be burnt by static discharge current and the destruction of causing permanent short between operating potential VPP and earth potential VGG, a real puzzlement greatly for the chip design dealer.
Therefore; how at shortcoming that above-mentioned known output buffer produced; and the problem that is taken place when using proposes a kind of novel solution; design a kind of simple and practical output buffer; the effect of output buffering not only can effectively be provided; reduce the chance that produces parasitic antenna; and can simplify the complexity of processing procedure; prevent the generation of leakage current; be not to use for a long time the person eagerly to look forward to and difficulty place that this creation human desires row solves always; and this creator is based on the correlative study of engaging in information and electronic industry for many years; exploitation; and the practical experience of selling; be to think and improved idea; through design in many ways; inquire into; after studying sample and improvement, work out a kind of excess voltage protection of exporting buffering finally, to solve the above problems.
Summary of the invention
The utility model is that a kind of excess voltage protection of exporting buffering will be provided, the technical problem that the core circuit that makes chip with solution can not be damaged because of the operate outside overtension.
It is such solving the problems of the technologies described above the technical scheme that is adopted:
A kind of excess voltage protection of exporting buffering is arranged at the data output element and is connected between the output ingress of output and input pins, it is characterized in that, mainly includes:
One pulls up transistor, and its drain electrode connects an operate outside current potential, and source electrode connects an output ingress, and gate then connects a data output element by the node that boosts;
One boost transistor, its drain electrode connects the operate outside current potential, and source electrode connects the node that boosts;
One boost control circuit, its input connects this output ingress, one output connects the gate of this boost transistor, this output ingress produces under the too high voltage status, its input sensing is learnt and is transmitted a signal in output, this boost transistor conducting, and it pulls up transistor and under closed condition the current potential of gate is drawn high, to reduce the cross-pressure between gate and source electrode, reduce the chance that produces leakage current;
This boost control circuit includes an oxide-semiconductor control transistors, and its drain electrode is connected in the input of this boost control circuit, and source electrode connects the gate of this boost transistor, and its gate then connects an output control signal;
Between pulling up transistor, this data output element and this be provided with a transmission lock, its input connects this output element, output connects this by this node that boosts and pulls up transistor, and control end then connects the source electrode of this oxide-semiconductor control transistors, and this transmission lock opens and closes according to the signal of oxide-semiconductor control transistors;
This boost control circuit is provided with one second oxide-semiconductor control transistors, its drain electrode is connected with the source electrode of oxide-semiconductor control transistors, and source ground, gate then connect a dual signal relative with this output control signal, under this oxide-semiconductor control transistors closed condition, the current potential of this boost control circuit output is drop-down;
This boost control circuit includes a voltage filter device, its input connects oxide-semiconductor control transistors, output then connects the control end of transmission lock and the gate of boost transistor respectively, this voltage filter device can be higher than in the current potential of input under the set point state, and its output is exported an operating potential signal;
This transmission lock includes the N channel transistor and the p channel transistor of one group of parallel connection;
This voltage filter device is to include a high critical voltage inverter and a low critical voltage inverter, wherein the input of this high critical voltage inverter connects the source electrode of oxide-semiconductor control transistors, output connects the input of this low critical voltage inverter, is connected to the control end of transmission lock and the gate of boost transistor and be somebody's turn to do the output that hangs down the critical voltage inverter;
This boost control circuit includes a high critical voltage inverter and a low critical voltage inverter, the input of this high critical voltage inverter connects the source electrode of oxide-semiconductor control transistors, output connects the input and the gate that transmits the N channel transistor in the lock of this low critical voltage inverter, and the output that should hang down the critical voltage inverter then connects the gate of the p channel transistor in the transmission lock and the gate of boost transistor;
This voltage filter device includes the p channel transistor and the N channel transistor of a high critical voltage inverter and one group of series connection, and the drain electrode of this boost transistor is connected in a core work current potential; Wherein the drain electrode of this p channel transistor connects this core work current potential, the drain electrode of source electrode and this N channel transistor is connected to the control end of transmission lock and the gate of this boost transistor simultaneously, the source ground of this N channel transistor, this p channel transistor and the gate of N channel transistor are connected the output of high critical voltage inverter simultaneously, and are connected with the gate of N channel transistor in the transmission lock;
This protective circuit also includes a drop-down buffer circuit, is connected in this output ingress.
The utility model mainly is to include one to pull up transistor, and its drain electrode connects an operate outside current potential, and source electrode connects an output ingress, and gate then connects a data output element by the node that boosts; One boost transistor, its drain electrode connects the operate outside current potential, and source electrode connects the node that boosts; An and boost control circuit, its input connects this output ingress, one output connects the gate of this boost transistor, can be when the output ingress produces too high voltage, learn and transmit a signal by the input sensing in output, allow this boost transistor conducting, this is pulled up transistor draws high the current potential of gate under closing state, to reduce the cross-pressure between gate and source electrode, can prevent the generation of leaking electricity, and the gate pole oxidation layer collapse and cause component wear of avoiding pulling up transistor, thereby solved the technical problem that the core circuit that makes chip can not be damaged because of the operate outside overtension.
The utility model relates to a kind of protective circuit, especially refer to a kind of excess voltage protection of exporting buffering, it mainly is in an output buffer protection circuit, utilize the one-level transistor to cooperate a boost control circuit, can when output goes into to bring out existing high voltage, the gate current potential that pulls up transistor be improved, under the situation that keeps closing that pulls up transistor, reduce the cross-pressure between gate and source electrode, but protection component and prevent electric leakage; Its advantage is as follows:
1, this protective circuit mainly is to utilize one-level to pull up transistor as the buffering of output, can effectively save usable floor area;
2, this protective circuit also can connect a booster circuit in the gate that one-level pulls up transistor, can be when output goes into to bring out existing high pressure, improve the voltage of gate, to reduce this cross-pressure between gate and source electrode of pulling up transistor, can prevent to produce leakage current, and avoid pulling up transistor gate pole oxidation layer collapse and cause component wear;
3, its data output element of this protective circuit still can be set up a transmission lock, can further protect core circuit;
4, its booster circuit of this protective circuit comprises boost an element and a boost control circuit, can be exported into the too high voltages of end by the boost control circuit sensing and starts this element that boosts, with the pull up transistor current potential of gate of raising;
5, this protective circuit still can include an ESD protection circuit, can strengthen the protection to core circuit.
Description of drawings
Fig. 1 is the circuit diagram of known output buffering excess voltage protection.
Fig. 2 is the circuit diagram of the utility model one preferred embodiment.
Fig. 3 is the circuit diagram of another embodiment of the utility model.
Embodiment
At first, seeing also shown in Figure 2ly, is the circuit diagram of the utility model one preferred embodiment.As shown in the figure, its data output element includes one and lock 201, its two input connects a data output line 203 and an output control line 205 respectively, output then is connected to a node 251, be connected respectively to pull-up circuit and pull-down circuit again, by the control signal EN (output enable) of this output control line 205 with and the effect of lock and whether the may command data is exported.Its output and input pins 202 is connected in an output ingress 253, is connected with one between output ingress 253 and operate outside current potential VPP and pulls up transistor 221.This drain electrode of 221 of pulling up transistor connects operate outside current potential VPP, and source electrode connects output ingress 253, and gate then receives the output signal of data output elements by the node 259 that boosts.Can make this 221 conductings that pull up transistor during for high potential in output signal, draw on the current potential with output ingress 253, and output signal is when being electronegative potential, then will pull up transistor and 221 close, to transmit the signal of high potential.
Then be provided with a drop-down buffer circuit (pull-downbuffer) 26 between output ingress 253 and earth potential VGG, with the transmission low-potential signal.It mainly is to utilize a protective transistor 263, and its drain electrode is connected output ingress 253, and gate connects operate outside current potential VPP, forms a protection component, and its source electrode then connects the drain electrode of a pull-down transistor 261.The source electrode of this pull-down transistor 261 connects earth potential VGG, and 251 of gate and nodes are provided with an inverter 241, can be when the output data be low-potential signal, make this pull-down transistor 261 conductings, the current potential of output ingress 253 is drop-down, and the output data is then closed this pull-down transistor 261 when being high potential signal.
The utility model is to set up a boost transistor 227 for pulling up transistor 221 guard method, makes its drain electrode connect the operate outside current potential, and source electrode connects the node 259 that boosts, and gate then connects a boost control circuit.When too high voltage appearred in output ingress 253 places, this boost control circuit promptly sent a control signal and makes boost transistor 227 conductings, can draw on the current potential with the node 259 that boosts.
This boost control circuit includes an oxide-semiconductor control transistors 223, one second oxide-semiconductor control transistors, 225, one high critical voltage inverter (high-threshold inverter), 247 and one low critical voltage inverter 249.And in the pull-up circuit, boost node 259 and 251 of nodes still can be provided with the transmission lock 24 that a NMOS 243 in parallel and PMOS 245 are formed, to strengthen the protection to core circuit.
The drain electrode of oxide-semiconductor control transistors 223 is connected to output ingress 253 in the boost control circuit, source electrode connected node 255, and (when EN was 1, EN_ was 0 to the gate connection one dual Control signal EN_ relative with output control signal EN; EN is 0 o'clock, and EN_ is 1).The drain electrode connected node 255 of second oxide-semiconductor control transistors 225, source ground, gate then connect output control signal EN.The input of this high critical voltage inverter 247 is connected in node 255, and output connects the input and the gate that transmits NMOS 243 in the lock 24 of low critical voltage inverter 249 by node 257.The output that should hang down critical voltage inverter 249 then is connected to the gate and the gate that transmits PMOS 245 in the lock 24 of boost transistor 227 by node 258.
The operation situation of entire circuit is as follows: when output control signal EN is 1, dual Control signal EN_ is 0, the potential drop of node 255 is to 0V at this moment, the current potential of node 257 is VPP, the current potential of node 258 is 0V, so boost transistor 227 is closed, and transmission lock 24 is conducting, and output signal can be by the 221 correctly transmission that pull up transistor.
When output control signal EN was 0, dual Control signal EN_ was 1, oxide-semiconductor control transistors 223 conductings this moment, and second oxide-semiconductor control transistors 225 is closed, so the signal at output ingress 253 places can enter in the boost control circuit.When too high voltage appearred in output ingress 253 places, if when the voltage of node 255 is higher than the critical voltage (threshold voltage) of high critical voltage inverter 247, the current potential of node 257 dropped to 0V, and the current potential of node 258 is VPP.Transmit lock 24 this moment and close, and boost transistor 227 conductings can be drawn high the current potential of the node 259 that boosts the critical voltage (Vt) that the operate outside current potential deducts boost transistor 227, that is VPP-Vt.
So, can 221 keep improving the current potential of gate under the closing state (current potential of gate is less than the current potential of source electrode) pulling up transistor, reduce the cross-pressure of gate and source electrode, avoiding component wear, and prevent the generation of leakage current.
In addition, still can set up an ESD protection circuit 28, be connected in this output ingress 253, it mainly is the NMOS 283 and NMOS 281 that includes series connection.Wherein the gate of NMOS 283 connects operate outside current potential VPP, and the gate of NMOS 281 then is connected earth potential simultaneously with source electrode.Can strengthen whole protection effect by this ESD protection circuit 28 to the static discharge effect.Again,, can export between ingress 253 and the data input line 209, set up the transistor 207 that a gate connects operate outside current potential VPP, can reach the effect of buffering in this in the data input part.
At last, seeing also shown in Figure 3ly, is the circuit diagram of another embodiment of the utility model, and its main circuit structure is roughly identical with the described embodiment of Fig. 2, main difference is in the foregoing description that its low critical voltage inverter 249 can also be replaced with NMOS 323 by one group of PMOS that connects 321; And the drain electrode of its boost transistor 227 is connected in the chip core core work current potential VDD in when running among this embodiment.Wherein the drain electrode of this PMOS 321 can be connected in this core work current potential VDD, and the drain electrode of source electrode and NMOS 323 is connected node 258 simultaneously, and the source ground of NMOS 323, both gates then are connected to node 257 simultaneously.So, when boost control circuit started because of output ingress 253 produces high voltage, node 257 current potentials were 0, and node 258 current potentials are VDD, transmission lock 24 can cut out.And boost transistor 227 also can be moved VDD-Vt in conducting this moment on the current potential with the node 259 that boosts, and can reach and identical effect embodiment illustrated in fig. 2.
In the various embodiments described above, respectively pull up transistor and oxide-semiconductor control transistors is to constitute the master with N channel metal-oxide transistor (NMOS).Yet, according to spirit of the present utility model, each element is done equivalence with other transistor replace, also should be contained in the utility model scope.
The above, it only is a preferred embodiment of the present utility model, be not to be used for limiting the scope that the utility model is implemented, be that all equalizations of doing according to the described shape of the utility model claim, structure, feature and spirit change and modification, all should be included in the claim of the present utility model.
In sum; when knowing that the utility model relates to a kind of protective circuit; especially refer to a kind of excess voltage protection of exporting buffering; it mainly is in an output buffer protection circuit, utilizes the one-level transistor to cooperate a boost control circuit, can be when output goes into to bring out existing high voltage; the gate current potential that pulls up transistor is improved; under the situation that keeps closing that pulls up transistor, reduce the cross-pressure between gate and source electrode, but protection component and prevent electric leakage.So the utility model is one to be rich in novelty, advance in fact, and can utilize effect, meet the utility application important document, so propose utility application in accordance with the law for industry.
Claims (10)
1, a kind of excess voltage protection of exporting buffering is arranged at the data output element and is connected between the output ingress of output and input pins, it is characterized in that, mainly includes:
One pulls up transistor, and its drain electrode connects an operate outside current potential, and source electrode connects an output ingress, and gate then connects a data output element by the node that boosts;
One boost transistor, its drain electrode connects the operate outside current potential, and source electrode connects the node that boosts;
One boost control circuit, its input connects this output ingress, one output connects the gate of this boost transistor, this output ingress produces under the too high voltage status, its input sensing is learnt and is transmitted a signal in output, this boost transistor conducting, it pulls up transistor and under closed condition the current potential of gate is drawn high, to reduce the cross-pressure between gate and source electrode.
2, the excess voltage protection of output buffering according to claim 1; it is characterized in that: this boost control circuit includes an oxide-semiconductor control transistors; its drain electrode is connected in the input of this boost control circuit; source electrode connects the gate of this boost transistor, and its gate then connects an output control signal.
3, the excess voltage protection of output buffering according to claim 2; it is characterized in that: be provided with a transmission lock between this data output element and this pull up transistor; its input connects this output element; output connects this by this node that boosts and pulls up transistor; control end then connects the source electrode of this oxide-semiconductor control transistors, and this transmission lock opens and closes according to the signal of oxide-semiconductor control transistors.
4, the excess voltage protection of output buffering according to claim 2; it is characterized in that: this boost control circuit is provided with one second oxide-semiconductor control transistors; its drain electrode is connected with the source electrode of oxide-semiconductor control transistors; source ground; gate then connects a dual signal relative with this output control signal; under this oxide-semiconductor control transistors closed condition, the current potential of this boost control circuit output is drop-down.
5, the excess voltage protection of output buffering according to claim 3; it is characterized in that: this boost control circuit includes a voltage filter device; its input connects oxide-semiconductor control transistors; output then connects the control end of transmission lock and the gate of boost transistor respectively; this voltage filter device can be higher than in the current potential of input under the set point state, and its output is exported an operating potential signal.
6, the excess voltage protection of output buffering according to claim 3, it is characterized in that: this transmission lock includes the N channel transistor and the p channel transistor of one group of parallel connection.
7, the excess voltage protection of output buffering according to claim 5; it is characterized in that: this voltage filter device is to include a high critical voltage inverter and a low critical voltage inverter; wherein the input of this high critical voltage inverter connects the source electrode of oxide-semiconductor control transistors; output connects the input of this low critical voltage inverter, is connected to the control end of transmission lock and the gate of boost transistor and be somebody's turn to do the output that hangs down the critical voltage inverter.
8, the excess voltage protection of output buffering according to claim 6; it is characterized in that: this boost control circuit includes a high critical voltage inverter and a low critical voltage inverter; the input of this high critical voltage inverter connects the source electrode of oxide-semiconductor control transistors; output connects the input and the gate that transmits the N channel transistor in the lock of this low critical voltage inverter, and the output that should hang down the critical voltage inverter then connects the gate of the p channel transistor in the transmission lock and the gate of boost transistor.
9, the excess voltage protection of output buffering according to claim 5, it is characterized in that: this voltage filter device includes the p channel transistor and the N channel transistor of a high critical voltage inverter and one group of series connection, and the drain electrode of this boost transistor is connected in a core work current potential; Wherein the drain electrode of this p channel transistor connects this core work current potential, the drain electrode of source electrode and this N channel transistor is connected to the control end of transmission lock and the gate of this boost transistor simultaneously, the source ground of this N channel transistor, this p channel transistor and the gate of N channel transistor are connected the output of high critical voltage inverter simultaneously, and are connected with the gate of N channel transistor in the transmission lock.
10, the excess voltage protection of output buffering according to claim 1 is characterized in that: include a drop-down buffer circuit, be connected in this output ingress.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 02239507 CN2562502Y (en) | 2002-06-25 | 2002-06-25 | Overvoltage protecting circuit with buffered output |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 02239507 CN2562502Y (en) | 2002-06-25 | 2002-06-25 | Overvoltage protecting circuit with buffered output |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN2562502Y true CN2562502Y (en) | 2003-07-23 |
Family
ID=33712871
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 02239507 Expired - Fee Related CN2562502Y (en) | 2002-06-25 | 2002-06-25 | Overvoltage protecting circuit with buffered output |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN2562502Y (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101304240B (en) * | 2007-05-09 | 2010-07-14 | 瑞鼎科技股份有限公司 | Voltage limiting apparatus as well as operation amplifier applying the same and circuit design method thereof |
| CN102655409A (en) * | 2011-03-02 | 2012-09-05 | 创意电子股份有限公司 | Two-stage rear-end driver |
| CN104716938A (en) * | 2013-12-16 | 2015-06-17 | 深圳市国微电子有限公司 | Grating following input and output circuit |
-
2002
- 2002-06-25 CN CN 02239507 patent/CN2562502Y/en not_active Expired - Fee Related
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101304240B (en) * | 2007-05-09 | 2010-07-14 | 瑞鼎科技股份有限公司 | Voltage limiting apparatus as well as operation amplifier applying the same and circuit design method thereof |
| CN102655409A (en) * | 2011-03-02 | 2012-09-05 | 创意电子股份有限公司 | Two-stage rear-end driver |
| CN102655409B (en) * | 2011-03-02 | 2014-08-20 | 创意电子股份有限公司 | Two-stage rear-end driver |
| CN104716938A (en) * | 2013-12-16 | 2015-06-17 | 深圳市国微电子有限公司 | Grating following input and output circuit |
| CN104716938B (en) * | 2013-12-16 | 2018-03-30 | 深圳市国微电子有限公司 | A kind of grid follow imput output circuit |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR102276808B1 (en) | scan drive circuit | |
| US20050122155A1 (en) | Level conversion circuit and semiconductor integrated circuit device employing the level conversion circuit | |
| TW201042747A (en) | Electrostatic discharge clamp circuit | |
| CN1722438A (en) | Low leakage monotonic CMOS logic | |
| CN1870436B (en) | Signal alignment circuit, drawing down circuit and pulling up circuit | |
| CN101030574A (en) | High-voltage tolerant power-rail electrostatic discharge protection circuit for mixed-voltage i/o interface | |
| TW200830078A (en) | Source follower, method, and electronic system utilizing the same | |
| JPH11274911A (en) | Output buffer with voltage withstanding characteristic | |
| CN1825765A (en) | Tie-high and tie-low circuit, system and interrelated semiconductor set | |
| CN1197332A (en) | Input/output voltage detection type substrate voltage generation circuit | |
| CN101682326A (en) | What have that dog days assist can tolerate five volts integrated circuit signal pad | |
| CN107408946A (en) | It is configured to grid and crosses the transistor of biasing and resultant circuit | |
| CN2562502Y (en) | Overvoltage protecting circuit with buffered output | |
| JPWO2017098909A1 (en) | Output circuit | |
| JPH0438012A (en) | Output buffer circuit | |
| CN1262068C (en) | Over-voltage protector circuit with output buffer | |
| CN1156980C (en) | Methods and appts. for bipolar elimination in silicon-on-insulator (sol) domino circuits | |
| JP3113853B2 (en) | Data output buffer circuit | |
| JP3422921B2 (en) | Semiconductor integrated circuit | |
| CN103365325B (en) | Audio device switching control apparatus and methods | |
| CN1612434A (en) | Voltage source electrostatic discharge protective circuit | |
| CN1162820A (en) | Signal generator | |
| CN1501561A (en) | Fast triggering electrostatic protection circuit and method thereof | |
| CN1783718A (en) | Logic circuit | |
| CN1615587A (en) | Integrated circuit and battery powered electronic device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| C19 | Lapse of patent right due to non-payment of the annual fee | ||
| CF01 | Termination of patent right due to non-payment of annual fee |