CN1501561A - Fast triggering electrostatic protection circuit and method thereof - Google Patents
Fast triggering electrostatic protection circuit and method thereof Download PDFInfo
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- CN1501561A CN1501561A CNA021513406A CN02151340A CN1501561A CN 1501561 A CN1501561 A CN 1501561A CN A021513406 A CNA021513406 A CN A021513406A CN 02151340 A CN02151340 A CN 02151340A CN 1501561 A CN1501561 A CN 1501561A
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- protective circuit
- transistor
- discharge protective
- electrostatic discharge
- rapid triggering
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- 230000001681 protective Effects 0.000 claims description 69
- 238000005421 electrostatic potential Methods 0.000 claims description 29
- 230000003068 static Effects 0.000 claims description 22
- 238000007599 discharging Methods 0.000 claims description 9
- 239000004065 semiconductors Substances 0.000 claims description 8
- 230000036887 VSS Effects 0.000 claims description 4
- 230000000694 effects Effects 0.000 abstract description 6
- 239000010410 layers Substances 0.000 abstract description 4
- 230000001808 coupling Effects 0.000 abstract 1
- 238000010168 coupling process Methods 0.000 abstract 1
- 238000005859 coupling reactions Methods 0.000 abstract 1
- 230000003647 oxidation Effects 0.000 abstract 1
- 238000007254 oxidation reactions Methods 0.000 abstract 1
- 239000003990 capacitor Substances 0.000 description 7
- 239000000969 carriers Substances 0.000 description 4
- 239000000758 substrates Substances 0.000 description 4
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- 238000004088 simulation Methods 0.000 description 2
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Abstract
Description
Technical field
The present invention relates to a kind of electrostatic discharge protective circuit, but particularly a kind of rapid triggering shunting transistor enters the electrostatic discharge protective circuit of jumping logical state (snap back).
Background technology
N type gold oxygen half (NMOS) transistor can be as the device of electrostatic protection.With gate coupled to the transistor of gate drive signal is example, and nmos pass transistor falls (pull down) transistor as drawing in a complementary gold oxygen half buffer (CMOS buffer) uses, with drive output signal.Transistor with grounded-grid is an example again, and nmos pass transistor is in order to provide the electrostatic protection of an input pin or power bus.
The mode that nmos pass transistor carries out electrostatic protection is to utilize collapse of nmos pass transistor (avalanchebreakdown) and the logical phenomenon (snap back) of jumping to reach.This kind phenomenon is when initial, and the caused impact ionization of big electric field (impact ionization) phenomenon that is positioned at drain junction can produce majority (majority) and minority (minority) charge carrier simultaneously.Minority carrier can be collected in drain electrode, and majority carrier then flows to the contact hole (contact) of substrate of P type or P wellblock and form a local potential in the P wellblock.When the contiguous N+ source potential of the local potential of substrate exceeded 0.8V, source junction just formed forward bias voltage drop.Suitable inclined to one side source junction meeting injected minority carrier is to the P wellblock.By combination (recombined) again, other then arrival drain junction has strengthened impacting Ionized phenomenon to the minority carrier that part is injected further in substrate.Xun Huan result according to this, MOSFET just can enter the logical state of a kind of low-impedance jumping, and a large amount of static discharge current of beginning conducting.
Fig. 1 has shown the transistorized electrostatic discharge protective circuit of traditional use gate coupled.In order to the shunting transistor N1 of electrostatic discharging path to be provided, its grid can be coupled to the positive bias of a 1--2V and make shunting transistor N1 enter the required trigger voltage reduction of the logical state of jumping when positive electrostatic potential produces, also make the nmos pass transistor conducting more simultaneously of many pins simultaneously.
United States Patent (USP) 6304127,6091593 and 5870268 all provides the method how an instantaneous back bias voltage is provided when positive electrostatic potential produces.This back bias voltage add all in substrate diffusion region (diffusionregion) or the wellblock on to reduce the required trigger voltage of electrostatic protection assembly.
Summary of the invention
In order to provide instantaneous back bias voltage to reduce transistorized trigger voltage when positive electrostatic potential produces, the present invention also provides a kind of electrostatic discharge protective circuit, and it directly is provided in instantaneous back bias voltage on the grid of shunting transistor.
A purpose of the present invention is to provide a kind of electrostatic discharge protective circuit of rapid triggering; provide a negative voltage extremely in order on the transistor gate that electrostatic discharging path is provided when utilizing electrostatic potential to produce; and its required trigger voltage value of jumping logical state that enters is reduced; and can reach the effect of rapid triggering, promote the electrostatic protection performance.
When a positive electrostatic potential produces on a first node, provide to the electrostatic discharging path of a Section Point, comprise a first transistor and the instantaneous negative voltage generator of a static.The drain electrode of the first transistor is coupled to this first node, and source electrode is coupled to this Section Point, when this electrostatic potential on this first node arrives a trigger voltage value, enters a jumping and leads to state and this electrostatic discharging path is provided.When the instantaneous negative voltage generator of static produces on this first node at this electrostatic potential, receive this electrostatic potential and export the grid of a negative voltage, reduce this trigger voltage value to this first transistor.
Described rapid triggering electrostatic discharge protective circuit also comprises a rectification circuit, after receiving this negative voltage and carrying out rectification, exports negative voltage after this rectification to the grid of this first transistor.
Described rapid triggering electrostatic discharge protective circuit, the instantaneous negative voltage generator of this static comprises:
One instantaneous oscillator when this electrostatic potential produces on this first node, receives this electrostatic potential and exports an oscillator signal; And
One first electric capacity, an end connects to receive this oscillator signal, and the other end is coupled to this first transistor grid.
Described rapid triggering electrostatic discharge protective circuit also comprises a transistor seconds, and its drain electrode is coupled to this first transistor grid jointly with grid, and source electrode is coupled to this Section Point.
Described rapid triggering electrostatic discharge protective circuit, this ringing device comprises:
One reverse swing door comprises at least one reverse logic door;
A series of reverser group contacts mutually and comprises one first reverser, and its input is connected to the output of this reverse swing door, also comprises a last reverser, and its output is connected to the first input end of this reverse swing door; And
One second resistance is coupled to second input of this reverse swing door.
Described rapid triggering electrostatic discharge protective circuit also comprises one second electric capacity, is coupled to second input of this reverse swing door.
Described rapid triggering electrostatic discharge protective circuit, this reverse swing door are a NOR gate, and this second resistance also is coupled to this first node.
Described rapid triggering electrostatic discharge protective circuit, this reverse swing door are a NAND gate, and this second resistance also is coupled to this Section Point.
Described rapid triggering electrostatic discharge protective circuit also comprises one the 3rd transistor, and its drain electrode and grid are coupled to the grid of this first transistor jointly, and its source electrode is coupled to this Section Point.
Described rapid triggering electrostatic discharge protective circuit also comprises at least one diode, is connected in series with between this first transistor grid and this Section Point.
Described rapid triggering electrostatic discharge protective circuit, this at least one diode is several.
Described rapid triggering electrostatic discharge protective circuit also comprises a switch, is connected between the grid and this Section Point of this first transistor.
Described rapid triggering electrostatic discharge protective circuit, this first node are a weld pad.
Described rapid triggering electrostatic discharge protective circuit, this first node are a high potential VDD power bus.
Described rapid triggering electrostatic discharge protective circuit, this Section Point are an electronegative potential VSS power bus.
Described rapid triggering electrostatic discharge protective circuit, this first transistor have the grid oxic horizon of a thickness less than 71 .
1 described rapid triggering electrostatic discharge protective circuit, this first transistor has the grid oxic horizon of a thickness less than 41 .
Described rapid triggering electrostatic discharge protective circuit, this first transistor have the grid oxic horizon of a thickness less than 21 .
Another object of the present invention is to provide a kind of method of electrostatic discharge protective circuit of rapid triggering one integrated circuit; this electrostatic discharge protective circuit comprises a MOS (metal-oxide-semiconductor) transistor; it is coupled to a first node and is coupled to a Section Point with one source pole with a drain electrode, may further comprise the steps.When an electrostatic potential adds all this first nodes, produce one with the reverse negative voltage of this electrostatic potential to add all grids in this MOS (metal-oxide-semiconductor) transistor.
Below, the embodiment of accompanying drawings a kind of rapid triggering electrostatic discharge protective circuit of the present invention.
Description of drawings
Fig. 1 has shown the transistorized electrostatic discharge protective circuit of traditional use gate coupled;
Fig. 2 shows the electrostatic discharge protective circuit in the first embodiment of the invention;
Fig. 3 shows the electrostatic discharge protective circuit in the second embodiment of the invention;
Fig. 4 shows the electrostatic discharge protective circuit in the third embodiment of the invention;
Fig. 5 shows the electrostatic discharge protective circuit in the fourth embodiment of the invention;
Fig. 6 shows the electrostatic discharge protective circuit in the fifth embodiment of the invention;
Fig. 7 shows the method for the electrostatic discharge protective circuit of rapid triggering one integrated circuit in one embodiment of the invention.
Symbol description
21,31,41,51, the instantaneous negative voltage generator of 61--static;
311,611--static ringing device;
312,612--electric charge pump circuit;
The 32--rectification circuit;
N1, P2, P1, N2--transistor;
C1, C2, C3--electric capacity;
R1, R2, R3--resistance;
D1, D2--diode;
The X1--NOR gate;
X2, X3, X4--reverser.
Embodiment
Fig. 2 has shown the electrostatic discharge protective circuit among the present invention one first embodiment.This electrostatic discharge protective circuit (can be the function that electrostatic protection is provided between weld pad or high potential VDD power bus and the B (can be electronegative potential VSS power bus) at node A; comprising the instantaneous back bias voltage generator 21 of a static, be coupled to a grid in order to shunting transistor N1 that electrostatic discharging path is provided.When positive electrostatic potential when node A produces, the instantaneous back bias voltage generator 21 of static can provide the grid of a back bias voltage to shunting transistor N1, enter the logical state of jumping to reduce shunting transistor N1 to enter the trigger voltage of jumping logical state fast, the current path of static discharge is provided.
According to the result of experimental data and circuit simulation, concerning a shunting transistor N1 with 40 thickness grid oxide layers,, need to trigger it and enter the trigger voltage of jumping logical state and will reduce about 1.5V when its grid bias during at-2V.This kind phenomenon part is caused by the electric field near the drain junction the grid, and (Gate Induced Drain Leakage GIDL) causes a part by the grid induction drain leakage.The grid induction drain leakage fails to be convened for lack of a quorum to be increased in the leakage current on the drain junction and to add and is better than the impact ionization phenomenon that takes place on the drain junction.
Fig. 3 has shown the electrostatic discharge protective circuit among the present invention one second embodiment.Similar with the electrostatic discharge protective circuit of Fig. 2, comprise the instantaneous back bias voltage generator 31 of a static, be coupled to a grid in order to shunting transistor N1 that electrostatic discharging path is provided.In addition, also comprise a resistance R 3, be coupled between the grid and Node B of shunting transistor N1.3 of capacitor C that are coupled between shunting transistor grid and source electrode can be the gate-to-source parasitic capacitance of shunting transistor or extra capacitance component.
The instantaneous back bias voltage generator 31 of the static of a kind of embodiment has comprised that one is coupled between node A and the B and is connected in the resistance R 2 (its value can be selected between 500--5K Ω) between electric charge pump circuit 312 and shunting transistor N1 grid in static ringing device 311, an electric charge pump circuit (charge pump circuit) 312 and that receives oscillator signal that node C exports an oscillator signal.
When node A produced, the oscillator signal owing to 311 outputs of static ringing device made node E place a series of negative voltage spike (spikes) can occur at positive electrostatic potential.The rectification circuit 32 that is made of resistance R 2 and capacitor C 3 can produce a more smooth back bias voltage at the grid of shunting transistor N1 after receiving this voltage spike, and the trigger voltage that shunting transistor N1 is entered jump logical state reduces.The effect of resistance R 3 is when the circuit normal running, the voltage of shunting transistor N1 grid can be pulled low near the place, to close transistor N1.
In a second embodiment, resistance R 2 can replace with " short circuit ".
Fig. 4 has shown the electrostatic discharge protective circuit in the third embodiment of the invention.With Fig. 3 relatively after as can be known, it additionally increases by a P transistor npn npn P2 between node E and B in the electrostatic discharge protective circuit of Fig. 3, its grid is coupled to node E jointly with drain electrode.The effect of transistor P2 is to adjust the size of shunting transistor N1 grid back bias voltage.Transistor P2 can be lower than at the current potential of node E its limit voltage value (as-conducting 0.7V) time, and make back bias voltage on the shunting transistor N1 be limited (as be limited to-2V).In the present embodiment, the actual size of each assembly can carry out optimal selection according to circuit simulation result and needed grid negative bias values.
In the 3rd embodiment, owing in transistor P2, had the p+/nwell composition surface of a parasitism, so diode D1 can remove.In addition, diode D1 can provide the current value that increases with E point current potential exponentially after conducting, and transistor P2 can provide the current value that becomes biquadratic to increase with E point current potential after conducting.Therefore, for instance, when positive electrostatic potential produced, E point current potential can be clamped down between the 0.7V to 1V when the oscillator signal of Node B is drawn high, and can be clamped down on when the oscillator signal reduction of Node B between-0.6 to-2V.Therefore, the average potential at node E can fall within about pact-1V.
Fig. 5 has shown the electrostatic discharge protective circuit in the fourth embodiment of the invention.With Fig. 4 relatively after as can be known, the electrostatic discharge protective circuit among Fig. 5 has used the diode D2 of polyphone to replace transistor P2 among Fig. 4.With two diode D2 is example, the diode D2 of this polyphone can node E current potential less than two turn-on voltages (2 *-conducting 0.7V=-1.4V) time, make in the average back bias voltage on the shunting transistor N1 grid between-1.5 to-2V, to avoid causing too greatly the oxide layer collapse of transistor N1 because of this negative voltage.
Fig. 6 has shown the electrostatic discharge protective circuit in the fifth embodiment of the invention, comprises the instantaneous back bias voltage generator 61 of a static, is coupled to a grid in order to shunting transistor N1 that electrostatic discharging path is provided.In addition, also comprise a transistor N2, its drain electrode is coupled to the grid of transistor N1, and source electrode is coupled to Node B, and grid then is coupled to node F.
The instantaneous back bias voltage generator 61 of static has comprised that one is coupled between node A and the B and is connected in the resistance R 2 between electric charge pump circuit 612 and shunting transistor N1 grid in static ringing device 611, an electric charge pump circuit 612 and that receives oscillator signal that node C exports an oscillator signal.Wherein, electric charge pump circuit 612 is made up of capacitor C 2 and diode D1.Static ringing device 611 has comprised capacitor C 1, resistance R 1, a reverse logic door, as NOR gate (NOR gate) X1, three reverser X2, X3 and X4.When positive electrostatic potential at the beginning of node A produces, along with the rising of electrostatic potential, at node C the oscillator signal that an amplitude increases gradually can appear, on the node E also can with the voltage spike of generation negative sense.After the low-pass filter effect of voltage spike on the node E via the gate-to-source parasitic capacitance of resistance R 2 and transistor N1, can produce one more smooth, the average potential bias voltage between-1 to-2V on the node D.The size of capacitor C 1 and resistance R 1 formed RC time constant (about 30--200ns) can make the current potential of node F remain on electronegative potential at the beginning of the manikin static discharge takes place, static ringing device 611 can be vibrated, and stop the vibration of static ringing device 611 at static discharge process latter end, also when normal electric power starting, static ringing device 611 is vibrated simultaneously.In normal power-up procedure, owing to being pulled to high potential, node F makes transistor N2 conducting, therefore can remain on electronegative potential and make transistor N1 be in stable closed condition by node D.
In the embodiment of Fig. 6, transistor N2 can be replaced by parallel resistor R3 among Fig. 3 and capacitor C 3, or replaces with the resistance R among Fig. 43.In addition, the NOR door X1 in Fig. 6 can also be replaced by a NAND door after resistance R 1 and capacitor C 1 are exchanged.
Fig. 7 shows the method for the electrostatic discharge protective circuit of rapid triggering one integrated circuit in one embodiment of the invention.
In the method for the electrostatic discharge protective circuit of rapid triggering one integrated circuit of present embodiment; electrostatic discharge protective circuit comprises a MOS (metal-oxide-semiconductor) transistor; its drain electrode is coupled to a first node; this node can be a weld pad or a VDD power bus; and source electrode is coupled to a Section Point, and Section Point can be a VSS power bus.
In step 71, when an electrostatic potential adds all first nodes, produce an oscillator signal.
In step 72, utilize oscillator signal to produce one and add all grids in this MOS (metal-oxide-semiconductor) transistor with the reverse negative voltage of electrostatic potential.In addition, when this integrated circuit normal running, this MOS (metal-oxide-semiconductor) transistor remains on closing state.
Comprehensively above-mentioned; the invention provides a kind of electrostatic discharge protective circuit of rapid triggering; when a positive electrostatic potential produces; can on the grid of shunting transistor, produce an instantaneous negative voltage; tradition uses the electrostatic discharge protective circuit of gate coupled N transistor npn npn to have better electrostatic protection effect, is specially adapted to use thickness of grid oxide layer below 40 or the transistor below 20 .
Though the present invention is open with preferred embodiment; right its is not in order to qualification the present invention, any those of ordinary skill in the art, without departing from the spirit and scope of the present invention; can do some equivalence and change and modification, so protection scope of the present invention is as the criterion with claim.
Claims (21)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
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| CNB021513406A CN1316706C (en) | 2002-11-15 | 2002-11-15 | Fast triggering electrostatic protection circuit and method thereof |
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| Application Number | Priority Date | Filing Date | Title |
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| CNB021513406A CN1316706C (en) | 2002-11-15 | 2002-11-15 | Fast triggering electrostatic protection circuit and method thereof |
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| CN1501561A true CN1501561A (en) | 2004-06-02 |
| CN1316706C CN1316706C (en) | 2007-05-16 |
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Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101834182A (en) * | 2010-03-23 | 2010-09-15 | 浙江大学 | Grid coupling NMOS (Negative-channel Metal-Oxide Semiconductor) tube modulated by dynamic grid resistance |
| CN101364731B (en) * | 2007-08-06 | 2010-10-06 | 北京中电华大电子设计有限责任公司 | Electrostatic discharge protecting circuit for USB interface chip |
| CN101093984B (en) * | 2006-01-06 | 2011-05-11 | 三星电子株式会社 | Voltage clamping circuits and semiconductor chips and methods of clamping voltages |
| CN107369672A (en) * | 2016-05-12 | 2017-11-21 | 瑞昱半导体股份有限公司 | ESD protection circuit |
| CN108335681A (en) * | 2018-02-13 | 2018-07-27 | 京东方科技集团股份有限公司 | It is a kind of for the antistatic unit of thin film transistor (TFT), driving circuit and display device |
| US10608429B2 (en) | 2016-05-09 | 2020-03-31 | Realtek Semiconductor Corporation | Electro-static discharge protection circuit |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI693766B (en) * | 2018-04-18 | 2020-05-11 | 力旺電子股份有限公司 | Electrostatic discharge protection device |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6091593A (en) * | 1997-10-22 | 2000-07-18 | Winbond Electronics Corp. | Early trigger of ESD protection device by a negative voltage pump circuit |
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2002
- 2002-11-15 CN CNB021513406A patent/CN1316706C/en not_active IP Right Cessation
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101093984B (en) * | 2006-01-06 | 2011-05-11 | 三星电子株式会社 | Voltage clamping circuits and semiconductor chips and methods of clamping voltages |
| CN101364731B (en) * | 2007-08-06 | 2010-10-06 | 北京中电华大电子设计有限责任公司 | Electrostatic discharge protecting circuit for USB interface chip |
| CN101834182A (en) * | 2010-03-23 | 2010-09-15 | 浙江大学 | Grid coupling NMOS (Negative-channel Metal-Oxide Semiconductor) tube modulated by dynamic grid resistance |
| US10608429B2 (en) | 2016-05-09 | 2020-03-31 | Realtek Semiconductor Corporation | Electro-static discharge protection circuit |
| CN107369672A (en) * | 2016-05-12 | 2017-11-21 | 瑞昱半导体股份有限公司 | ESD protection circuit |
| CN108335681A (en) * | 2018-02-13 | 2018-07-27 | 京东方科技集团股份有限公司 | It is a kind of for the antistatic unit of thin film transistor (TFT), driving circuit and display device |
Also Published As
| Publication number | Publication date |
|---|---|
| CN1316706C (en) | 2007-05-16 |
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