CN106411303A - Anti-creeping MOS switch structure applicable to integrated circuit - Google Patents

Abstract

The invention discloses an anti-leakage MOS switch structure suitable for integrated circuits, comprising one PMOS transistor MP1, two NMOS transistors MN4, MN5 and one operational amplifier AMP1 with single-ended output; that is, on the basis of series NMOS switches Above, an operational amplifier AMP1 is added to realize the source-drain voltage follower control of the NMOS switch. The operational amplifier AMP1 is connected to the circuit when the NMOS switch is turned off, so as to ensure that the source and drain voltages of the NMOS switch can still be kept equal when the NMOS switch is turned off, and prevent the NMOS switch from generating leakage current; the operational amplifier is disconnected from the circuit when the NMOS switch is turned on , without affecting the switching performance. The operational amplifier used is implemented with a simple five-tube operational amplifier structure, which has a simple structure, occupies a small area and consumes little power. Through the switch structure proposed by the present invention, the node voltage variation caused by the leakage current of the MOS switch can be significantly reduced, and the effective protection of key nodes can be realized.

Description

An anti-leakage MOS switch structure suitable for integrated circuits

technical field

The invention relates to the field of analog integrated circuits, in particular to an anti-leakage MOS switch structure that can be used in digital and analog mixed signal circuits.

Background technique

The rapid development of semiconductor technology has brought great changes to people's lives. High-tech electronic products are used in all aspects of life, including shopping malls, supermarkets, hotels, restaurants, railway stations, airports, etc., which facilitate people's basic necessities of life and improve people's lives. Among them, the CMOS process is the most important process technology in the semiconductor industry due to its low cost and mature process.

In recent years, before Moore's Law expired, the critical dimension of CMOS process decreased year by year, from 0.8 micron to 0.18 micron, 14 nanometers or even smaller. As the critical size of CMOS decreases, the operating voltage and gate voltage of MOS transistors decrease, and at the same time, the gate oxide layer thickness and channel length of MOS transistors also decrease. In deep submicron or nanoscale integrated circuits, the phenomenon of leakage is becoming more and more significant, including the leakage caused by the thinning of the gate oxide layer of the MOS transistor, and the subthreshold leakage between the source and drain of the MOS transistor.

In digital integrated circuits, leakage currents can lead to a significant increase in circuit power consumption, and in severe cases, logic errors. In the field of analog and mixed-signal integrated circuits, the leakage current will cause the voltage of key nodes to change, so that the node that should have been conserved in charge has a current path to the ground or to the power supply, resulting in a change in charge, resulting in an error in the voltage signal. Therefore, on key nodes that require special protection, special designs must be used to reduce errors caused by leakage.

Contents of the invention

In order to solve the error caused by the above-mentioned leakage problem, the present invention proposes an anti-leakage MOS switch structure suitable for integrated circuits, including PMOS transistor MP1, NMOS transistor MN4 and NMOS transistor MN5 and an operational amplifier AMP1 with single-ended output; The NMOS transistor MN4 and the NMOS transistor MN5 are MOS switches on the signal transmission path, and the PMOS transistor MP1 is a switch for controlling the output feedback signal of the single-ended output operational amplifier AMP1; the source of the NMOS transistor MN4 is connected to the input signal, The drain of the NMOS transistor MN4 is connected to the source of the NMOS transistor MN5 and the source of the PMOS transistor MP1 at the same time, the gate of the NMOS transistor MN4 is connected to the clock signal CLK; the drain of the NMOS transistor MN5 is connected to the signal output terminal and the operational amplifier AMP1 The positive phase input terminal of the NMOS transistor MN5 is connected to the clock signal CLK; the source of the PMOS transistor MP1 is connected to the drain of the NMOS transistor MN4, the drain of the PMOS transistor MP1 is connected to the output terminal of the operational amplifier AMP, and the gate of the PMOS transistor MP1 The pole is connected to the clock signal CLK; the positive input terminal of the operational amplifier AMP1 is connected to the signal output terminal, and the negative input terminal of the operational amplifier AMP1 is connected to the output terminal of the operational amplifier AMP1 and then connected to the drain of the PMOS transistor MP1.

Wherein, the operational amplifier AMP1 adopts a five-tube operational amplifier structure.

The operational amplifier AMP1 includes 4 NMOS transistors, 2 PMOS transistors and 1 resistor R1; wherein, the 4 NMOS transistors are respectively recorded as NMOS transistor NMOS6, NMOS transistor NMOS7, NMOS transistor NMOS8 and NMOS transistor NMOS9, and 2 PMOS transistors They are respectively recorded as PMOS transistor MP2 and PMOS transistor MP3; one end of resistor R1 is connected to the power supply VDD, and the other end of resistor R1 is connected to the gate and drain of NMOS transistor MN6 at the same time; the source of NMOS transistor MN6 is grounded, and the gate of NMOS transistor MN6 The drain of the NMOS transistor MN6 is simultaneously connected to the gate of the NMOS transistor MN7; the source of the NMOS transistor MN7 is grounded, and the drain of the NMOS transistor MN7 is simultaneously connected to the sources of the NMOS transistor MN8 and the NMOS transistor MN9; the gate of the NMOS transistor MN8 It is the positive phase input terminal of the op amp, the source of the NMOS transistor MN8 is connected to the drain of the NMOS transistor MN7, and the drain of the NMOS transistor MN8 is connected to the drain and gate of the PMOS transistor MP2 at the same time; the gate of the NMOS transistor MN9 is the op amp negative Phase input terminal, the source of the NMOS transistor MN9 is connected to the drain of the NMOS transistor MN7, the drain of the NMOS transistor MN9 is connected to the drain of the PMOS transistor MP3, the source of the PMOS transistor MP3 is connected to the power supply VDD, and the gate of the PMOS transistor MP3 is connected to the PMOS The gate of the transistor MP2 and the drain of the PMOS transistor MP3 are the output terminals of the operational amplifier.

Compared with the prior art, an anti-leakage MOS switch structure suitable for integrated circuits proposed by the present invention is based on the series connection of NMOS switches, and an operational amplifier is added to realize the source-drain voltage following control of the NMOS switches. The operational amplifier is connected to the circuit when the NMOS switch is turned off, so as to ensure that the source and drain voltages of the NMOS switch tube can still be kept equal when the NMOS switch is turned off, so as to prevent the NMOS switch from generating leakage current; the operational amplifier is disconnected from the circuit when the NMOS switch is turned on, No impact on switching performance. The operational amplifier used is implemented with a simple five-tube operational amplifier structure, which has a simple structure, occupies a small area and consumes little power. Through the switch structure proposed by the present invention, the node voltage variation caused by the leakage current of the MOS switch can be significantly reduced, and the effective protection of key nodes can be realized.

Description of drawings

Figure 1 is a schematic diagram of a traditional NMOS switch;

Figure 2 is a schematic diagram of an anti-leakage series NMOS switch;

Fig. 3 is the schematic diagram of the anti-leakage switch proposed by the present invention;

Figure 4 is a schematic diagram of the operational amplifier AMP1.

detailed description

The present invention will be further described in detail below in combination with specific embodiments.

The traditional NMOS switch structure is shown in FIG. 1 , wherein the NMOS transistor MN1 is used as a switch under the control of the clock CLK. When CLK is high level, MN1 is turned on, the switch is turned on, the source and drain voltages of MN1 are equal, the load C1 is driven by the signal source, VC=VA; when CLK is low level, MN1 is turned off, the switch is turned off, and the capacitor on the right side of MN1 The voltage before MN1 cut-off remains unchanged on C1. But in fact, due to the leakage current between the source and the drain of MN1, the capacitor C1 is continuously charged or discharged, and the voltage on the capacitor C1 will change after a period of time, resulting in an error.

A simple improved switch, that is, an anti-leakage series NMOS switch is shown in Figure 2, in which the NMOS transistors MN2 and MN3 are used as switches under the control of the clock CLK. When CLK is high level, MN2 and MN3 are turned on, the switch is turned on, capacitor C2 is driven by the signal source, and the voltages of the three nodes VA, VB, and VC are equal; when CLK is low level, MN2 and MN3 are turned off, and capacitor C2 Keep the voltage constant before the switch is turned off. But in fact, due to the existence of the leakage current, the voltage on the capacitor C2 will still change slowly. The main reason for the leakage between the source and drain of the MOS tube is that the source-drain voltage is different when the MOS tube is off, and the greater the voltage difference, the more obvious the leakage phenomenon. Compared with the traditional structure shown in FIG. 1 , when the switch is turned off, the voltage of VB will be between VA and VC, and the leakage current on MN3 will be smaller than the leakage current on MN1 in FIG. 1 . The switch shown in Figure 2 reduces the leakage current by reducing the voltage difference between the source and the drain when the MOS tube is off.

As shown in Figure 3, a kind of anti-leakage MOS switch structure that the present invention proposes is suitable for integrated circuit, comprises PMOS transistor MP1, NMOS transistor MN4 and NMOS transistor MN5 and the operational amplifier AMP1 of a single-ended output; Said NMOS transistor MN4 and NMOS transistor MN5 are MOS switches on the signal transmission path, and the PMOS transistor MP1 is a switch for controlling the output feedback signal of the single-ended output operational amplifier AMP1; the source of the NMOS transistor MN4 is connected to the input signal, and the NMOS transistor MN4 The drain of the tube MN4 is connected to the source of the NMOS tube MN5 and the source of the PMOS tube MP1 at the same time, the gate of the NMOS tube MN4 is connected to the clock signal CLK; the drain of the NMOS tube MN5 is connected to the signal output terminal and the positive phase of the operational amplifier AMP1 At the input end, the gate of the NMOS transistor MN5 is connected to the clock signal CLK; the source of the PMOS transistor MP1 is connected to the drain of the NMOS transistor MN4, the drain of the PMOS transistor MP1 is connected to the output terminal of the operational amplifier AMP, and the gate of the PMOS transistor MP1 is connected to the clock Signal CLK; the positive phase input terminal of the operational amplifier AMP1 is connected to the signal output terminal, and the negative phase input terminal of the operational amplifier AMP1 is connected to the output terminal of the operational amplifier AMP1 and then connected to the drain of the PMOS transistor MP1.

The principle of the anti-leakage MOS switch of the present invention is that when the switch is turned on, the operational amplifier AMP1 is disconnected from the circuit, which does not affect the normal function of the switch; when the switch is cut off, the operational amplifier AMP1 is connected to the circuit in the form of a unity gain buffer, The source and drain of the switch tube MN5 directly connected to the load are clamped to the same voltage to prevent the charge on the load from leaking through the switch MOS tube. The specific working method is as follows. When CLK is at a high level, the NMOS transistors MN4 and MN5 are turned on, and the PMOS transistor MP1 is turned off. At this time, the output terminal of the operational amplifier AMP1 is disconnected from the circuit, and the positive phase input terminal of the operational amplifier AMP1 is connected in parallel with the load capacitor C3. , since the input terminal of the operational amplifier AMP1 is a high-impedance node, no current will pass through, which will not affect the performance of the circuit. When CLK is at low level, the NMOS transistors MN4 and MN5 are disconnected, and the PMOS transistor MP1 is turned on. At this time, the output terminal of the operational amplifier AMP1 is connected to the node VB. The negative phase input terminal of the operational amplifier is connected to the output terminal as a unity gain buffer, so that the voltages of VB and VC nodes are equal, and the voltages of the source and drain of MN5 are equal, so there is almost no leakage current on the switch tube MN5. Finally, the effect of preventing the voltage change of the load capacitor node VC caused by the leakage of the switch is realized.

The structure of the operational amplifier AMP1 used in the anti-leakage switch structure of the present invention is shown in Figure 4, which is a five-transistor operational amplifier structure input by ordinary NMOS tubes, and the bias is generated by the resistor R1, the structure is simple, and the area and power consumption are saved. The operational amplifier AMP1 includes 4 NMOS transistors, 2 PMOS transistors and 1 resistor R1; wherein, the 4 NMOS transistors are respectively recorded as NMOS transistor NMOS6, NMOS transistor NMOS7, NMOS transistor NMOS8 and NMOS transistor NMOS9, and 2 PMOS transistors They are respectively recorded as PMOS transistor MP2 and PMOS transistor MP3; one end of resistor R1 is connected to the power supply VDD, and the other end of resistor R1 is connected to the gate and drain of NMOS transistor MN6 at the same time; the source of NMOS transistor MN6 is grounded, and the gate of NMOS transistor MN6 The drain of the NMOS transistor MN6 is simultaneously connected to the gate of the NMOS transistor MN7; the source of the NMOS transistor MN7 is grounded, and the drain of the NMOS transistor MN7 is simultaneously connected to the sources of the NMOS transistor MN8 and the NMOS transistor MN9; the gate of the NMOS transistor MN8 It is the positive phase input terminal of the op amp, the source of the NMOS transistor MN8 is connected to the drain of the NMOS transistor MN7, and the drain of the NMOS transistor MN8 is connected to the drain and gate of the PMOS transistor MP2 at the same time; the gate of the NMOS transistor MN9 is the op amp negative Phase input terminal, the source of the NMOS transistor MN9 is connected to the drain of the NMOS transistor MN7, the drain of the NMOS transistor MN9 is connected to the drain of the PMOS transistor MP3, the source of the PMOS transistor MP3 is connected to the power supply VDD, and the gate of the PMOS transistor MP3 is connected to the PMOS The gate of the transistor MP2 and the drain of the PMOS transistor MP3 are the output terminals of the operational amplifier.

To sum up, the anti-leakage MOS switch structure proposed by the present invention is based on the series connection of NMOS switches, and an operational amplifier is added to realize the source-drain voltage following control of the NMOS switches. The operational amplifier is connected to the circuit when the NMOS switch is turned off, so as to ensure that the source and drain voltages of the NMOS switch tube can still be kept equal when the NMOS switch is turned off, so as to prevent the NMOS switch from generating leakage current; the operational amplifier is disconnected from the circuit when the NMOS switch is turned on, No impact on switching performance. The operational amplifier used is implemented with a simple five-tube operational amplifier structure, which has a simple structure, occupies a small area and consumes little power. Through the switch structure proposed by the present invention, the node voltage variation caused by the leakage current of the MOS switch can be significantly reduced, and the effective protection of key nodes can be realized.

Although the present invention has been described above in conjunction with the drawings, the present invention is not limited to the above-mentioned specific embodiments, and the above-mentioned specific embodiments are only illustrative, rather than restrictive. Under the inspiration, many modifications can be made without departing from the gist of the present invention, and these all belong to the protection of the present invention.

Claims (3)

1. a kind of anticreep MOS switch structure be applied to integrated circuit is it is characterised in that include PMOS MP1, NMOS tube MN4 and operational amplifier A MP1 of NMOS tube MN5 and a Single-end output；Described NMOS tube MN4 and NMOS tube MN5 are that signal passes MOS switch on defeated path, described PMOS MP1 is to control described Single-end output operational amplifier A MP1 output feedback signal Switch；

The source electrode of described NMOS tube MN4 connects input signal, and the drain electrode of described NMOS tube MN4 is simultaneously connected with the source of NMOS tube MN5 Pole and the source electrode of PMOS MP1, NMOS tube MN4 grid connects clock signal clk；The drain electrode of NMOS tube MN5 connects signal output End and the normal phase input end of described operational amplifier A MP1, the grid of NMOS tube MN5 connects clock signal clk；PMOS MP1 The drain electrode of source electrode connection NMOS tube MN4, the output end of the drain electrode concatenation operation amplifier AMP of PMOS MP1, PMOS MP1 Grid connects clock signal clk；The normal phase input end of operational amplifier A MP1 and signal output part connect, operational amplifier A MP1 Negative-phase input be connected with the output end of operational amplifier A MP1 after and connect to the drain electrode of PMOS MP1.

2. according to claim 1 the anticreep MOS switch structure be applied to integrated circuit it is characterised in that described fortune Calculate amplifier AMP1 and adopt five pipe amplifier structures.

3. according to claim 2 the anticreep MOS switch structure be applied to integrated circuit it is characterised in that described fortune Calculate amplifier AMP1 and include 4 NMOS tube, 2 PMOS and 1 resistance R1；Wherein, 4 NMOS tube are denoted as NMOS tube respectively NMOS6, NMOS tube NMOS7, NMOS tube NMOS8 and NMOS tube NMOS9,2 PMOS are denoted as PMOS MP2 and PMOS respectively MP3；

One end of resistance R1 connects power vd D, and the other end of resistance R1 connects grid and the drain electrode of NMOS tube MN6 simultaneously；NMOS tube The source ground of MN6, the grid of NMOS tube MN6 and the drain electrode of NMOS tube MN6 are simultaneously connected to the grid of NMOS tube MN7；NMOS The source ground of pipe MN7, the drain electrode of NMOS tube MN7 is simultaneously connected with the source electrode of NMOS tube MN8 and NMOS tube MN9；NMOS tube MN8 Grid is amplifier normal phase input end, and the source electrode of NMOS tube MN8 connects the drain electrode of NMOS tube MN7, and the drain electrode of NMOS tube MN8 connects simultaneously Connect the drain and gate of PMOS MP2；The grid of NMOS tube MN9 is amplifier negative-phase input, and the source electrode of NMOS tube MN9 connects The drain electrode of NMOS tube MN7, the drain electrode of NMOS tube MN9 connects the drain electrode of PMOS MP3, and the source electrode of PMOS MP3 connects power supply VDD, the grid of PMOS MP3 connects the grid of PMOS MP2, and the drain electrode of PMOS MP3 is amplifier output end.