CN109687863B - Drive circuit of RS485 chip - Google Patents

Drive circuit of RS485 chip Download PDF

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Publication number
CN109687863B
CN109687863B CN201811624935.1A CN201811624935A CN109687863B CN 109687863 B CN109687863 B CN 109687863B CN 201811624935 A CN201811624935 A CN 201811624935A CN 109687863 B CN109687863 B CN 109687863B
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tube
pmos
nmos tube
nmos
pmos tube
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CN109687863A (en
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赵海亮
阮颐
常祥岭
刘燕涛
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Shanghai Beiling Co Ltd
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Shanghai Beiling Co Ltd
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H03K19/0185—Coupling arrangements; Interface arrangements using field effect transistors only
    • H03K19/018507—Interface arrangements
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0008—Arrangements for reducing power consumption
    • H03K19/0013—Arrangements for reducing power consumption in field effect transistor circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/003—Modifications for increasing the reliability for protection
    • H03K19/00315—Modifications for increasing the reliability for protection in field-effect transistor circuits

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

The invention discloses a driving circuit of an RS485 chip. The drive circuit includes: the interface end, the PMOS tube passage and the NMOS tube passage; one end of the PMOS tube passage is connected with a power supply, the other end of the PMOS tube passage is connected with the interface end and one end of the NMOS tube passage, and the other end of the NMOS tube passage is grounded; the interface end is used for connecting with an A pin or a B pin of the RS485 chip. The invention realizes the driving circuit of the RS485 chip through the PMOS tube passage and the NMOS tube passage, can reduce EMI (electromagnetic interference) and reflection caused by improper cable termination, improves the reliability of data transmission, and realizes high-speed and error-free data transmission. And can meet the RS485 remote data transmission application standard of the national network standard.

Description

Drive circuit of RS485 chip
Technical Field
The invention relates to the technical field of electronics, in particular to a driving circuit of an RS485 chip.
Background
RS-485 is a low-cost and reliable communication standard, and can be used in the application fields of networking of an electric meter system and the like. The RS-485 communication interface adopts a differential level mode for transmission and works in a half-duplex mode. At any one time, the RS-485 transceiver can only work in one of two modes of receiving or sending, therefore, the reversing control of the receiving/sending logic of the RS-485 interface circuit is needed.
In the prior art, a software program is generally adopted to realize the commutation control or a hardware circuit is adopted to realize the commutation control. However, the adoption of software programs to realize the reversing control occupies the I/O pin resource of a CPU, cannot ensure good anti-interference performance, and causes data loss due to certain time delay; the commutation control is realized by adopting a hardware circuit, most of the prior art is based on an inverter and is combined with a matched resistor, but the inverter has high power consumption on one hand and poor reliability on the other hand, and high-speed error-free data transmission is difficult to ensure.
Disclosure of Invention
The invention aims to overcome the defect of poor reliability of a driving circuit of an RS-485 interface chip in the prior art, and provides the driving circuit of the RS485 chip.
The invention solves the technical problems through the following technical scheme:
the utility model provides a drive circuit of RS485 chip, RS485 chip includes A pin and B pin, drive circuit includes: the interface end, the PMOS tube passage and the NMOS tube passage;
one end of the PMOS tube passage is connected with a power supply, the other end of the PMOS tube passage is connected with the interface end and one end of the NMOS tube passage, and the other end of the NMOS tube passage is grounded;
the interface end is used for connecting the A pin or the B pin.
Preferably, the RS485 chip further includes: a DI pin (data input pin of the transmit driver) and an overvoltage protection circuit;
the PMOS pipe path comprises: the transistor comprises a first PMOS (P-channel metal oxide semiconductor) tube, a second PMOS tube, a third PMOS tube, a first resistor, a second resistor, a third resistor and a fourth resistor;
the source electrode of the first PMOS tube is respectively connected with one end of the first resistor and the power supply, and the drain electrode of the first PMOS tube is respectively connected with the other end of the first resistor, the source electrode of the second PMOS tube and the source electrode of the third PMOS tube;
the drain electrode of the second PMOS tube is connected with the interface end through the second resistor;
the drain electrode of the third PMOS tube is connected with the interface end through the third resistor;
one end of the fourth resistor is connected with the drain electrode of the first PMOS tube, and the other end of the fourth resistor is connected with the interface end;
the grid electrode of the first PMOS tube is connected with the overvoltage protection circuit; the grid electrodes of the second PMOS tube and the third PMOS tube are connected with the DI pin;
the overvoltage protection circuit is used for detecting voltage values of the pin A and the pin B, judging whether the voltage values are within a preset range, and outputting a low level to a grid electrode of the first PMOS tube when the voltage values are judged to be within the preset range.
Preferably, the driving circuit further comprises a fourth PMOS transistor;
the source electrode of the fourth PMOS tube is connected with the drain electrode of the first PMOS tube, the drain electrode of the fourth PMOS tube is connected with the interface end through the fourth resistor, and the grid electrode of the fourth PMOS tube is connected with the overvoltage protection circuit;
and the overvoltage protection circuit is also used for outputting a low level to the grid electrode of the fourth PMOS tube when the judgment result is yes.
Preferably, the NMOS pipe path includes: the first NMOS tube, the second NMOS tube, the third NMOS tube, the fifth resistor, the sixth resistor, the seventh resistor and the eighth resistor;
the source electrode of the first NMOS tube is connected with one end of the fifth resistor and is grounded, and the drain electrode of the first NMOS tube is respectively connected with the other end of the fifth resistor, the source electrode of the second NMOS tube and the source electrode of the third NMOS tube;
the drain electrode of the second NMOS tube is connected with the interface end through the sixth resistor;
the drain electrode of the third NMOS tube is connected with the interface end through the seventh resistor;
one end of the eighth resistor is connected with the drain electrode of the first NMOS tube, and the other end of the eighth resistor is connected with the interface end;
the grid electrode of the first NMOS tube is connected with the overvoltage protection circuit; the grid electrodes of the second NMOS tube and the third NMOS tube are connected with the DI pin;
and the overvoltage protection circuit is also used for outputting a high level to the grid electrode of the first NMOS tube when the judgment result is yes.
Preferably, the driving circuit further comprises a fourth NMOS transistor;
the source electrode of the fourth NMOS tube is connected with the drain electrode of the first NMOS tube, the drain electrode of the fourth NMOS tube is connected with the interface end through the eighth resistor, and the grid electrode of the fourth NMOS tube is connected with the overvoltage protection circuit;
and the overvoltage protection circuit is also used for outputting a high level to the grid electrode of the fourth NMOS tube when the judgment result is yes.
Preferably, the driving circuit further comprises: a polarity judgment path;
when the interface end is connected with the pin A, the output end of the polarity judging passage is connected with the grid electrode of the third PMOS tube and the grid electrode of the third NMOS tube;
when the interface end is connected with the pin B, the output end of the polarity judging path is connected with the grid electrode of the third PMOS tube and the grid electrode of the third NMOS tube through a phase inverter;
the polarity judging path is used for detecting whether the pin A is connected with a positive connection wire of the RS485 bus or not, whether the pin B is connected with a negative connection wire of the RS485 bus or not, and outputs a low level when the pin A is judged to be positive, and outputs a high level when the pin B is judged to be negative.
Preferably, the first PMOS transistor, the second PMOS transistor, the third PMOS transistor and the fourth PMOS transistor each include a parasitic diode;
the anode of the parasitic diode of the first PMOS tube is connected with the source electrode of the first PMOS tube, and the cathode of the parasitic diode of the first PMOS tube is connected with the drain electrode of the first PMOS tube;
the anode of the parasitic diode of the second PMOS tube is connected with the drain electrode of the second PMOS tube, and the cathode of the parasitic diode of the second PMOS tube is connected with the source electrode of the second PMOS tube;
the anode of the parasitic diode of the third PMOS tube is connected with the drain electrode of the third PMOS tube, and the cathode of the parasitic diode of the third PMOS tube is connected with the source electrode of the third PMOS tube;
and the anode of the parasitic tetrode of the fourth PMOS tube is connected with the drain electrode of the fourth PMOS tube, and the cathode of the parasitic tetrode of the fourth PMOS tube is connected with the source electrode of the fourth PMOS tube.
Preferably, the first NMOS transistor, the second NMOS transistor, the third NMOS transistor, and the fourth NMOS transistor each include a parasitic diode;
the anode of the parasitic diode of the first NMOS tube is connected with the drain electrode of the first NMOS tube, and the cathode of the parasitic diode of the first NMOS tube is connected with the source electrode of the first NMOS tube;
the anode of the parasitic diode of the second NMOS tube is connected with the source electrode of the second NMOS tube, and the cathode of the parasitic diode of the second NMOS tube is connected with the drain electrode of the second NMOS tube;
the anode of the parasitic diode of the third NMOS tube is connected with the source electrode of the third NMOS tube, and the cathode of the parasitic diode of the third NMOS tube is connected with the drain electrode of the third NMOS tube;
and the anode of the parasitic tetrode of the fourth NMOS tube is connected with the source electrode of the fourth NMOS tube, and the cathode of the parasitic tetrode of the fourth NMOS tube is connected with the drain electrode of the fourth NMOS tube.
The positive progress effects of the invention are as follows: the driving circuit of the RS485 chip is realized through the PMOS pipe passage and the NMOS pipe passage, so that the reflection caused by EMI (electromagnetic interference) and improper cable termination can be reduced, the reliability of data transmission is improved, and high-speed error-free data transmission is realized. And can meet the RS485 remote data transmission application standard of the national network standard.
Drawings
Fig. 1 is a partial circuit diagram of a driving circuit of an RS485 chip according to embodiment 1 of the present invention.
Fig. 2 is a partial circuit diagram of a driving circuit of an RS485 chip according to embodiment 2 of the present invention.
Detailed Description
The invention is further illustrated by the following examples, which are not intended to limit the scope of the invention.
Example 1
The embodiment provides a drive circuit of an RS485 chip, and the RS485 chip comprises an overvoltage protection circuit, a pin A and a pin B, wherein the pin A and the pin B are both connected with one-way drive circuit. For convenience of understanding, in this embodiment, a driver circuit connected to the a pin is referred to as a first driver circuit, and a circuit connected to the B pin is referred to as a second driver circuit.
In this embodiment, as shown in fig. 1, the driving circuit includes: interface terminal 1, PMOS pipe path 2 and NMOS pipe path 3. One end of the PMOS tube passage 2 is connected with a power supply VDD, the other end of the PMOS tube passage is connected with the interface end 1 and one end of the NMOS tube passage 3, and the other end of the NMOS tube passage 3 is grounded. And the pin A or the pin B of the RS485 chip is connected with the driving circuit through an interface end.
Specifically, the PMOS transistor path includes: the transistor comprises a first PMOS (P-channel metal oxide semiconductor) transistor M1, a second PMOS transistor M2, a third PMOS transistor M3, a first resistor R1, a second resistor R2, a third resistor R3 and a fourth resistor R4; a source electrode of the first PMOS tube M1 is respectively connected with one end of the first resistor R1 and a power supply VDD, and a drain electrode of the first PMOS tube M1 is respectively connected with a source electrode of the second PMOS tube M2, a source electrode of the third PMOS tube M3 and the other end of the first resistor R1; the drain electrode of the second PMOS M2 is connected with the interface end 1 through a second resistor R2; the drain electrode of the third PMOS tube M3 is connected with the interface end 1 through a third resistor R3; one end of the fourth resistor R4 is connected with the drain electrode of the first PMOS tube M1, and the other end of the fourth resistor R4 is connected with the interface end 1.
The NMOS transistor path includes: a first NMOS transistor M5, a second NMOS transistor M6, a third NMOS transistor M7, a fifth resistor R5, a sixth resistor R6, a seventh resistor R7 and an eighth resistor R8; the source electrode of the first NMOS tube M5 is connected with one end of the fifth resistor R5 and is grounded, and the drain electrode of the first NMOS tube M5 is respectively connected with the source electrode of the second NMOS tube M6, the source electrode of the third NMOS tube M7 and the other end of the fifth resistor R5; the drain electrode of the second NMOS tube M6 is connected with the interface end 1 through a sixth resistor R6; the drain electrode of the third NMOS tube M7 is connected with the interface end 1 through a seventh resistor R7; one end of the eighth resistor R8 is connected to the drain of the first NMOS transistor M5, and the other end of the eighth resistor R8 is connected to the interface terminal 1.
The grids of the second PMOS tube M2, the third PMOS tube M3, the second NMOS tube M6 and the third NMOS tube M7 are all connected with a DI pin of the RS485 chip. The grid electrode of the first PMOS tube M1 and the grid electrode of the first NMOS tube M5 are connected with the protection circuit.
The overvoltage protection circuit is used for detecting the voltage value of an A/B pin of the RS485 chip, when the voltage of the A/B pin is in the range of 0-5V, the overvoltage protection circuit generates a normal signal, the grid GP _ T of the first PMOS tube M1 is in a low level, the grid GN _ L node of the first NMOS tube M5 is in a high level, the first PMOS tube M1 and the first NMOS tube M5 are kept in a conducting state, and the first resistor R1 and the fifth resistor R5 which are respectively connected with the first PMOS tube M1 and the NMOS tube M5 in parallel ensure that a logic path can be generated.
The data of the DI pin is transmitted to four grids of a grid GP _ M of a second PMOS tube, a grid GP _ S of a third PMOS tube, a grid GN _ M of a second NMOS tube and a grid GN _ S of a third NMOS tube of the output stage, and the grid GP _ S, the grid GN _ M of the second NMOS tube and the grid GN _ S of the third NMOS tube of the output stage respectively control a second PMOS tube M2, a third PMOS tube M3, a second NMOS tube M6 and a second NMOS tube M7 of the power output tube, so that the logic inversion of the A/B pin signal is driven.
In this embodiment, the driving circuit further includes: and a polarity judging path. The output end of the polarity judging passage is connected with the grid electrode of the third PMOS tube M3 and the grid electrode of the third NMOS tube M7 of the first driving circuit, and the output end of the polarity judging passage is also connected with the grid electrode of the third PMOS tube M3 and the grid electrode of the third NMOS tube M7 of the second driving circuit through an inverter.
The polarity judgment circuit is used for detecting whether the polarity of the RS485 chip is consistent with that of the RS485 bus, namely detecting whether a pin A of the RS485 chip is connected with a positive connection wire of the RS485 bus, and whether a pin B is connected with a negative connection wire of the RS485 bus, and when the polarities of the pin A and the pin B are consistent, the polarity judgment circuit outputs a low level, at the moment, a third PMOG tube M3 of the first driving circuit is conducted, a third NMOG tube M7 of the second driving circuit is conducted, namely a pull-up channel of the pin A is opened, and a pull-down channel of the pin B is opened; when the polarities of the first pin and the second pin are not consistent, the polarity judgment circuit outputs a high level, at the moment, the third NMOG tube M7 of the first driving circuit is conducted, the third PMOG tube M3 of the second driving circuit is conducted, namely, the pull-up channel of the pin B is opened, and the pull-down channel of the pin A is opened. Therefore, when automatic polarity judgment is realized, a pull-up path and a pull-down path are additionally arranged in the chip of the A/B pin.
In this embodiment, referring to fig. 1, in the PMOS channel, each PMOS transistor includes a parasitic diode, an anode of the parasitic diode of the first PMOS transistor is connected to a source of the first PMOS transistor, and a cathode of the parasitic diode of the first PMOS transistor is connected to a drain of the first PMOS transistor; the anode of a parasitic diode of the second PMOS tube is connected with the drain electrode of the second PMOS tube, and the cathode of the parasitic diode of the second PMOS tube is connected with the source electrode of the second PMOS tube; and the anode of the parasitic diode of the third PMOS tube is connected with the drain electrode of the third PMOS tube, and the cathode of the parasitic diode of the third PMOS tube is connected with the source electrode of the third PMOS tube. In the PMOS tube passage, parasitic diodes of the first PMOS tube, the second PMOS tube and the third PMOS tube are connected in a back-to-back mode, so that the high voltage of the A/B pin is prevented from being transmitted to the grid electrode of the first PMOS tube when the PMOS tubes are in an off state, and the current is prevented from flowing backwards. Meanwhile, the A/B pin can bear a wide working voltage in a positive and negative voltage range in the off state.
In the NMOS tube path, the parasitic diodes of the first NMOS tube, the second NMOS tube and the third NMOS tube are connected in a back-to-back mode, so that the high voltage of the A/B pin is prevented from being transmitted to the grid electrode of the first NMOS tube when the NMOS tubes are in an off state, and the current is prevented from flowing backwards.
The driving circuit of the embodiment can reduce EMI (electromagnetic interference) and reflection caused by improper cable termination, improve the reliability of data transmission, and realize high-speed error-free data transmission. The RS485 remote data transmission application standard of the national network standard can be met.
Example 2
On the basis of embodiment 1, as shown in fig. 2, in this embodiment, the PMOS transistor path further includes a fourth PMOS transistor M4; the source electrode of the fourth PMOS transistor M4 is connected to the drain electrode of the first PMOS transistor M1, and the drain electrode of the fourth PMOS transistor M4 is connected to the interface terminal 1 through a fourth resistor R4. The NMOS tube path further comprises a fourth NMOS tube M8; the source electrode of the fourth NMOS tube M8 is connected to the drain electrode of the first NMOS tube M5, and the drain electrode of the fourth NMOS tube M8 is connected to the interface terminal 1 through an eighth resistor R8. And a grid M4 of the fourth PMOS tube and a fourth NMOS tube M8 are both connected with the overvoltage protection circuit. When the voltage of the A/B pin is in the range of 0-5V, the overvoltage protection circuit outputs a low level to a grid electrode M4 of the fourth PMOS tube and outputs a high level to a fourth NMOS tube M8.
In this embodiment, each PMOS transistor is provided with a first enable transistor; and each NMOS tube is provided with a second enabling tube. When the driving circuit does not work, the output is required (namely, the A/B pin keeps a high-impedance state), and the enabling tube is used for keeping the NMOS tube M7/M8/M6 and the PMOS tube M3/M4/M2 in an off state when the driving circuit is required to be turned off.
The driving circuit of the embodiment can provide overcurrent protection of two mechanisms, and the protection principles of the two mechanisms are explained as follows:
(1) The overcurrent signal of the a/B pin sets the gate GP _ B of the fourth PMOS transistor M4 to a high level and the gate GN _ B of the fourth NMOS transistor M4 to a low level, thereby turning off the fourth PMOS transistor M4 and the fourth NMOS transistor M8, and only leaving the two transistors of the second PMOS transistor M2 and the second NMOS transistor M6 to be turned over, thereby playing a role in limiting current. The on-state large resistors (the second resistor R2 and the sixth resistor R6) respectively connected in series with the second PMOS transistor M2 and the second NMOS transistor M6 determine the magnitude of the current limiting value.
(2) When the voltage of the A/B pin exceeds 5V, the grid GP _ T of the first PMOS tube M1 is set to be at a high level, and the PD _ SD is pulled down (a PD _ SD signal is generated by an overvoltage protection circuit, and when the overvoltage protection circuit detects that the voltage of the A/B pin exceeds 5V, a low level control logic is generated), so that the PMOS tube M1 is turned off, the first enabling tube is completely turned on through the PMOS tubes controlled by the PD _ SD, and VGS =0 of the middle two rows of tubes (comprising the PMOS tubes M2/M3/M4 and the NMOS tubes M6/M7/M8) keeps a turned-off state.
Similarly, when the voltage of the a/B pin is lower than 0V, the gate GN _ L of the first NMOS transistor is set to a low level, and ND _ SD is pulled high, so that the first NMOS transistor M5 is turned off, the second enable transistor is turned on by all the NMOS transistors controlled by ND _ SD, and VGS =0 of the two middle rows of transistors maintains the off state.
In this embodiment, the driving circuit realizes overcurrent protection and power consumption overload protection of two mechanisms. When the bus is normally driven, when the current of the chip is overlarge due to the abnormal bus, an overcurrent protection circuit in the chip plays a role to ensure that the driving current cannot exceed a set value under certain conditions.
While specific embodiments of the invention have been described above, it will be understood by those skilled in the art that this is by way of example only, and that the scope of the invention is defined by the appended claims. Various changes and modifications to these embodiments may be made by those skilled in the art without departing from the spirit and scope of the invention, and these changes and modifications are within the scope of the invention.

Claims (6)

1. The utility model provides a drive circuit of RS485 chip, the RS485 chip includes A pin and B pin, its characterized in that, drive circuit includes: the interface end, the PMOS tube passage and the NMOS tube passage;
one end of the PMOS tube passage is connected with a power supply, the other end of the PMOS tube passage is connected with the interface end and one end of the NMOS tube passage, and the other end of the NMOS tube passage is grounded;
the interface end is used for connecting the pin A or the pin B;
the RS485 chip further comprises: a DI pin and an over-voltage protection circuit;
the PMOS pipe path comprises: the transistor comprises a first PMOS (P-channel metal oxide semiconductor) tube, a second PMOS tube, a third PMOS tube, a first resistor, a second resistor, a third resistor and a fourth resistor;
the source electrode of the first PMOS tube is respectively connected with one end of the first resistor and the power supply, and the drain electrode of the first PMOS tube is respectively connected with the other end of the first resistor, the source electrode of the second PMOS tube and the source electrode of the third PMOS tube;
the drain electrode of the second PMOS tube is connected with the interface end through the second resistor;
the drain electrode of the third PMOS tube is connected with the interface end through the third resistor;
the grid electrode of the first PMOS tube is connected with the overvoltage protection circuit; the grid electrodes of the second PMOS tube and the third PMOS tube are connected with the DI pin;
the overvoltage protection circuit is used for detecting voltage values of the pin A and the pin B, judging whether the voltage values are within a preset range, and outputting a low level to a grid electrode of the first PMOS tube when the voltage values are judged to be within the preset range;
the driving circuit further comprises a fourth PMOS tube;
the source electrode of the fourth PMOS tube is connected with the drain electrode of the first PMOS tube, the drain electrode of the fourth PMOS tube is connected with the interface end through the fourth resistor, and the grid electrode of the fourth PMOS tube is connected with the overvoltage protection circuit;
and the overvoltage protection circuit is also used for outputting a low level to the grid electrode of the fourth PMOS tube when the voltage value is judged to be within a preset range.
2. The driving circuit of the RS485 chip of claim 1, wherein the NMOS transistor path comprises: the first NMOS tube, the second NMOS tube, the third NMOS tube, the fifth resistor, the sixth resistor, the seventh resistor and the eighth resistor;
the source electrode of the first NMOS tube is connected with one end of the fifth resistor and grounded, and the drain electrode of the first NMOS tube is respectively connected with the other end of the fifth resistor, the source electrode of the second NMOS tube and the source electrode of the third NMOS tube;
the drain electrode of the second NMOS tube is connected with the interface end through the sixth resistor;
the drain electrode of the third NMOS tube is connected with the interface end through the seventh resistor;
one end of the eighth resistor is connected with the drain electrode of the first NMOS tube, and the other end of the eighth resistor is connected with the interface end;
the grid electrode of the first NMOS tube is connected with the overvoltage protection circuit; the grid electrodes of the second NMOS tube and the third NMOS tube are connected with the DI pin;
the overvoltage protection circuit is further used for outputting a high level to the grid electrode of the first NMOS tube when the voltage value is judged to be within a preset range.
3. The driving circuit of the RS485 chip of claim 2, wherein the driving circuit further comprises a fourth NMOS transistor;
the source electrode of the fourth NMOS tube is connected with the drain electrode of the first NMOS tube, the drain electrode of the fourth NMOS tube is connected with the interface end through the eighth resistor, and the grid electrode of the fourth NMOS tube is connected with the overvoltage protection circuit;
and the overvoltage protection circuit is also used for outputting a high level to the grid electrode of the fourth NMOS tube when the voltage value is judged to be within a preset range.
4. The driving circuit of the RS485 chip of claim 2, wherein the driving circuit further comprises: a polarity determination path;
when the interface end is connected with the pin A, the output end of the polarity judgment path is connected with the grid electrode of the third PMOS tube and the grid electrode of the third NMOS tube;
when the interface end is connected with the pin B, the output end of the polarity judging path is connected with the grid electrode of the third PMOS tube and the grid electrode of the third NMOS tube through a phase inverter;
the polarity judgment circuit is used for detecting whether the pin A is connected with a positive connection wire of the RS485 bus or not, whether the pin B is connected with a negative connection wire of the RS485 bus or not, and outputs a low level when the pin A is judged to be connected with the negative connection wire of the RS485 bus, and outputs a high level when the pin B is judged to be not connected with the negative connection wire of the RS485 bus.
5. The driving circuit of the RS485 chip of claim 1, wherein the first PMOS transistor, the second PMOS transistor, the third PMOS transistor and the fourth PMOS transistor each comprise a parasitic diode;
the anode of the parasitic diode of the first PMOS tube is connected with the source electrode of the first PMOS tube, and the cathode of the parasitic diode of the first PMOS tube is connected with the drain electrode of the first PMOS tube;
the anode of the parasitic diode of the second PMOS tube is connected with the drain electrode of the second PMOS tube, and the cathode of the parasitic diode of the second PMOS tube is connected with the source electrode of the second PMOS tube;
the anode of the parasitic diode of the third PMOS tube is connected with the drain electrode of the third PMOS tube, and the cathode of the parasitic diode of the third PMOS tube is connected with the source electrode of the third PMOS tube;
and the anode of the parasitic diode of the fourth PMOS tube is connected with the drain electrode of the fourth PMOS tube, and the cathode of the parasitic diode of the fourth PMOS tube is connected with the source electrode of the fourth PMOS tube.
6. The driving circuit of the RS485 chip of claim 3, wherein the first NMOS transistor, the second NMOS transistor, the third NMOS transistor and the fourth NMOS transistor each comprise a parasitic diode;
the anode of the parasitic diode of the first NMOS tube is connected with the drain electrode of the first NMOS tube, and the cathode of the parasitic diode of the first NMOS tube is connected with the source electrode of the first NMOS tube;
the anode of the parasitic diode of the second NMOS tube is connected with the source electrode of the second NMOS tube, and the cathode of the parasitic diode of the second NMOS tube is connected with the drain electrode of the second NMOS tube;
the anode of the parasitic diode of the third NMOS tube is connected with the source electrode of the third NMOS tube, and the cathode of the parasitic diode of the third NMOS tube is connected with the drain electrode of the third NMOS tube;
and the anode of the parasitic diode of the fourth NMOS tube is connected with the source electrode of the fourth NMOS tube, and the cathode of the parasitic diode of the fourth NMOS tube is connected with the drain electrode of the fourth NMOS tube.
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