CN109687863A - The driving circuit of RS485 chip - Google Patents
The driving circuit of RS485 chip Download PDFInfo
- Publication number
- CN109687863A CN109687863A CN201811624935.1A CN201811624935A CN109687863A CN 109687863 A CN109687863 A CN 109687863A CN 201811624935 A CN201811624935 A CN 201811624935A CN 109687863 A CN109687863 A CN 109687863A
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- tube
- connect
- nmos tube
- pmos tube
- pmos
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/0175—Coupling arrangements; Interface arrangements
- H03K19/0185—Coupling arrangements; Interface arrangements using field effect transistors only
- H03K19/018507—Interface arrangements
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/0008—Arrangements for reducing power consumption
- H03K19/0013—Arrangements for reducing power consumption in field effect transistor circuits
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/003—Modifications for increasing the reliability for protection
- H03K19/00315—Modifications for increasing the reliability for protection in field-effect transistor circuits
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- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Computing Systems (AREA)
- General Engineering & Computer Science (AREA)
- Mathematical Physics (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
The invention discloses a kind of driving circuits of RS485 chip.The driving circuit includes: interface end, PMOS tube access and NMOS tube access；One end of the PMOS tube access connects to power supply, and the other end of the PMOS tube access is connect with one end of the interface end and the NMOS tube access, the other end ground connection of the NMOS tube access；The interface end is used to connect A pin or the connection of B pin of RS485 chip.The present invention realizes the driving circuit of RS485 chip by PMOS tube access and NMOS tube access, reflection caused by EMI (electromagnetic interference) and inappropriate cable termination can be reduced, the reliability of improve data transfer, realize rate high speed without number of bit errors according to transmission.And it can satisfy the RS485 remote data transmission application standard of state's network mark standard.
Description
Technical field
The present invention relates to electronic technology field, in particular to a kind of driving circuit of RS485 chip.
Background technique
RS-485 is a kind of at low cost and reliable communication specification, can be used for the application fields such as the networking of electric meter system.
RS-485 communication interface is transmitted using differential level mode, is worked for half-duplex.Any moment, RS-485 transceiver are merely able to work
Make in one of " reception " or " transmission " both of which, therefore, it is necessary to transmit/receive to RS-485 interface circuit the commutation control of logic
System.
In the prior art, commutation control is generally realized using software program or commutation control is realized using hardware circuit.But
Be, using software program realize commutation control, the I/O pin resource of CPU can be occupied, not can guarantee good anti-interference, and
It can be because causing loss of data there are certain delay；Commutation control is realized using hardware circuit, is at present mostly based on anti-
Phase device, and combine build-out resistor, but its one side power consumption is big, another aspect poor reliability, it is difficult to ensure high speed without error code
Data transmission.
Summary of the invention
The technical problem to be solved by the present invention is in order to overcome the driving circuit of RS-485 interface chip in the prior art
The poor defect of reliability provides a kind of driving circuit of RS485 chip.
The present invention is to solve above-mentioned technical problem by following technical proposals:
A kind of driving circuit of RS485 chip, the RS485 chip include A pin and B pin, the driving circuit packet
It includes: interface end, PMOS tube access and NMOS tube access；
One end of the PMOS tube access connects to power supply, the other end of the PMOS tube access and the interface end and institute
State one end connection of NMOS tube access, the other end ground connection of the NMOS tube access；
The interface end is for connecting the A pin or B pin connection.
Preferably, the RS485 chip further include: DI pin (data-out pin for sending driver) and overvoltage protection
Circuit；
The PMOS tube access includes: the first PMOS tube, the second PMOS tube, third PMOS tube, first resistor, the second electricity
Resistance, 3rd resistor and the 4th resistance；
The source electrode of first PMOS tube is connect with one end of the first resistor and the power supply respectively, and described first
PMOS tube drain electrode respectively with the other end of the first resistor, the source electrode of second PMOS tube and the third PMOS tube
Source electrode connection；
The drain electrode of second PMOS tube is connect by the second resistance with the interface end；
The drain electrode of the third PMOS tube is connect by the 3rd resistor with the interface end；
One end of 4th resistance is connect with the drain electrode of first PMOS tube, the other end of the 4th resistance and institute
State interface end connection；
The grid of first PMOS tube is connect with the overvoltage crowbar；Second PMOS tube and the third
The grid of PMOS tube is connect with the DI pin；
The overvoltage crowbar is used to detect the voltage value of the A pin and B pin, and whether judges the voltage value
Within a preset range, and when being judged as YES, the grid of output low level to first PMOS tube.
Preferably, the driving circuit further includes the 4th PMOS tube；
The source electrode of 4th PMOS tube is connect with the drain electrode of first PMOS tube, and the drain electrode of the 4th PMOS tube is logical
It crosses the 4th resistance to connect with the interface end, the grid of the 4th PMOS tube is connect with the overvoltage crowbar；
The overvoltage crowbar is also used to when being judged as YES, the grid of output low level to the 4th PMOS tube.
Preferably, the NMOS tube access include: the first NMOS tube, the second NMOS tube, third NMOS tube, the 5th resistance,
6th resistance, the 7th resistance and the 8th resistance；
One end connect and ground of the source electrode of first NMOS tube and the 5th resistance, the leakage of first NMOS tube
Pole is connect with the source electrode of the other end of the 5th resistance, the source electrode of second NMOS tube and the third NMOS tube respectively；
The drain electrode of second NMOS tube is connect by the 6th resistance with the interface end；
The drain electrode of the third NMOS tube is connect by the 7th resistance with the interface end；
One end of 8th resistance is connect with the drain electrode of first NMOS tube, the other end of the 8th resistance and institute
State interface end connection；
The grid of first NMOS tube is connect with the overvoltage crowbar；Second NMOS tube and the third
The grid of NMOS tube is connect with the DI pin；
The overvoltage crowbar is also used to when being judged as YES, the grid of output high level to first NMOS tube.
Preferably, the driving circuit further includes the 4th NMOS tube；
The source electrode of 4th NMOS tube is connect with the drain electrode of first NMOS tube, and the drain electrode of the 4th NMOS tube is logical
It crosses the 8th resistance to connect with the interface end, the grid of the 4th NMOS tube is connect with the overvoltage crowbar；
The overvoltage crowbar is also used to when being judged as YES, the grid of output high level to the 4th NMOS tube.
Preferably, the driving circuit further include: polarity judges access；
When the interface end is connect with the A pin, the polarity judges the output end and the 3rd PMOS of access
The grid of pipe is connected with the grid of third NMOS tube；
When the interface end is connect with the B pin, the polarity judge the output end of access by a phase inverter with
The grid of the third PMOS tube is connected with the grid of the third NMOS tube；
The polarity judges access for detecting whether the A pin connect with the positive wiring of RS485 bus, and the B draws
Whether foot connect with the negative wiring of RS485 bus, and when being judged as YES, and exports low level, when being judged as NO, exports high electricity
It is flat.
Preferably, first PMOS tube, second PMOS tube, the third PMOS tube and the 4th PMOS tube are equal
Including a parasitic diode；
The anode of the parasitic diode of first PMOS tube is connect with the source electrode of first PMOS tube, cathode with it is described
The drain electrode of first PMOS tube connects；
The anode of the parasitic diode of second PMOS tube is connect with the drain electrode of second PMOS tube, cathode and second
The source electrode of PMOS tube connects；
The anode of the parasitic diode of the third PMOS tube is connect with the drain electrode of the third PMOS tube, cathode and third
The source electrode of PMOS tube connects；
The anode of the parasitic tetrode of 4th PMOS tube is connect with the drain electrode of the 4th PMOS tube, cathode with it is described
The source electrode of 4th PMOS tube connects.
Preferably, first NMOS tube, second NMOS tube, the third NMOS tube and the 4th NMOS tube are equal
Including a parasitic diode；
The anode of the parasitic diode of first NMOS tube is connect with the drain electrode of first NMOS tube, cathode with it is described
The source electrode of first NMOS tube connects；
The anode of the parasitic diode of second NMOS tube is connect with the source electrode of second NMOS tube, cathode and second
The drain electrode of NMOS tube connects；
The anode of the parasitic diode of the third NMOS tube is connect with the source electrode of the third NMOS tube, cathode and third
The drain electrode of NMOS tube connects；
The anode of the parasitic tetrode of 4th NMOS tube is connect with the source electrode of the 4th NMOS tube, cathode with it is described
The drain electrode of 4th NMOS tube connects.
The positive effect of the present invention is that: the present invention realizes RS485 core by PMOS tube access and NMOS tube access
The driving circuit of piece can reduce reflection caused by EMI (electromagnetic interference) and inappropriate cable termination, improve data transfer
Reliability, realize rate high speed without number of bit errors according to transmission.And it can satisfy the RS485 remote data transmission application of state's network mark standard
Standard.
Detailed description of the invention
Fig. 1 is the circuit diagram of the driving circuit of the RS485 chip of the embodiment of the present invention 1.
Fig. 2 is the circuit diagram of the driving circuit of the RS485 chip of the embodiment of the present invention 2.
Specific embodiment
The present invention is further illustrated below by the mode of embodiment, but does not therefore limit the present invention to the reality
It applies among a range.
Embodiment 1
The present embodiment provides a kind of driving circuit of RS485 chip, RS485 chip include overvoltage crowbar, A pin and
B pin, A pin and B pin are all connected with driving circuit all the way.In order to make it easy to understand, in the present embodiment, by what is connect with A pin
Driving circuit is known as the first driving circuit, and the circuit connecting with B pin is known as the second driving circuit.
In the present embodiment, as shown in Figure 1, driving circuit includes: interface end 1, PMOS tube access 2 and NMOS tube access 3.
One end of PMOS tube access 2 is connect with power vd D, the other end of PMOS tube access and one end of interface end 1 and NMOS tube access 3
Connection, 3 other end of NMOS tube access ground connection.The A pin or B pin of RS485 chip are connect by interface end with driving circuit.
Specifically, PMOS tube access includes: the first PMOS tube M1, the second PMOS tube M2, third PMOS tube M3, first resistor
R1, second resistance R2,3rd resistor R3 and the 4th resistance R4；The source electrode of first PMOS tube M1 one end with first resistor R1 respectively
Connected with power vd D, the first PMOS tube M1 drain electrode respectively with the source electrode of the second PMOS tube M2, third PMOS tube M3 source electrode and
The other end of first resistor R1 connects；The drain electrode of 2nd PMOS M2 is connect by second resistance R2 with interface end 1；3rd PMOS
The drain electrode of pipe M3 is connect by 3rd resistor R3 with interface end 1；The drain electrode of one end of 4th resistance R4 and the first PMOS tube M1 connect
It connects, the other end of the 4th resistance R4 is connect with interface end 1.
NMOS tube access includes: the first NMOS tube M5, the second NMOS tube M6, third NMOS tube M7, the 5th resistance R5, the 6th
Resistance R6, the 7th resistance R7 and the 8th resistance R8；The source electrode of first NMOS tube M5 and one end connect and ground of the 5th resistance R5,
First NMOS tube M5 drain electrode is another with the source electrode of the second NMOS tube M6, the source electrode of third NMOS tube M7 and the 5th resistance R5 respectively
End connection；The drain electrode of second NMOS tube M6 is connect by the 6th resistance R6 with interface end 1；The drain electrode of third NMOS tube M7 passes through the
Seven resistance R7 are connect with interface end 1；One end of 8th resistance R8 is connect with the drain electrode of the first NMOS tube M5, and the 8th resistance R8's is another
One end is connect with interface end 1.
Second PMOS tube M2, third PMOS tube M3, the second NMOS tube M6 and third NMOS tube M7 grid with RS485 core
The DI pin of piece connects.The grid of the grid of first PMOS tube M1 and the first NMOS tube M5 and protection circuit connection.
Overvoltage crowbar is used to detect the voltage value of the A/B pin of RS485 chip, when the voltage of A/B pin is in 0~5V
In range, overvoltage crowbar generates normal signal, makes the grid G P_T low level of the first PMOS tube M1, the first NMOS tube M5
Grid G N_L node be high level, then the first PMOS tube M1, the first NMOS tube M5 are tended to remain on, respectively with the first PMOS
Pipe M1, NMOS tube M5 parallel connection first resistor R1 and the 5th resistance R5, it is ensured that centainly have logical path.
The data of DI pin be transmitted to the grid G P_M of the second PMOS tube of output stage, third PMOS tube grid G P_S,
The grid G N_M of second NMOS tube and tetra- grids of grid G N_S of third NMOS tube control the 2nd PMOS of power output tube respectively
Pipe M2, third PMOS tube M3, the second NMOS tube M6, the second NMOS tube M7, so that the logic of A/B leg signal be driven to overturn.
In the present embodiment, driving circuit further include: polarity judges access.The polarity judges that the output end of access and first drives
The grid of the third PMOS tube M3 of dynamic circuit is connected with the grid of third NMOS tube M7, which judges that the output end of access is also logical
A phase inverter is crossed to connect with the grid of the grid of the third PMOS tube M3 of the second driving circuit and third NMOS tube M7.
Polarity judges whether polarity of the access for detecting RS485 chip is consistent with the polarity of RS485 bus, namely detection
Whether the A pin of RS485 chip connect with the positive wiring of RS485 bus, and whether B pin connect with the negative wiring of RS485 bus,
And when the two polarity is consistent, polarity judges that access exports low level, at this time the 3rd PMOG pipe M3 conducting of the first driving circuit,
3rd NMOG pipe M7 of the second driving circuit is connected, i.e., the pull-up channel of A pin is opened, and the drop-down channel of B pin is opened；When two
When person's polarity is inconsistent, polarity judges that access exports high level, at this time the 3rd NMOG pipe M7 conducting of the first driving circuit, second
3rd PMOG pipe M3 of driving circuit is connected, i.e., the pull-up channel of B pin is opened, and the drop-down channel of A pin is opened.To realize
When auto polarity judges, and the pull-up and drop-down access added in the chip interior of A/B pin.
In the present embodiment, referring to Fig. 1, in PMOS access, each PMOS tube includes a parasitic diode, the first PMOS
The anode of the parasitic diode of pipe is connect with the source electrode of the first PMOS tube, and cathode is connect with the drain electrode of the first PMOS tube；Second
The anode of the parasitic diode of PMOS tube is connect with the drain electrode of the second PMOS tube, and cathode is connect with the source electrode of the second PMOS tube；The
The anode of the parasitic diode of three PMOS tube is connect with the drain electrode of third PMOS tube, and cathode is connect with the source electrode of third PMOS tube.
In PMOS tube access, the parasitic diode of the first PMOS tube and the second PMOS tube, third PMOS tube is all connected into back-to-back form,
To prevent in PMOS tube off state, the high pressure of A/B pin is transmitted to the grid of the first PMOS tube, namely electric current is avoided to fall
It fills.Meanwhile A/B pin being made to be able to bear the operating voltage of very wide generating positive and negative voltage range in the off case.
Equally, in NMOS tube access, the parasitic diode of the first NMOS tube and the second NMOS tube, third NMOS tube is all connected into
Back-to-back form, to prevent in NMOS tube off state, the high pressure of A/B pin is transmitted to the grid of the first NMOS tube, keeps away
Exempt from electric current reverse irrigation.
The driving circuit of the present embodiment can reduce reflection caused by EMI (electromagnetic interference) and inappropriate cable termination,
The reliability of improve data transfer, realize rate high speed without number of bit errors according to transmission.The RS485 that can satisfy state's network mark standard is long-range
Data transmission applications standard.
Embodiment 2
On the basis of embodiment 1, as shown in Fig. 2, in the present embodiment, PMOS tube access further includes the 4th PMOS tube M4；
The source electrode of 4th PMOS tube M4 is connect with the drain electrode of the first PMOS tube M1, the drain electrode of the 4th PMOS tube M4 by the 4th resistance R4 with
Interface end 1 connects.NMOS tube access further includes the 4th NMOS tube M8；The leakage of the source electrode of 4th NMOS tube M8 and the first NMOS tube M5
The drain electrode of pole connection, the 4th NMOS tube M8 is connect by the 8th resistance R8 with interface end 1.The grid M4 and the 4th of 4th PMOS tube
NMOS tube M8 is connect with overvoltage crowbar.When the voltage of A/B pin is within the scope of 0~5V, overvoltage crowbar output is low
Grid M4 of the level to the 4th PMOS tube, output high level to the 4th NMOS tube M8.
In the present embodiment, each PMOS tube is equipped with one first enabled pipe；Each NMOS tube, which is equipped with one second, to be made
It can pipe.Driving circuit is when idle, it is desirable that output (namely A/B pin keeps high-impedance state) enables the effect of pipe
It is to be held off NMOS tube M7/M8/M6 and PMOS tube M3/M4/M2 when needing driving circuit to turn off.
The driving circuit of the present embodiment can provide the overcurrent protection of two kinds of mechanism, below to the protection philosophy of two kinds of mechanism into
Row explanation:
(1) the grid G P B of the 4th PMOS tube M4 can be set to high level, the 4th NMOS tube M4 by the over-current signal of A/B pin
Grid G N_B be set to low level, thus shutdown the 4th PMOG pipe M4 and the 4th NMOS tube M8, only leave the second PMOS tube M2 and
Second pipe of NMOS tube M6 two overturning, to play the role of current limliting.Wherein, with the second PMOS tube M2 and the second NMOS tube M6
The concatenated big resistance (second resistance R2 and the 6th resistance R6) of conducting determines the size of cut-off current respectively.
(2) when the voltage of A/B pin is more than 5V, the grid G P_T of the first PMOS tube M1 is set to high level, and PD_SD
Drag down that (PD_SD signal is generated by overvoltage crowbar, when overvoltage crowbar detects that the voltage of A/B pin is more than 5V, is produced
Raw low level control logic), so that PMOS tube M1 is turned off, the first enabled pipe is all turned on by the PMOS tube that PD_SD is controlled, in
Between the VGS=0 of two array of pipes (including PMOS tube M2/M3/M4 and NMOS tube M6/M7/M8) be held off.
Equally, when the voltage of A/B pin is lower than 0V, the grid G N_L of the first NMOS tube is set to low level, and ND_SD
It draws high, so that the first NMOS tube M5 is turned off, the second enabled pipe is all turned on by the NMOS tube that ND_SD is controlled, intermediate two combs
The VGS=0 of son is held off.
In the present embodiment, driving circuit realizes the super-high-current protection and the excessive protection of power consumption of two kinds of mechanism.When normal
When driving bus, when causing chip current excessive extremely due to bus, the current foldback circuit of chip interior works, to guarantee
Driving current does not exceed the setting value under certain condition.
Although specific embodiments of the present invention have been described above, it will be appreciated by those of skill in the art that this is only
For example, protection scope of the present invention is to be defined by the appended claims.Those skilled in the art without departing substantially from
Under the premise of the principle and substance of the present invention, many changes and modifications may be made, but these change and
Modification each falls within protection scope of the present invention.
Claims (8)
1. a kind of driving circuit of RS485 chip, the RS485 chip include A pin and B pin, which is characterized in that the drive
Dynamic circuit includes: interface end, PMOS tube access and NMOS tube access；
One end of the PMOS tube access connects to power supply, the other end of the PMOS tube access and the interface end and described
One end of NMOS tube access connects, the other end ground connection of the NMOS tube access；
The interface end is for connecting the A pin or B pin connection.
2. the driving circuit of RS485 chip as described in claim 1, which is characterized in that the RS485 chip further include: DI
Pin and overvoltage crowbar；
The PMOS tube access includes: the first PMOS tube, the second PMOS tube, third PMOS tube, first resistor, second resistance,
Three resistance and the 4th resistance；
The source electrode of first PMOS tube is connect with one end of the first resistor and the power supply respectively, first PMOS tube
Drain electrode respectively with the source electrode of the other end of the first resistor, the source electrode of second PMOS tube and the third PMOS tube connect
It connects；
The drain electrode of second PMOS tube is connect by the second resistance with the interface end；
The drain electrode of the third PMOS tube is connect by the 3rd resistor with the interface end；
One end of 4th resistance is connect with the drain electrode of first PMOS tube, and the other end of the 4th resistance connects with described
The connection of mouth end；
The grid of first PMOS tube is connect with the overvoltage crowbar；Second PMOS tube and the third PMOS tube
Grid connect with the DI pin；
Whether the overvoltage crowbar is used to detect the voltage value of the A pin and B pin, and judge the voltage value pre-
If in range, and when being judged as YES, the grid of output low level to first PMOS tube.
3. the driving circuit of RS485 chip as claimed in claim 2, which is characterized in that the driving circuit further includes the 4th
PMOS tube；
The source electrode of 4th PMOS tube is connect with the drain electrode of first PMOS tube, and the drain electrode of the 4th PMOS tube passes through institute
It states the 4th resistance to connect with the interface end, the grid of the 4th PMOS tube is connect with the overvoltage crowbar；
The overvoltage crowbar is also used to when being judged as YES, the grid of output low level to the 4th PMOS tube.
4. the driving circuit of RS485 chip as claimed in claim 2, which is characterized in that the NMOS tube access includes: first
NMOS tube, the second NMOS tube, third NMOS tube, the 5th resistance, the 6th resistance, the 7th resistance and the 8th resistance；
One end connect and ground of the source electrode of first NMOS tube and the 5th resistance, the drain electrode point of first NMOS tube
It is not connect with the source electrode of the other end of the 5th resistance, the source electrode of second NMOS tube and the third NMOS tube；
The drain electrode of second NMOS tube is connect by the 6th resistance with the interface end；
The drain electrode of the third NMOS tube is connect by the 7th resistance with the interface end；
One end of 8th resistance is connect with the drain electrode of first NMOS tube, and the other end of the 8th resistance connects with described
The connection of mouth end；
The grid of first NMOS tube is connect with the overvoltage crowbar；Second NMOS tube and the third NMOS tube
Grid connect with the DI pin；
The overvoltage crowbar is also used to when being judged as YES, the grid of output high level to first NMOS tube.
5. the driving circuit of RS485 chip as claimed in claim 4, which is characterized in that the driving circuit further includes the 4th
NMOS tube；
The source electrode of 4th NMOS tube is connect with the drain electrode of first NMOS tube, and the drain electrode of the 4th NMOS tube passes through institute
It states the 8th resistance to connect with the interface end, the grid of the 4th NMOS tube is connect with the overvoltage crowbar；
The overvoltage crowbar is also used to when being judged as YES, the grid of output high level to the 4th NMOS tube.
6. the driving circuit of RS485 chip as claimed in claim 4, which is characterized in that the driving circuit further include: polarity
Judge access；
When the interface end is connect with the A pin, the polarity judge access output end and the third PMOS tube
Grid is connected with the grid of third NMOS tube；
When the interface end is connect with the B pin, the polarity judge the output end of access by a phase inverter with it is described
The grid of third PMOS tube is connected with the grid of the third NMOS tube；
The polarity judges access for detecting whether the A pin connect with the positive wiring of RS485 bus, and the B pin is
The no negative wiring with RS485 bus is connect, and when being judged as YES, and exports low level, when being judged as NO, exports high level.
7. the driving circuit of RS485 chip as claimed in claim 3, which is characterized in that first PMOS tube, described second
PMOS tube, the third PMOS tube and the 4th PMOS tube include a parasitic diode；
The anode of the parasitic diode of first PMOS tube is connect with the source electrode of first PMOS tube, cathode and described first
The drain electrode of PMOS tube connects；
The anode of the parasitic diode of second PMOS tube is connect with the drain electrode of second PMOS tube, cathode and the 2nd PMOS
The source electrode of pipe connects；
The anode of the parasitic diode of the third PMOS tube is connect with the drain electrode of the third PMOS tube, cathode and the 3rd PMOS
The source electrode of pipe connects；
The anode of the parasitic tetrode of 4th PMOS tube is connect with the drain electrode of the 4th PMOS tube, cathode and the described 4th
The source electrode of PMOS tube connects.
8. the driving circuit of RS485 chip as claimed in claim 5, which is characterized in that first NMOS tube, described second
NMOS tube, the third NMOS tube and the 4th NMOS tube include a parasitic diode；
The anode of the parasitic diode of first NMOS tube is connect with the drain electrode of first NMOS tube, cathode and described first
The source electrode of NMOS tube connects；
The anode of the parasitic diode of second NMOS tube is connect with the source electrode of second NMOS tube, cathode and the 2nd NMOS
The drain electrode of pipe connects；
The anode of the parasitic diode of the third NMOS tube is connect with the source electrode of the third NMOS tube, cathode and the 3rd NMOS
The drain electrode of pipe connects；
The anode of the parasitic tetrode of 4th NMOS tube is connect with the source electrode of the 4th NMOS tube, cathode and the described 4th
The drain electrode of NMOS tube connects.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811624935.1A CN109687863B (en) | 2018-12-28 | 2018-12-28 | Drive circuit of RS485 chip |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811624935.1A CN109687863B (en) | 2018-12-28 | 2018-12-28 | Drive circuit of RS485 chip |
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| CN109687863A true CN109687863A (en) | 2019-04-26 |
| CN109687863B CN109687863B (en) | 2023-02-28 |
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| CN201811624935.1A Active CN109687863B (en) | 2018-12-28 | 2018-12-28 | Drive circuit of RS485 chip |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111786431A (en) * | 2020-06-29 | 2020-10-16 | 南京微盟电子有限公司 | Circuit for preventing battery from flowing backward current by high-input voltage-resistant charging management chip |
| CN113114195A (en) * | 2021-04-23 | 2021-07-13 | 广东省大湾区集成电路与系统应用研究院 | Power-off closing circuit, power-off closing chip and switch chip |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102938720A (en) * | 2012-11-21 | 2013-02-20 | 武汉昊昱微电子股份有限公司 | Non-polarity communication circuit based on ammeter application |
| CN107947784A (en) * | 2017-10-20 | 2018-04-20 | 上海华力微电子有限公司 | A kind of high-performance output driving circuit |
| CN108768381A (en) * | 2018-08-27 | 2018-11-06 | 珠海市中科蓝讯科技有限公司 | GPIO circuits and chip |
-
2018
- 2018-12-28 CN CN201811624935.1A patent/CN109687863B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102938720A (en) * | 2012-11-21 | 2013-02-20 | 武汉昊昱微电子股份有限公司 | Non-polarity communication circuit based on ammeter application |
| CN107947784A (en) * | 2017-10-20 | 2018-04-20 | 上海华力微电子有限公司 | A kind of high-performance output driving circuit |
| CN108768381A (en) * | 2018-08-27 | 2018-11-06 | 珠海市中科蓝讯科技有限公司 | GPIO circuits and chip |
Non-Patent Citations (1)
| Title |
|---|
| 辛萌萌: "RS-485通信接口芯片的IC设计与实现", 《中国优秀硕士学位论文全文数据库信息科技辑》 * |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111786431A (en) * | 2020-06-29 | 2020-10-16 | 南京微盟电子有限公司 | Circuit for preventing battery from flowing backward current by high-input voltage-resistant charging management chip |
| CN113114195A (en) * | 2021-04-23 | 2021-07-13 | 广东省大湾区集成电路与系统应用研究院 | Power-off closing circuit, power-off closing chip and switch chip |
| CN113114195B (en) * | 2021-04-23 | 2024-06-04 | 广东省大湾区集成电路与系统应用研究院 | Power-off closing circuit, power-off closing chip and switch chip |
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|---|---|
| CN109687863B (en) | 2023-02-28 |
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