CN104467799A - Input/output circuit device - Google Patents
Input/output circuit device Download PDFInfo
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- CN104467799A CN104467799A CN201310415468.2A CN201310415468A CN104467799A CN 104467799 A CN104467799 A CN 104467799A CN 201310415468 A CN201310415468 A CN 201310415468A CN 104467799 A CN104467799 A CN 104467799A
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Abstract
The invention discloses an input/output circuit device, which includes an output circuit, a biasing circuit and an input circuit, wherein the output circuit is connected to the input circuit by the biasing circuit; the input circuit is used for being connected to first input signals and input signals; the output circuit is used for receiving output signals and bias generating signal and electrically connected to an input/output port; the biasing circuit includes a series resistor dividing module, a capacitor sustaining voltage module and a control module; the series resistor dividing module is used for regulating the working voltages of a first input signal end and a second input signal end according to the voltage of the input/output port; the control module is used for controlling the working voltage of a bias generating signal end according to a voltage signal of the second input signal end; the capacitor sustaining voltage module is used for sustaining the working voltage of the bias generating signal end. According to the input/output circuit device, the phenomenon that an MOS transistor is damaged when the input/output port is provided with a voltage signal with swing of 5V in the case that a local power supply has no power is effectively avoided.
Description
Technical field
The present invention relates to integrated circuit, particularly relate to a kind of imput output circuit that can bear 5V voltage signal.
Background technology
Along with the fast development of electronics and information industry, the speed of transfer of data grows with each passing day, and the various interface protocols between chip and chip, between equipment and equipment emerge in an endless stream.Wherein many protocol requirements have the imput output circuit (or 5V voltage detecting circuit) of 5V signal work range, and active device---metal oxide semiconductor field effect tube (the metal-oxide-semiconductor filedeffect transistor of integrated circuit use usually, be called for short MOS transistor) any two ports between rated insulation voltage be 3.3V, directly be applied in the operational environment of 5V signal, the damage of device can be caused.Therefore, how to use the MOS transistor that rated insulation voltage is 3.3V to carry out the imput output circuit that the modelled signal amplitude of oscillation is 5V, and to ensure that when local power supply is invalid device is not damaged and just become a challenging problem.
Summary of the invention
Based on this, when to be necessary for local power supply without electricity, the voltage of input/output port 5V_IO is 5V, and in circuit, MOS transistor holds flimsy problem, provides a kind of imput output circuit device.
For realizing the object of the invention, a kind of imput output circuit device provided, is characterized in that, comprise input circuit, biasing circuit and output circuit:
Described input circuit is electrically connected with described biasing circuit, for connecting the first input signal and input signal;
Described biasing circuit is electrically connected with input/output port and described input circuit, and exports the first input signal and biased generation signal;
Described output circuit is electrically connected with input/output port and described biasing circuit, for receiving output signal and described biased generation signal.
Wherein in an embodiment, described biasing circuit comprises series resistance division module, electric capacity keeps voltage module and control module:
Described series resistance division module is electrically connected, for the operating voltage of the first input signal end and the second input signal end according to the voltage-regulation of input/output port with the second input signal end of described input/output port, the first input signal end of described input circuit, described control module and the 3rd input signal end respectively;
Described control module and described second input signal end, biasedly produces signal end and supply voltage is electrically connected, for the operating voltage of the described biased generation signal end of voltage signal control according to described second input signal end, described supply voltage is 3.3V;
Described electric capacity keeps voltage module to be series at biased generation signal end and the earth terminal of described control module, for keeping the operating voltage of described biased generation signal end;
Described 3rd input signal end is electrically connected with earth terminal.
Wherein in an embodiment, described biasing circuit also comprises mode selection module, and described mode selection module is series between described 3rd input signal end and earth terminal, and receives described biased generation signal and output mode selection signal.
Wherein in an embodiment, described mode selection module comprises the 3rd inverter and the 5th transistor, and the grid of described 5th transistor is connected with the output of described 3rd inverter;
Substrate, the source electrode of described 5th transistor are connected with earth terminal, and the drain electrode of described 5th transistor is electrically connected with described 3rd input signal end;
The operating voltage of described 3rd inverter is the voltage of described biased generation signal end.
Wherein in an embodiment, described control module comprises the first transistor and transistor seconds, and the grid of described the first transistor is connected with the source electrode of described transistor seconds and is coupled to described second input signal end;
The drain electrode of described the first transistor, the substrate of the first transistor, the substrate of transistor seconds are connected with the drain electrode of transistor seconds and are coupled to described biased generation signal end;
The source electrode of described the first transistor is connected with the grid of described transistor seconds and is coupled to described supply voltage.
Wherein in an embodiment, described electric capacity keeps voltage module to comprise capacitor, and described capacitor one end is connected with earth terminal, and the other end is coupled to the biased generation signal end of described control module.
Wherein in an embodiment, described output circuit comprises third transistor, the 4th transistor and the first inverter, and the substrate of the substrate of described third transistor, the source electrode of third transistor, the 4th transistor connects and is coupled to earth terminal;
The grid of described third transistor is connected with the output of described first inverter, and the drain electrode of described third transistor is connected with the source electrode of described 4th transistor;
The drain electrode of described 4th transistor is connected with described input/output port;
The grid voltage of described 4th transistor is described biased generation signal end voltage.
Wherein in an embodiment, described series resistance division module comprises the first resistance, the second resistance and the 3rd resistance, described second resistant series is between described first resistance and described 3rd resistance, the other end of described first resistance is connected with earth terminal, and the other end of described 3rd resistance is electrically connected with described input/output port;
The link of described first resistance and described second resistance is coupled to the second input signal end of described control module;
The link of described second resistance and described 3rd resistance is coupled to the first input signal end of described input circuit.
In another embodiment, described series resistance division module comprises the first resistance, the second resistance and the 3rd resistance, described second resistant series is between described first resistance and described 3rd resistance, the other end of described first resistance is connected with earth terminal, and the other end of described 3rd resistance is electrically connected with described input/output port;
The link of described first resistance and described second resistance is coupled to the first input signal end of described control module;
The link of described second resistance and described 3rd resistance is coupled to the second input signal end of described input circuit.
Wherein in an embodiment, described input circuit comprises the second inverter, and described second inverter input is coupled to described first input signal end, and described second inverter output is coupled with input signal;
The operating voltage of described second inverter is 3.3V or 1V;
Described second inverter comprises PMOS, the nmos pass transistor that rated insulation voltage is 3.3V.
In another embodiment, described input circuit comprises the second inverter, and described second inverter input is coupled to described first input signal end, and described second inverter output is coupled with input signal;
The operating voltage of described second inverter is 1V;
Described second inverter comprises PMOS, the nmos pass transistor that rated insulation voltage is 1V.
Wherein in an embodiment, described the first transistor and transistor seconds are enhancement mode PMOS;
Described third transistor, the 4th transistor and the 5th transistor are enhancement mode NMOS tube;
Described first inverter and the 3rd inverter comprise PMOS, the nmos pass transistor that rated insulation voltage is 3.3V.
Imput output circuit device provided by the invention comprises output circuit, biasing circuit and input circuit, and output circuit is connected with input circuit by biasing circuit; Input circuit is for connecting the first input signal and input signal; Output circuit produces signal for receiving output signal and being biased and is electrically connected with input/output port; Biasing circuit comprises series resistance division module, electric capacity keeps voltage module and control module; Series resistance division module is used for according to the voltage-regulation first input signal end of input/output port and the operating voltage of the second input signal end; Control module is used for controlling the biased operating voltage producing signal end according to the voltage signal of the second input signal end; Electric capacity keeps voltage module for keeping the operating voltage of described biased generation signal end.It effectively avoids local power supply without when the input/output port connection amplitude of oscillation is 5V voltage signal in electric situation, the impaired phenomenon of MOS transistor.
Accompanying drawing explanation
Fig. 1 is imput output circuit device one embodiment schematic diagram of the present invention;
Fig. 2 is the another embodiment schematic diagram of imput output circuit device of the present invention;
Fig. 3 is an imput output circuit device of the present invention embodiment schematic diagram again;
Fig. 4 is another embodiment schematic diagram of imput output circuit device of the present invention;
Fig. 5 is another embodiment schematic diagram of imput output circuit device of the present invention.
Embodiment
In order to make object of the present invention, the technical scheme of employing and advantage clearly understand, below in conjunction with drawings and the specific embodiments, imput output circuit device of the present invention is described in further detail.
See Fig. 1, a kind of imput output circuit device of the embodiment of the present invention, comprises input circuit, biasing circuit and output circuit.
Described input circuit is electrically connected with described biasing circuit, for connecting the first input signal and input signal;
Described biasing circuit is electrically connected with input/output port and described input circuit, and exports the first input signal and biased generation signal.
Described output circuit is electrically connected with input/output port and described biasing circuit, for receiving output signal and described biased generation signal.
Described biasing circuit comprises series resistance division module, electric capacity keeps voltage module and control module:
Described series resistance division module is electrically connected, for the operating voltage of the first input signal end and the second input signal end according to the voltage-regulation of input/output port with the second input signal end of described input/output port, the first input signal end of described input circuit, described control module and the 3rd input signal end respectively;
Described control module and described second input signal end, biasedly produces signal end and supply voltage is electrically connected, for the operating voltage of the described biased generation signal end of voltage signal control according to described second input signal end, described supply voltage is 3.3V;
Described electric capacity keeps voltage module to be series at biased generation signal end and the earth terminal of described control module, for keeping the operating voltage of described biased generation signal end;
Described 3rd input signal end is electrically connected with earth terminal.
Preferably, as a kind of embodiment, described biasing circuit also comprises mode selection module, and described mode selection module is series between described 3rd input signal end and earth terminal, and receives described biased generation signal and output mode selection signal.
See Fig. 2, as one embodiment of the present of invention, a kind of imput output circuit device, during for avoiding local power supply without electricity, it is 5V voltage signal that input/output port 5V_IO connects the amplitude of oscillation, the impaired phenomenon of MOS transistor, comprise output circuit, biasing circuit and input circuit, output circuit is connected with input circuit by biasing circuit; Input circuit connects the first input signal and input signal; Output circuit is connected with input/output port, for receiving output signal and biased generation signal;
Biasing circuit comprises series resistance division module, electric capacity keeps voltage module and control module;
Series resistance division module is electrically connected with the first input signal end IO1 of input/output port 5V_IO, input circuit, the second input signal end IO2 of control module and earth terminal respectively, for according to the voltage-regulation first input signal end IO1 of input/output port 5V_IO and the operating voltage of the second input signal end IO2;
Control module and the second input signal end IO2, biasedly produce signal end and supply voltage V
cCelectrical connection, for controlling the biased operating voltage V producing signal end according to the voltage signal of the second input signal end IO2
bulk;
Electric capacity keeps voltage module to be series at biased generation signal end and the earth terminal of control module, for keeping the biased operating voltage V producing signal end
bulk.
Series resistance division module comprises the first resistance R0, the second resistance R1 and the 3rd resistance R2, second resistance R1 is series between the first resistance R0 and the 3rd resistance R2, the other end of the first resistance R0 is connected with earth terminal, and the other end of the 3rd resistance R2 is electrically connected with input/output port 5V_IO; The link of the second resistance R1 and the 3rd resistance R2 is electrically connected with the first input signal end IO1; The link of the first resistance R0 and the second resistance R1 is coupled to the second input signal end IO2.
Electric capacity keeps voltage module to comprise capacitor C0, and capacitor C0 one end is connected with earth terminal, and the other end is coupled to biased generation signal end.
Control module comprises the first transistor PMOS0 and transistor seconds PMOS1, and the grid of the first transistor PMOS0 is connected with the source electrode of transistor seconds PMOS1 and is coupled to the second input signal end IO2; The substrate of the drain electrode of the first transistor PMOS0, the substrate of the first transistor PMOS0, transistor seconds PMOS1 is connected with the drain electrode of transistor seconds PMOS1 and is coupled to and biased produces signal end; The source electrode of the first transistor PMOS0 is connected with the grid of transistor seconds PMOS1 and is coupled to supply voltage V
cC.
Preferably, the first transistor PMOS0 and transistor seconds PMOS1 is enhancement mode PMOS.
Output circuit comprises third transistor NMOS0, the 4th transistor NMOS1 and the first inverter, and the source electrode of the substrate of third transistor NMOS0, the source electrode of third transistor NMOS0, the 4th transistor NMOS1 connects and is coupled to earth terminal; The grid of third transistor NMOS0 is connected with the output of the first inverter, and the drain electrode of third transistor NMOS0 is connected with the source electrode of the 4th transistor NMOS1; The drain electrode of the 4th transistor NMOS1 is connected with input/output port 5V_IO; The grid voltage of the 4th transistor NMOS1 is the biased voltage V producing signal end
bulk.
Preferably, third transistor NMOS0 and the 4th transistor NMOS1 is enhancement mode NMOS tube;
Input circuit comprises the second inverter, and the second inverter input is coupled to the first input signal end IO1, and the second inverter output is coupled with input signal, and the operating voltage of the second inverter is 3.3V or 1V;
Preferably, the second inverter comprises PMOS, the nmos pass transistor that rated insulation voltage is 3.3V.
When in input circuit, the operating voltage of the second inverter is 3.3V, when described input/output port is connected to 5V power supply, two kinds of situations can be divided into:
(1) as 3.3V power supply V
cChave electricity, input/output port is connected to the power supply of 5V by a pull-up resistor, now by the ratio of design first resistance R0, the second resistance R1 and the 3rd resistance R2, can realize following relation:
Wherein V
iO1be the magnitude of voltage of the first input signal end IO1 when signal is high level, V
5V_IO (high)for the magnitude of voltage of input/output port 5V_IO when signal is high level.Like this by regulating (R0+R1) to realize the adjustment of the maximum voltage value of the first input signal input to input circuit with the ratio of R2, not damaged to ensure the MOS transistor in input circuit, and realize the input of logical signal;
By designing the ratio of the first resistance R0, the second resistance R1 and the 3rd resistance R2, following relation can also be realized:
Wherein V
iO2 (high)be the magnitude of voltage of the second input signal end IO2 when signal is high level, V
5V_IO (high)for the magnitude of voltage of input/output port 5V_IO when signal is high level.Like this by regulating R0 and the ratio of (R1+R2), V can be realized
iO2 (high)the threshold value of a first transistor PMOS0 lower than VCC or larger voltage.Like this when input/output port 5V_IO exists the signal swing of 5V, the grid of the first transistor PMOS0 is low level, because the first transistor PMOS0 is P channel MOS tube, so now the first transistor PMOS0 conducting, and biased generation signal end voltage V
bulkequal V
cC, thus in output circuit, the grid voltage of the 4th transistor NMOS1 is V
cC, again due to V
cCfor 3.3V supply voltage, therefore the 4th transistor NMOS1 normally works, can not be damaged, and then ensure that the normal work of metal-oxide-semiconductor in output circuit.
(2) as 3.3V power supply V
cCduring without electricity, input/output port 5V_IO is connected to the power supply of 5V by a pull-up resistor, now, the voltage at the first input signal end IO1 and the second input signal end IO2 place also can be essentially pulled up to higher level at short notice, thus transistor seconds PMOS1 source level is higher level, grid and supply voltage V
cCbe connected, V
cCwithout electricity, so transistor seconds PMOS1 grid is low level, again because transistor seconds PMOS1 is P channel MOS tube, thus transistor seconds PMOS1 conducting, thus make biased generation signal end voltage V
bulkalso high level is pulled to, now, biased generation signal end voltage V
bulk, the first input signal end IO1 and the second input signal end IO2 voltage all return to 3.3V power supply V
cCthere is situation during electricity, therefore, it is possible to ensure that imput output circuit CMOS transistor when input/output port 5V_IO is 5V is not damaged.
See Fig. 3, preferably, as another embodiment of the present invention, when may to be operated in the amplitude of oscillation be the situation of 3.3V signal or 5V signal to input/output port 5V_IO, biasing circuit also comprises mode selection module, mode selection module be series at that in series resistance division module, the first resistance is not connected with the second resistance between one end and earth terminal.Mode selection module comprises the 3rd inverter and the 5th transistor NMOS2, and the grid of the 5th transistor NMOS2 is connected with the output of the 3rd inverter; Substrate, the source electrode of the 5th transistor NMOS2 are connected with earth terminal, and one end that drain electrode and the first resistance R0 in series resistance division module of the 5th transistor NMOS2 are not connected with the second resistance R1 connects; The operating voltage of the 3rd inverter is the biased voltage V producing signal end
bulk.
Preferably, the 3rd inverter comprises PMOS, the nmos pass transistor that rated insulation voltage is 3.3V, and the 5th transistor NMOS2 is enhancement mode NMOS tube;
As embodiment, when input/output port 5V_IO is connected to 3.3V power supply by a pull-up resistor, by external system, the mode select signal in mode selection module is set to 3.3V, now the 5th transistor NMOS2 is in cut-off state, thus the second input signal end IO2 is all identical with the magnitude of voltage of input/output port 5V_IO with the voltage of the first input signal end IO1, and series resistance division module no longer includes dividing potential drop effect.Because the signal of input/output port 5V_IO swings between 0V to 3.3V, when the voltage of input/output port 5V_IO is 0V, the first transistor PMOS0 grid is low level, now the first transistor PMOS0 conducting, biased generation signal end voltage V
bulkequal V
cC, electric capacity keeps the electric capacity C0 in voltage module to keep V
bulknot declining, ensure that the normal work of the 4th transistor NMOS1 in output circuit thus, imput output circuit function can also be realized when not wasting quiescent dissipation.
As embodiment, when input/output port 5V_IO is connected to 5V power supply by a pull-up resistor, the mode select signal in mode selection module is set to 0V.Below analyze in two kinds of situation:
(1) at 3.3V power supply V
cChave electricity, input/output port is connected in the short time of the power supply of 5V by a pull-up resistor, and assumed initial state the 5th transistor NMOS2 is cut-off state.Second input signal end IO2 is all identical with the magnitude of voltage of input/output port 5V_IO with the voltage of the first input signal end IO1.The grid potential of transistor seconds PMOS1 is V
cC, source voltage is the second input signal IO2, therefore transistor seconds PMOS1 conducting.The biased signal that produces can rise to a higher current potential at short notice, and now the grid potential of the 5th transistor NMOS2 also can rise to a higher current potential, causes the 5th transistor NMOS2 conducting.Due to the 5th transistor NMOS2 conducting, the series resistance division module of the ratio of appropriate design first resistance R0, the second resistance R1 and the 3rd resistance R2 can cause the second input signal V
iO2 (high)compare V
cCthe threshold value of a low the first transistor PMOS0 or larger voltage.Because the first transistor PMOS0 is P channel MOS tube, so now the first transistor PMOS0 conducting, biased generation signal end voltage V
bulkdrop to V
cC, thus in output circuit, the grid voltage of the 4th transistor NMOS1 is V
cC, again due to V
cCfor 3.3V supply voltage, therefore the 4th transistor NMOS1 normally works, can not be damaged, and then ensure that the normal work of metal-oxide-semiconductor in output circuit.
(2) at 3.3V power supply V
cCwithout electricity, input/output port is connected in the short time of the power supply of 5V by a pull-up resistor, and assumed initial state the 5th transistor NMOS2 is cut-off state.Second input signal end IO2 is all identical with the magnitude of voltage of input/output port 5V_IO with the voltage of the first input signal end IO1.The grid potential of transistor seconds PMOS1 is 0, and source voltage is the second input signal IO2, therefore transistor seconds PMOS1 conducting.The biased signal that produces can rise to a higher current potential at short notice, and now the grid potential of the 5th transistor NMOS2 also can rise to a higher current potential, causes the 5th transistor NMOS2 conducting.Due to the 5th transistor NMOS2 conducting, the series resistance division module of the ratio of appropriate design first resistance R0, the second resistance R1 and the 3rd resistance R2 can cause the second input signal V
iO2 (high)compare V
cCthe threshold value of a low the first transistor PMOS0 or larger voltage.Because the first transistor PMOS0 is P channel MOS tube, so now the first transistor PMOS0 conducting, biased generation signal end voltage V
bulkdrop to the second input signal current potential V
iO2 (high), thus in output circuit, the grid voltage of the 4th transistor NMOS1 equals the second input signal current potential V
iO2 (high), therefore the 4th transistor NMOS1 normally works, can not be damaged.
See Fig. 4, as another embodiment of the present invention, in described input circuit, the operating voltage Vdd of the second inverter is approximately 1V, and the second inverter in input circuit is that the PMOS of 3.3V and nmos pass transistor are formed by rated insulation voltage.When the high level voltage scope of described input/output port 5V_IO is more than or equal to 1.5V and is less than or equal to 5V, by reasonably designing the ratio of the first resistance R0, the second resistance R1 and the 3rd resistance R2, it is made to meet
Due to 1.5V≤V
5V_IO (high)≤ 5V and
So
Operating voltage Vdd due to the second inverter is 1V, rated insulation voltage is that the conduction threshold of the nmos pass transistor of 3.3V is approximately 0.7V, in order to ensure that the second inverter normally works, by design, the input logic high level turn threshold setting the second inverter is about 0.8V, then V
iO1 (high)>=1V>V
th, high=0.8V, therefore when the high level voltage scope of input/output port 5V_IO is more than or equal to 1.5V and is less than or equal to 5V, the high level of the first input signal is greater than the input logic high level upset threshold of the second inverter, second inverter exports as logical zero, thus can normally work ensureing that in imput output circuit, MOS transistor is not impaired while.
See Fig. 5, as another embodiment of the present invention, as the operating voltage V of the second inverter in input circuit
ddduring for 1V, namely input signal needs to give supply voltage is V
ddsystem process time, the second inverter comprises the CMOS transistor can born and be approximately 1V voltage.V
ddfor rated voltage equals the power supply of about 1V, now V
cCfor rated voltage equals the power supply of 3.3V.
(1) V is worked as
cCtime effective, input/output port 5V_IO is connected to 5V power supply by pull-up resistor, by designing the ratio of the first resistance R0, the second resistance R1 and the 3rd resistance R2, can realize following relation:
Wherein, V
iO1 (high)be the magnitude of voltage of the first input signal end IO1 when signal is high level, V
5V_IO (high)for the magnitude of voltage of input/output port 5V_IO when signal is high level.Just can ensure that supply voltage is V by the dividing potential drop effect of series resistance division module like this
ddinput circuit in MOS transistor not damaged, and realize the input of logical signal.
By regulating the ratio of the first resistance R0, the second resistance R1 and the 3rd resistance R2, following relation can also be realized:
Wherein, V
iO2 (high)be the magnitude of voltage of the second input signal end IO2 when signal is high level, V
5V-IO (high)for the magnitude of voltage of input/output port 5V_IO when signal is high level.Like this by regulating the ratio of (R0+R1) and R2 to make V
iO2 (high)compare V
cCthe threshold value of a low the first transistor PMOS0 or larger voltage, like this when input/output port 5V_IO exists the signal swing of 5V, the first transistor PMOS0 conducting, V
bulkequal VCC, thus the grid voltage of the 4th transistor NMOS1 equals V
cC, and then ensure that the 4th transistor NMOS1 normally works, and then ensure that the metal-oxide-semiconductor in output circuit is not damaged.
(2) V is worked as
cCtime invalid, input/output port 5V_IO is connected to 5V power supply by pull-up resistor, and now, when input/output port 5V_IO is essentially pulled up to 5V, series resistance division module makes biased generation signal end voltage V
bulk, the first input signal end IO1 and the second input signal end IO2 voltage all return to VCC effective time, V
5V-IO (high)situation during=5V, thus ensure that in imput output circuit, MOS transistor can not be damaged.
The above embodiment only have expressed several execution mode of the present invention, and it describes comparatively concrete and detailed, but therefore can not be interpreted as the restriction to the scope of the claims of the present invention.It should be pointed out that for the person of ordinary skill of the art, without departing from the inventive concept of the premise, can also make some distortion and improvement, these all belong to protection scope of the present invention.Therefore, the protection range of patent of the present invention should be as the criterion with claims.
Claims (12)
1. an imput output circuit device, is characterized in that, comprises input circuit, biasing circuit and output circuit:
Described input circuit is electrically connected with described biasing circuit, for connecting the first input signal and input signal;
Described biasing circuit is electrically connected with input/output port and described input circuit, and exports the first input signal and biased generation signal;
Described output circuit is electrically connected with input/output port and described biasing circuit, for receiving output signal and described biased generation signal.
2. imput output circuit device according to claim 1, is characterized in that, described biasing circuit comprises series resistance division module, electric capacity keeps voltage module and control module:
Described series resistance division module is electrically connected, for the operating voltage of the first input signal end and the second input signal end according to the voltage-regulation of input/output port with the second input signal end of described input/output port, the first input signal end of described input circuit, described control module and the 3rd input signal end respectively;
Described control module and described second input signal end, biasedly produces signal end and supply voltage is electrically connected, for the operating voltage of the described biased generation signal end of voltage signal control according to described second input signal end, described supply voltage is 3.3V;
Described electric capacity keeps voltage module to be series at biased generation signal end and the earth terminal of described control module, for keeping the operating voltage of described biased generation signal end;
Described 3rd input signal end is electrically connected with earth terminal.
3. imput output circuit device according to claim 2, is characterized in that:
Described biasing circuit also comprises mode selection module, and described mode selection module is series between described 3rd input signal end and earth terminal, and receives described biased generation signal and output mode selection signal.
4. imput output circuit device according to claim 3, is characterized in that:
Described mode selection module comprises the 3rd inverter and the 5th transistor, and the grid of described 5th transistor is connected with the output of described 3rd inverter;
Substrate, the source electrode of described 5th transistor are connected with earth terminal, and the drain electrode of described 5th transistor is electrically connected with described 3rd input signal end;
The operating voltage of described 3rd inverter is the voltage of described biased generation signal end.
5. the imput output circuit device according to any one of claim 2 to 4, is characterized in that:
Described control module comprises the first transistor and transistor seconds, and the grid of described the first transistor is connected with the source electrode of described transistor seconds and is coupled to described second input signal end;
The drain electrode of described the first transistor, the substrate of the first transistor, the substrate of transistor seconds are connected with the drain electrode of transistor seconds and are coupled to described biased generation signal end;
The source electrode of described the first transistor is connected with the grid of described transistor seconds and is coupled to described supply voltage.
6. imput output circuit device according to claim 5, is characterized in that:
Described electric capacity keeps voltage module to comprise capacitor, and described capacitor one end is connected with earth terminal, and the other end is coupled to the biased generation signal end of described control module.
7. imput output circuit device according to claim 6, is characterized in that:
Described output circuit comprises third transistor, the 4th transistor and the first inverter, and the substrate of the substrate of described third transistor, the source electrode of third transistor, the 4th transistor connects and is coupled to earth terminal;
The grid of described third transistor is connected with the output of described first inverter, and the drain electrode of described third transistor is connected with the source electrode of described 4th transistor;
The drain electrode of described 4th transistor is connected with described input/output port;
The grid voltage of described 4th transistor is described biased generation signal end voltage.
8. imput output circuit device according to claim 7, is characterized in that:
Described series resistance division module comprises the first resistance, the second resistance and the 3rd resistance, described second resistant series is between described first resistance and described 3rd resistance, the other end of described first resistance is connected with earth terminal, and the other end of described 3rd resistance is electrically connected with described input/output port;
The link of described first resistance and described second resistance is coupled to the second input signal end of described control module;
The link of described second resistance and described 3rd resistance is coupled to the first input signal end of described input circuit.
9. imput output circuit device according to claim 7, is characterized in that:
Described series resistance division module comprises the first resistance, the second resistance and the 3rd resistance, described second resistant series is between described first resistance and described 3rd resistance, the other end of described first resistance is connected with earth terminal, and the other end of described 3rd resistance is electrically connected with described input/output port;
The link of described first resistance and described second resistance is coupled to the first input signal end of described control module;
The link of described second resistance and described 3rd resistance is coupled to the second input signal end of described input circuit.
10. imput output circuit device according to claim 8, is characterized in that:
Described input circuit comprises the second inverter, and described second inverter input is coupled to described first input signal end, and described second inverter output is coupled with input signal;
The operating voltage of described second inverter is 3.3V or 1V;
Described second inverter comprises PMOS, the nmos pass transistor that rated insulation voltage is 3.3V.
11. imput output circuit devices according to claim 9, is characterized in that:
Described input circuit comprises the second inverter, and described second inverter input is coupled to described first input signal end, and described second inverter output is coupled with input signal;
The operating voltage of described second inverter is 1V;
Described second inverter comprises PMOS, the nmos pass transistor that rated insulation voltage is 1V.
12. imput output circuit devices according to claim 10 or 11, is characterized in that:
Described the first transistor and transistor seconds are enhancement mode PMOS;
Described third transistor, the 4th transistor and the 5th transistor are enhancement mode NMOS tube;
Described first inverter and the 3rd inverter comprise PMOS, the nmos pass transistor that rated insulation voltage is 3.3V.
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| CN108322208A (en) * | 2017-01-17 | 2018-07-24 | 上海贝岭股份有限公司 | Signaling interface and its signal interface circuit for positive/negative voltage signal input |
| CN113468089A (en) * | 2021-09-03 | 2021-10-01 | 上海类比半导体技术有限公司 | Output driving circuit and GPIO circuit |
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| CN113468089A (en) * | 2021-09-03 | 2021-10-01 | 上海类比半导体技术有限公司 | Output driving circuit and GPIO circuit |
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