CN101741373A - Low voltage differential signal driver adaptive to various IO power supplies - Google Patents

Abstract

The invention discloses a low voltage differential signal driver adaptive to various IO power supplies. The low voltage differential signal driver comprises a differential conversion module, a pre-amplifier and a driving amplification circuit, wherein the differential conversion module is used for converting a low-voltage digital signal of a core into a differential voltage signal; the pre-amplifier is used for amplifying the differential voltage signal and outputting a positive path of voltage signals and a negative path of voltage signals; and the driving amplification circuit is used for amplifying the positive and negative paths of output signals of the pre-amplifier to obtain the output of the driver. The low-voltage differential signal driver automatically changes through bias along with the power supply and changes the control range of operational amplification to form a new circuit device. The low voltage differential signal driver is adapted to a microelectronic circuit of which core voltage is changed from low voltage 0.9 V to 1.5 V and IO voltage is changed from 1.8 V to high voltage 5 V through a topological structure where a low voltage core circuit and a high voltage IO circuit are separated and the bias which comes from the low voltage of the core and is flexibly adapted to the high voltage of the IO power supply, can be used for a multi-path LVDS driver and can transmit data at a rate of 1 G bit per second (bps).

Description

The low-voltage differential signal driver of the multiple IO power supply of a kind of self adaptation

Technical field

The present invention relates to a kind of circuit of LVDS (Low Voltage Differential Signal, low-voltage differential signal) driver of deep-submicron, in particular a kind of microelectronic circuit that adapts to the lvds driver of multiple IO power supply.

Background technology

In the design of modem electronic circuitry, use a large amount of differential lines come in the plate or plate between long distance High-speed rate signal, be the LVDS differential lines and wherein use maximum.But along with the reduction of the supply voltage of integrated circuit, integrated circuit kernel (core) voltage can fall to such an extent that form very for a short time very soon, but the reduction of speed of the voltage of IO is more slowly than core voltage height, and both reductions of speed are disproportionate.

So in order to adapt to the gap of core voltage and IO voltage, people can only ceaselessly revise the circuit of lvds driver, the redesign as biasing has brought the bottleneck of many designs.Such as, a kind of technology of using the lvds driver of low-voltage is arranged in the prior art, it is to utilize switchable current source to control the LVDS switching tube, though can be used in the application under the low pressure, but, the common-mode voltage of lvds driver output is unstable easily first, and is if adopt common mode feedback circuit, higher to the requirement of common mode feedback circuit; Second describe inadequately for biasing, cause high-pressure and low-pressure to differ and use simultaneously surely.

As seen, there is certain problem in the prior art, needs further to improve.

Summary of the invention

The invention provides a kind of low-voltage differential signal driver that adapts to multiple IO power supply, it utilizes the general core voltage characteristics lower than IO voltage dexterously, for the IO drive circuit provides stable biasing, and then makes the IO driver can adapt to the requirement of multiple IO voltage.

For achieving the above object, the present invention adopts following technical scheme:

The low-voltage differential signal driver of the multiple IO power supply of adaptation of the present invention, it comprises: the differential conversion module is used for converting the digital signal of kernel low pressure to differential voltage signal; Prime amplifier is used for described differential voltage signal is carried out processing and amplifying, exports positive and negative two-way voltage signal; Drive amplifying circuit, be used for the positive and negative two-way output signal of described prime amplifier is carried out processing and amplifying, obtain the output of described driver.

Described driver, wherein, described driver also comprises: be connected on the output of described prime amplifier and the buffer cell between the described driving input amplifier.

Described driver, wherein, described driving amplifying circuit comprises: two PMOS pipes, two NMOS manage and resistance unit; The positive output of described prime amplifier is divided two-way, and the described buffer cell of wherein leading up to connects the grid of a PMOS pipe, and another road connects the grid of a NMOS pipe by described buffer cell; The negative output of described prime amplifier is divided two-way, and the described buffer cell of wherein leading up to connects the grid of another PMOS pipe, and another road connects the grid of another NMOS pipe by described buffer cell; The source electrode of described two PMOS pipes links to each other, and is connected to the positive bias power end; The source electrode of described two NMOS pipes links to each other, and is connected to the negative bias power end; Described PMOS pipe links to each other with the drain electrode of a described NMOS pipe, and is connected to the positive output end of described driver; Described another PMOS pipe links to each other with the drain electrode of described another NMOS pipe, and is connected to the negative output terminal of driver; Link to each other by described resistance unit between described positive output end and the negative output terminal.

Described driver, wherein, the positive supply of described positive bias power end is to utilize a bias voltage to input in the buffer structure that is made of N type operational amplifier to obtain; The negative supply of described negative bias power end is to utilize a bias voltage to input in the buffer structure that is made of P type operational amplifier to obtain.

Described driver, wherein, described positive bias power end is connected to the drain electrode of another PMOS pipe, and the source electrode of this PMOS pipe connects IO voltage, and the grid of this PMOS pipe connects a control signal.

Described driver, wherein, described driver also comprises: the biasing module that is used for providing for driver according to kernel low pressure and IO voltage bias voltage, in biasing module, be connected to the drain electrode of NMOS pipe MLN1 by a resistance R L1 from the kernel low-voltage, the grid leak of NMOS pipe MLN1 links to each other, the source ground of NMOS pipe MLN1; The grid of NMOS pipe MLN2 links to each other with the grid of NMOS pipe MLN1, the source ground of NMOS pipe MLN2; The drain electrode of NMOS pipe MLN2 links to each other with the drain electrode of PMOS pipe MBP3, the grid leak of PMOS pipe MBP3 links to each other, the source electrode of PMOS pipe MBP3 connects IO voltage, the grid of PMOS pipe MBP4, PMOS pipe MBP5, PMOS pipe MBOP and the grid of PMOS pipe MBP3 link to each other, and the source electrode of PMOS pipe MBP4, PMOS pipe MBP5, PMOS pipe MBOP is received IO voltage; The drain terminal of PMOS pipe MBP4 links to each other with the drain terminal of NMOS pipe MBN3, and the source electrode of NMOS pipe MBN3 links to each other with the drain electrode of NMOS pipe MBN1, and the grid of NMOS pipe MBN3 links to each other with the drain electrode of PMOS pipe MBP6 and NMOS pipe MBN6; PMOS pipe MBP6 links to each other with the grid leak of NMOS pipe MBN6, and the source electrode of PMOS pipe MBP6 connects the kernel low-voltage, the source ground of NMOS pipe MBN6; PMOS pipe MBP5 links to each other with the drain electrode of NMOS pipe MBN4, and the source electrode of NMOS pipe MBN4 links to each other with the drain electrode of NMOS pipe MBN2, and bias voltage VREF1 is provided, and the grid of NMOS pipe MBN4 links to each other with the output of inverter INV2 with inverter INV1; The source ground of NMOS pipe MBN2, the grid of NMOS pipe MBN2 is connected with the grid of NMOS pipe MBN1, the drain electrode of PMOS pipe MBOP links to each other with the drain electrode of NMOS pipe MBON1, the grid leak of NMOS pipe MBON1 links to each other, and output offset voltage VREF_POP, the grid leak of NMOS pipe MBON1 links to each other, and the source ground of NMOS pipe MBON1; The end of the input of inverter INV1 and resistance R L2, resistance R L3 links to each other, the other end of resistance R L2 is connected to IO voltage, resistance R L2, resistance R L3, resistance R L4 are connected in series successively, the other end of resistance R L3 links to each other with the input of INV2, the end of resistance R L4 is connected to the drain electrode of NMOS pipe MBN5, the grid of NMOS pipe MBN5 is connected to described bias voltage VREF1, and the source electrode of NMOS pipe MBN5 links to each other with resistance R L6, and the other end of resistance R L6 is connected to ground; The output of described bias voltage VREF1 links to each other with the grid of NMOS pipe MBN9, and source electrode and the grounded drain of NMOS pipe MBN9 have formed a mos capacitance; The source electrode of the normal phase input end of one N type amplifier and NMOS pipe MBN8 also is connected to kernel low-voltage vddcore together; The output of described N type amplifier is received the grid of PMOS pipe MBP9 and PMOS pipe MBOP1, and forms bias voltage VREF_POP; The source electrode of PMOS pipe MBP9 connects IO voltage, and the drain electrode of PMOS pipe MBP9 is connected to the negative-phase input of resistance R L7 and described N type amplifier, forms buffer structure; N type amplifier 1 be biased to bias voltage VREF_NOP; The other end ground connection of resistance R L7, the drain electrode output offset voltage VREF3 of PMOS pipe MBOP1; The grid leak of NMOS pipe MBN8 links to each other and forms bias voltage VREF2, and the drain electrode of the output of bias voltage VREF2 and PMOS pipe MBP8 links to each other; The source electrode of PMOS pipe MBP8 connects IO voltage, and the grid of PMOS pipe MBP8 extremely links to each other with the grid leak of PMOS pipe MBP7; The source electrode of PMOS pipe MBP7 meets IO voltage vddio, the grid leak of PMOS pipe MBP7 is extremely continuous, and the grid of PMOS pipe MBP7 links to each other with the drain electrode of the grid of PMOS pipe MBP8, NMOS pipe MBN7, the source ground of NMOS pipe MBN7, and the grid of NMOS pipe MBN7 connects bias voltage VREF1.

Described driver, wherein, between the bias voltage VREF3 output of described biasing module and kernel low pressure successively by series resistance R1, resistance R 2, resistance R 3, resistance R 4 ground connection; Insert kernel low pressure between resistance R 2 and resistance R 3, and the output between described resistance R 1 and the resistance R 2 inserts the normal phase input end of described N type operational amplifier, the output of described resistance R 3 and resistance R 4 inserts the normal phase input end of described P type operational amplifier.

Described driver, wherein, described prime amplifier comprises: PMOS pipe MN3, PMOS pipe MN4, NMOS pipe MN1, NMOS pipe MN2 and NMOS pipe MN0; Receive the grid that NMOS manages MN1 and NMOS pipe MN2 respectively through the differential signal that described differential conversion module forms, NMOS pipe MN1 links to each other with the source electrode of NMOS pipe MN2, and connecing the drain electrode that NMOS manages MN0, the grid of NMOS pipe MN0 meets described bias voltage VREF1, the source ground of NMOS pipe MN0; The drain electrode of NMOS pipe MN1 and NMOS pipe MN2 connects the source electrode of PMOS pipe MN3 and PMOS pipe MN4 respectively, and the grid of PMOS pipe MN3 and PMOS pipe MN4 meets described bias voltage VREF2, and the drain electrode of PMOS pipe MN3 and PMOS pipe MN4 connects the output of described prime amplifier; The drain electrode of PMOS pipe MN3 and PMOS pipe MN4 is connected to the drain electrode of high-voltage tube MPP1 respectively together by resistance R 1 and resistance R 2; The source electrode of high-voltage tube MPP1 connects IO voltage.

The invention effect: the present invention utilizes biasing to change automatically with power source change, and transforms the control range of amplifier, forms new line unit.This topological structure that separates by low pressure kernel circuitry and high pressure IO circuit, with derive from the biasing that kernel low pressure adapts to the IO high pressure again flexibly, adapt to core voltage from low pressure 0.9v to 1.5V, the microelectronic circuit of IO voltage from 1.8V to high pressure 5V, and can be used in the multichannel lvds driver, the speed of the data that can transmit reaches 1G bit rate (bps).

Description of drawings

Fig. 1 is the circuit block diagram of the lvds driver of the multiple IO power supply of self adaptation that proposes of the present invention;

Fig. 2 is the internal structure schematic diagram of the prime amplifier among Fig. 1 of the present invention,

Fig. 3 is the bias circuit construction schematic diagram of the multiple IO of adaptation of the present invention.

Embodiment

Below in conjunction with accompanying drawing, with the present invention is described in further detail.

As Fig. 1, lvds driver of the present invention on the whole comprises: connect the differential conversion module S2D of digital signal and the prime amplifier PREDRIVER of S2D and then, and drive amplifying circuit 200.The differential conversion module is used for converting the digital signal of kernel low pressure to differential voltage signal; Prime amplifier is used for described differential voltage signal is carried out processing and amplifying, exports positive and negative two-way voltage signal; Drive amplifying circuit and be used for the positive and negative two-way output signal of described prime amplifier is carried out processing and amplifying, obtain the output of described driver.

As Fig. 1, buffer BUFFER1, BUFFER2, BUFFER3 and BUFFER4 constitute the buffer cell between output that is connected on prime amplifier and the input that drives amplifying circuit.Two NMOS pipes, two PMOS manage and resistance unit 201 formation driving amplifying circuits 200.

The positive output end of prime amplifier PREDRIVER is connecting buffer BUFFER1 and BUFFER2, the negative output terminal of prime amplifier PREDRIVER is connecting buffer BUFFER3 and BUFFER4, the output of buffer BUFFER1 is connecting the grid of PMOS pipe MU1, the output of buffer BUFFER2 is connecting the grid of NMOS pipe MD1, the output of buffer BUFFER3 is connecting the grid of PMOS pipe MU2, and the output of buffer BUFFER4 is connecting the grid of NMOS pipe MD2.Differential conversion module S2D is kernel low pressure vddcore power supply completely.Here buffer BUFFER1, BUFFER2, BUFFER3 and BUFFER4 is used for remedying the gap between different pieces of information processing speed speed.The effect of prime amplifier PREDRIVER is the driving force that increases differential signal.

PMOS pipe MU1 links to each other with the source electrode of PMOS pipe MU2, and is connected to positive bias power end VHIGH end; NMOS pipe MD1 links to each other with the source electrode of NMOS pipe MD2, and is connected to negative bias power end VLOW end.The VHIGH end here is the output of the buffer structure OP1 of N type amplifier formation; And the VLOW end is the output of the buffer structure OP2 of P type amplifier formation.For the LVDS common mode range that arrives 1.525V at 0.875V, the input voltage Vh that can recommend buffer structure OP1 is 1.5v, and the input voltage Vl of buffer structure OP2 is 0.9v.Below will describe the acquisition principle of input voltage Vh and Vl in detail.

NMOS pipe MD1 links to each other with the drain electrode of PMOS pipe MU1, and is connected to the positive output end VOUTP of driver; NMOS pipe MD1 links to each other with the drain electrode of PMOS pipe MU1, and is connected to the negative output terminal VOUTN of driver.PMOS pipe MU1 here and the size of MU2 are the same big, and the size of NMOS pipe MD1 and MD2 is the same big.And, link to each other by external resistance unit between the negative output terminal VOUTN of the positive output end VOUTP of driver and driver usually, such as connecting by 100 Europe resistance, as shown in Figure 1, it adopts two 50 Europe of series connection, and equivalence is one 100 Europe mode.

Above-mentioned VHGH end is connected to the drain electrode of PMOS pipe MU0, and the source electrode of PMOS pipe MU0 meets IO voltage vddio, and the grid of PMOS pipe MU0 connects control signal PWDN signal, and this PWDN signal is realized lvds driver is carried out necessary power down function.

The foregoing circuit total needs 5 biasing: VREF1, VREF2, and VREF3, VREF POP, VREF NOP by biasing module, produces as Fig. 3.

Fig. 3 describes biasing VREF1, VREF2, VREF3, VREF_POP, the generation circuit of VREF_NOP.Be connected to the drain electrode that NMOS manages MLN1 from kernel low-voltage vddcore by a resistance R L1, the grid leak of NMOS pipe MLN1 pipe links to each other, the source ground of NMOS pipe MLN1; The grid of NMOS pipe MLN2 links to each other with the grid of NMOS pipe MLN1, and the source electrode of NMOS pipe MLN2 is ground connection also, and NMOS pipe MLN1 is the same big with the size of NMOS pipe MLN2.The drain electrode of NMOS pipe MLN2 links to each other with the drain electrode of PMOS pipe MBP3, the grid leak of PMOS pipe MBP3 also links to each other, the source electrode of PMOS pipe MBP3 meets IO voltage vddio, the grid of PMOS pipe MBP4, PMOS pipe MBP5, PMOS pipe MBOP and the grid of PMOS pipe MBP3 link to each other, the source electrode of PMOS pipe MBP4, PMOS pipe MBP5, PMOS pipe MBOP is received IO voltage vddio, and the size of PMOS pipe MBP3, PMOS pipe MBP4, PMOS pipe MBP5, PMOS pipe MBOP is equally big.The drain terminal of PMOS pipe MBP4 links to each other with the drain terminal of NMOS pipe MBN3, the source electrode of NMOS pipe MBN3 links to each other with the drain electrode of NMOS pipe MBN1, the grid of NMOS pipe MBN3 links to each other with the drain electrode of PMOS pipe MBP6 and NMOS pipe MBN6, the size of NMOS pipe MBN3, NMOS pipe MBN4 pipe is equally big, and the size of MBN1 and MBN2 pipe is the same big.PMOS pipe MBP6 and NMOS pipe MBN6 are that grid leak links to each other, and the MBP6 source electrode meets kernel low-voltage v ddcore, the source ground of NMOS pipe MBN6.NMOS pipe MBN1 also is that grid leak links to each other, the source ground of NMOS pipe MBN1.

PMOS pipe MBP5 links to each other with the drain electrode of NMOS pipe MBN4, and the source electrode of NMOS pipe MBN4 links to each other with the drain electrode of NMOS pipe MBN2, and this root connecting line is reference offset voltage VREF1, and the grid of NMOS pipe MBN4 links to each other with the output of inverter INV2 with inverter INV1.The source ground of NMOS pipe MBN2, the grid of NMOS pipe MBN2 is connected with the grid of NMOS pipe MBN1, and the grid leak of MBN1 links to each other.The drain electrode of PMOS pipe MBOP links to each other with the drain electrode of NMOS pipe MBON1, and the grid leak of NMOS pipe MBON1 links to each other, and is output as bias voltage VREF_POP, and the grid leak of NMOS pipe MBON1 links to each other, and the source ground of NMOS pipe MBON1.

The end of the input of inverter INV1 and resistance R L2, resistance R L3 links to each other, the other end of resistance R L2 is connected to IO voltage vddio, resistance R L2, resistance R L3, resistance R L4 are connected in series successively, the other end of resistance R L3 links to each other with the input of INV2, the end of resistance R L4 is connected to the drain electrode of NMOS pipe MBN5, the grid of NMOS pipe MBN5 is connected to bias voltage VREF1, and the source electrode of NMOS pipe MBN5 links to each other with resistance R L6, and the other end of resistance R L6 is connected to ground.The output of bias voltage VREF1 also links to each other with the grid of NMOS pipe MBN9, source electrode and all ground connection that drains of NMOS pipe MBN9, and MBN9 has just formed a mos capacitance like this.

The source electrode of the normal phase input end of one N type amplifier 1 and NMOS pipe MBN8 also is connected to kernel low-voltage vddcore together.

The output of N type amplifier 1 is received the grid of PMOS pipe MBP9 and PMOS pipe MBOP1, and formation bias voltage VREF POP, the source electrode of PMOS pipe MBP9 meets IO voltage vddio, the drain electrode of PMOS pipe MBP9 is connected to the negative-phase input of resistance R L7 and N type amplifier 1, also become a kind of buffer structure, N type amplifier 1 be biased to bias voltage VREF_NOP.The other end ground connection of resistance R L7.And the drain electrode of PMOS pipe MBOP1 is exactly bias voltage VREF3.

The grid leak of NMOS pipe MBN8 links to each other, and forms bias voltage VREF2, and links to each other with the drain electrode of PMOS pipe MBP8.The source electrode of PMOS pipe MBP8 meets IO voltage vddio, and the grid of PMOS pipe MBP8 extremely links to each other with the grid leak of PMOS pipe MBP7, and the size of PMOS pipe MBP7, PMOS pipe MBP8 pipe is equally big.The source electrode of PMOS pipe MBP7 meets IO voltage vddio, the grid leak of PMOS pipe MBP7 is extremely continuous, remove with the grid of PMOS pipe MBP8 and link to each other, and the grid of PMOS pipe MBP7 links to each other with the drain electrode of the grid of PMOS pipe MBP8, NMOS pipe MBN7, the source ground of NMOS pipe MBN7, the grid of NMOS pipe MBN7 connects bias voltage VREF1.

The grid of NMOS pipe MBP8 connects the drain electrode of PMOS pipe MBP11 and the grid of NMOS pipe MBN11, the source ground of NMOS pipe MBN11, the drain electrode of PMOS pipe MBP11 connects the drain electrode of NMOS pipe MBN11 and the grid of PMOS pipe MBP11, and the source electrode of PMOS pipe MBP11 connects IO voltage vddio.

As shown in Figure 1, between bias voltage VREF3 and kernel low pressure vddcore, receive ground by series resistance R1, R2, R3, R4 successively.Directly insert kernel low-tension supply vddcore at R2 and R3, directly insert vh, directly insert vl at R3 and R4 at R1 and R2.For the LVDS common mode range that arrives 1.525V at 0.875V, can recommend Vh is 1.5v, and Vl is 0.9v.Vh inserts the normal phase input end of above-mentioned N type operational amplifier OP1, and N type operational amplifier OP1 is connected into buffer structure, and promptly output is connected with negative-phase input, and its output is VHIGH end, and N type operational amplifier OP1 is biased to bias voltage VREF_NOP.

Above-mentioned Vl inserts the anode of P type operational amplifier OP2, and P type operational amplifier OP2 also is connected into buffer structure, i.e. output is connected with negative-phase input, and its output is that VLOW holds, and P type operational amplifier OP2 is biased to bias voltage VREF_POP.

For prime amplifier structure shown in Figure 2, low voltage digital signal becomes differential signal VINP, VINN through differential conversion module S2D, and receive the grid of NMOS pipe MN1 and NMOS pipe MN2 respectively, NMOS pipe MN1 links to each other with the source electrode of NMOS pipe MN2, and the drain electrode of receiving NMOS pipe MN0, the grid of NMOS pipe MN0 meets bias voltage VREF1, the source ground of NMOS pipe MN0.The drain electrode of NMOS pipe MN1 and MN2 connects the source electrode of PMOS pipe MN3 and PMOS pipe MN4 respectively, and the grid of PMOS pipe MN3 and PMOS pipe MN4 meets bias voltage VREF2, and the drain electrode of PMOS pipe MN3 and PMOS pipe MN4 meets the output VOUTP and the VOUTN of prime amplifier.Simultaneously, the drain electrode of PMOS pipe MN3 and PMOS pipe MN4 is connected to the drain electrode of high-voltage tube MPP1 respectively together by resistance R 1 and resistance R 2.PMOS pipe MN3 is the same big with the size of PMOS pipe MN4, and NMOS pipe MN1 is the same big with the size of NMOS pipe MN2.The grid of high-voltage tube MPP1 connects control signal PWDN signal equally, and the source electrode of high-voltage tube MPP1 meets IO voltage vddio.The PWDN signal of MPP1 also is that lvds driver is carried out necessary power down function, can close the output of LVDS when being necessary.Prime amplifier PREDRIVER (as Fig. 2) be by IO voltage vddio power supply, but each biasing is to be provided by circuit shown in Figure 3 like this.When practical application, can set the kernel low-tension supply value of biasing VREF1=1/3 approx; The high voltage source value of the IO voltage of biasing VREF2=2/3.

From said structure as can be seen, the present invention at first changes two voltage signals that convert difference to the digital signal of kernel low pressure by list, converts the differential signal of IO high pressure then to by prime amplifier; Simultaneously, utilize kernel low pressure, form biasing such as the many places that comprise pre-driver, N type amplifier, P type amplifier, syntype bias by the feedback arrangement that designs, and make them be adaptive to the variation of IO voltage neatly as the biasing in the circuit of IO high pressure; Drive two pairs of PMOS pipes NMOS pipe by different buffer delay line then, by alternately opening PMOS pipe and NMOS pipe, make electric current from high potential through the external resistance electronegative potential of flowing through, generation Low Voltage Differential Signal.

The course of work of above-mentioned integrated circuit is described below:

At first, the digital signal of kernel low pressure is changeed two voltage signals that convert difference to by list, convert differential signal under the IO high pressure to by pre-driver then, by four delay line BUFFER1, BUFFER2, BUFFER3, BUFFER4 drive two couples of PMOS pipe MU1, MU2 and two NMOS pipes MD1, MD2.The time of delay of BUFFER1 and BUFFER2 is the same, because very zero conducting of gate pmos, the NMOS tube grid is high conducting, MU1 and MD2 conducting together; In like manner, the time of delay of BUFFER3 and BUFFER4 is the same, MU2 and MD1 conducting together.Like this, by alternately opening PMOS pipe and NMOS pipe, make electric current from high potential through the external resistance electronegative potential of flowing through, generation Low Voltage Differential Signal.But the time of delay of BUFFER1 and BUFFER3 is more a little bit smaller a little than the time of delay of BUFFER2 and BUFFER4, is because avoid like this, MU1 and MD1, and the perhaps moment conducting of MU2 and MD2 forms short circuit current.

N type operational amplifier OP1, P type operational amplifier OP2, N type amplifier 1 here all have been the effects of buffer, be because these signals take out from resistance string, are not suitable for directly connecing capacitive load, be connected into buffer with operational amplifier, solve the ability of this band capacitive load well.

Biasing module for Fig. 3, the vddcore of low pressure, produce stable electric current by resistance R L1 and MBN1, because MBN1 and MBN2 are mirror current sources, MBP3, MBP4, MBP5, MBOP also is a mirror current source, and then, the electric current of MBP4, MBN3, MBN1 branch road and MBP5, MBN4, MBN2 branch road equates.Because what MBN6 and MBP6 formed is the structure of two DIODE, the grid voltage of MBN3 is exactly vddio/2, and the grid voltage of MBN1 has just been determined like this, and VREF1 just only is decided by the grid voltage of MBN4.

And in RL2, RL3, RL4, MBN5, the RL6 branch road, the gate bias voltage of MBN9 is fixed, to RL2, the RL3 of proper proportion, RL4, RL6 value (as 1: 8: 2: 0.3, or RL4 is arranged to active pull-up by VREF2 control), the input voltage of INV1 is higher, and the input voltage of INV2 is on the low side, and the grid voltage of MBN4 is just set vddio/2 easily for like this, VREF1 is main relevant with the size of current mirror MBN2 like this, is relevant very little with vddcore, vddio only.When the size of MBN2 is determined, when vddcore was constant, when vddio changes (as when 5v or 3.3V change to 2.5V or 1.8V), VREF1 can correspondingly change, but changes very for a short time.When the digital signal of input is overturn, can cause that VREF1 rises or descends, and supposes to rise, the equivalent resistance of MBN5 can descend like this, thereby the grid voltage that causes INV1 and INV2 all descends, thereby the grid voltage that causes MBN4 rises, the equivalent resistance of MBN4 increases, and causes VREF1 to descend; Otherwise when VREF1 descended, feedback promoted VREF1 equally.And mos capacitance MBN9 also can carry out the effect of elimination ripple to VREF1, and VREF1 keeps stable substantially like this.As a kind of approximate calculation, can draw

$V_{\mathrm{vref}1}\≈\frac{1}{3}{V}_{\mathrm{vddcore}}.$

In the above-mentioned formula, V _Vref1The size of expression bias voltage VREF1; V _VddcoreThe size of expression kernel low pressure vddcore.

Because the relation of the image current of MBP7 and MBP8, the voltage of the grid leak utmost point VREF2 of MBN8 pipe are also only relevant with the equivalent resistance of vddcore and MBN8.Because MBN11 and MBP11 all are connected into the diode structure that drain-gate joins, therefore the equivalent resistance of MBN8 is only relevant with vddio, so VREF2 is only relevant with vddcore and vddio, and VREF2 is lower than vddio, is suitable as the high-voltage tube MN3 of Fig. 2 and the bias voltage of MN4.As a kind of approximate calculation, can draw equally

$V_{\mathrm{vref}2}=V_{\mathrm{vddcore}}+R_{\mathrm{mbn}8}\≈V_{\mathrm{vddcore}}+\frac{1}{3}{V}_{\mathrm{vddio}}$

In the above-mentioned formula, V _Vref2The size of expression bias voltage VREF2; V _VddioThe size of expression IO voltage vddio, R _Mbn8The size of the equivalent resistance of expression MBN8.

Because the relation of the image current of MBOP and MBP3, the grid leak utmost point VREF_NOP of MBON1 pipe is only relevant with vddcore, as a kind of approximate calculation, can draw

$V_{\mathrm{vref}\_\mathrm{nop}}=\frac{V_{\mathrm{vddio}}}{V_{\mathrm{vddcore}}}\×V_{\mathrm{MLN}1}\≈1.7\×V_{\mathrm{vref}1}$

In the above-mentioned formula, V _{Vref_nop}The size of expression bias voltage VREF_NOP; V _MLN1The drain-source voltage of expression NMOS pipe MLN1.

The output of N type amplifier 1 drives PMOS pipe MBP9, MBP9, RL7 branch road constitute the dividing potential drop feedback arrangement, the grid of MBP9 pipe links to each other with the output stage of N type amplifier 1, N type amplifier 1 plays the effect of buffer, the output of N type amplifier 1 obtains littler than IO voltage vddio, only relevant with a vddcore stable biasing VREF_POP like this, along with the setting of the resistance of RL7, as a kind of approximate calculation, can draw

$V_{\mathrm{vref}\_\mathrm{pop}}=V_{\mathrm{vddcore}}\×\frac{R_{\mathrm{RL}7}+R_{\mathrm{mbp}9}}{R_{\mathrm{RL}7}},$

In the above-mentioned formula, V _{Vref_pop}The size of expression bias voltage VREF_POP; R _RL7The size of expression resistance R L7, R _Mbp9The size of the equivalent resistance of expression MBP9.The value of bias voltage VREF_POP can be adjusted to the bias voltage that is fit to very much do P type operational amplifier.。

VREF_POP control PMOS pipe MBOP1 obtains one like this than the littler VREF3's of vddio variation.Since the effect of series circuit, the vddcore that between R2 and R3, inserts, for R1, R2, R3, the R4 resistance of proper proportion, the variation of voltage vh and voltage vl is also very little, and promptly voltage vh and voltage vl are very stable.

From top analysis, as seen the variation of IO voltage vddio, except that the variation of VREF2 with moving Voutp that impels PREDRIVER and Voutn flexible adaptation vddio, VREF1, VREF3 and VREF_NOP, VREF_POP are very little with the variation of vddio, the stable of vh and vl makes the LVDS signal common mode range of output little again, here refer generally to the arrowband LVDS common mode range of 0.875v to 1.525v, thereby when being highly suitable for the IO change in voltage, the variation that circuit can self adaptation IO.Consider that LVDS broadband signal common mode range also allows the scope from 0.5v to 2.4v, adaptability then of the present invention is wider, for RSDS (Reduced Swing Differential Signal, low-swing difference signal) and Mini-LVDS (Mini Low Voltage Differential Signal, little low-voltage differential signal) also be to support.

This topological structure that separates by low pressure kernel circuitry and high pressure IO circuit, with derive from the biasing that kernel low pressure vddcore adapts to IO high pressure vddio again, can directly adapt to core voltage from low pressure 0.9v to 1.5v, the microelectronic circuit of IO voltage from 1.8v to high pressure 5v, and can be used in the multichannel lvds driver.Further, if from the principle of whole invention, also be can adapt to core voltage to be low to moderate 0.65v, IO voltage surpasses in the microelectronic circuit of lvds driver of high pressure 5V, but above approximate calculation formula does not re-use.

Because the speed of the whole lvds driver of decision mainly is the switching speed of pre-driver PREDRIVER and MU1, MU2, MD1, MD2, and the gain of pre-driver PREDRIVER of the present invention is very little so bandwidth can be very big, and the maximum current limit that the switching speed of MU1, MU2, MD1, MD2 only tolerates, therefore the speed of the data that can transmit of whole lvds driver is very high, can reach 1.3G bit rate (bps).

Should be understood that; above-mentioned description at the specific embodiment of the invention is comparatively detailed; but can not therefore be interpreted as restriction to scope of patent protection of the present invention; simple and easy reasoning of all processes and conversion all are the included scopes of the present invention, and scope of patent protection of the present invention should be as the criterion with claims.

Claims (8)

1. the low-voltage differential signal driver of the multiple IO power supply of self adaptation is characterized in that, described driver comprises:

The differential conversion module is used for converting the digital signal of kernel low pressure to differential voltage signal;

Prime amplifier is used for described differential voltage signal is carried out processing and amplifying, exports positive and negative two-way voltage signal;

Drive amplifying circuit, be used for the positive and negative two-way output signal of described prime amplifier is carried out processing and amplifying, obtain the output of described driver.

2. driver according to claim 1 is characterized in that, described driver also comprises: be connected on the output of described prime amplifier and the buffer cell between the described driving input amplifier.

3. driver according to claim 2 is characterized in that, described driving amplifying circuit comprises: two PMOS pipes, two NMOS manage and resistance unit;

The positive output of described prime amplifier is divided two-way, and the described buffer cell of wherein leading up to connects the grid of a PMOS pipe, and another road connects the grid of a NMOS pipe by described buffer cell; The negative output of described prime amplifier is divided two-way, and the described buffer cell of wherein leading up to connects the grid of another PMOS pipe, and another road connects the grid of another NMOS pipe by described buffer cell; The source electrode of described two PMOS pipes links to each other, and is connected to the positive bias power end; The source electrode of described two NMOS pipes links to each other, and is connected to the negative bias power end; Described PMOS pipe links to each other with the drain electrode of a described NMOS pipe, and is connected to the positive output end of described driver; Described another PMOS pipe links to each other with the drain electrode of described another NMOS pipe, and is connected to the negative output terminal of driver; Link to each other by described resistance unit between described positive output end and the negative output terminal.

4. driver according to claim 3 is characterized in that, the positive supply of described positive bias power end is to utilize a bias voltage to input in the buffer structure that is made of N type operational amplifier to obtain; The negative supply of described negative bias power end is to utilize another bias voltage to input in the buffer structure that is made of P type operational amplifier to obtain.

5. driver according to claim 3 is characterized in that described positive bias power end is connected to the drain electrode of another PMOS pipe, and the source electrode of this PMOS pipe connects IO voltage, and the grid of this PMOS pipe connects a control signal.

6. driver according to claim 4, it is characterized in that, described driver also comprises: the biasing module that is used for providing for driver according to kernel low pressure and IO voltage bias voltage, in biasing module, be connected to the drain electrode of NMOS pipe MLN1 by a resistance R L1 from the kernel low-voltage, the grid leak of NMOS pipe MLN1 links to each other, the source ground of NMOS pipe MLN1; The grid of NMOS pipe MLN2 links to each other with the grid of NMOS pipe MLN1, the source ground of NMOS pipe MLN2; The drain electrode of NMOS pipe MLN2 links to each other with the drain electrode of PMOS pipe MBP3, the grid leak of PMOS pipe MBP3 links to each other, the source electrode of PMOS pipe MBP3 connects IO voltage, the grid of PMOS pipe MBP4, PMOS pipe MBP5, PMOS pipe MBOP and the grid of PMOS pipe MBP3 link to each other, and the source electrode of PMOS pipe MBP4, PMOS pipe MBP5, PMOS pipe MBOP is received IO voltage; The drain terminal of PMOS pipe MBP4 links to each other with the drain terminal of NMOS pipe MBN3, and the source electrode of NMOS pipe MBN3 links to each other with the drain electrode of NMOS pipe MBN1, and the grid of NMOS pipe MBN3 links to each other with the drain electrode of PMOS pipe MBP6 and NMOS pipe MBN6; PMOS pipe MBP6 links to each other with the grid leak of NMOS pipe MBN6, and the source electrode of PMOS pipe MBP6 connects the kernel low-voltage, the source ground of NMOS pipe MBN6;

PMOS pipe MBP5 links to each other with the drain electrode of NMOS pipe MBN4, and the source electrode of NMOS pipe MBN4 links to each other with the drain electrode of NMOS pipe MBN2, and bias voltage VREF1 is provided, and the grid of NMOS pipe MBN4 links to each other with the output of inverter INV2 with inverter INV1;

The source ground of NMOS pipe MBN2, the grid of NMOS pipe MBN2 is connected with the grid of NMOS pipe MBN1, the drain electrode of PMOS pipe MBOP links to each other with the drain electrode of NMOS pipe MBON1, the grid leak of NMOS pipe MBON1 links to each other, and output offset voltage VREF_POP, the grid leak of NMOS pipe MBON1 links to each other, and the source ground of NMOS pipe MBON1;

The end of the input of inverter INV1 and resistance R L2, resistance R L3 links to each other, the other end of resistance R L2 is connected to IO voltage, resistance R L2, resistance R L3, resistance R L4 are connected in series successively, the other end of resistance R L3 links to each other with the input of INV2, the end of resistance R L4 is connected to the drain electrode of NMOS pipe MBN5, the grid of NMOS pipe MBN5 is connected to described bias voltage VREF1, and the source electrode of NMOS pipe MBN5 links to each other with resistance R L6, and the other end of resistance R L6 is connected to ground; The output of described bias voltage VREF1 links to each other with the grid of NMOS pipe MBN9, and source electrode and the grounded drain of NMOS pipe MBN9 have formed a mos capacitance;

The source electrode of the normal phase input end of one N type amplifier and NMOS pipe MBN8 also is connected to kernel low-voltage vddcore together; The output of described N type amplifier is received the grid of PMOS pipe MBP9 and PMOS pipe MBOP1, and forms bias voltage VREF_POP; The source electrode of PMOS pipe MBP9 connects IO voltage, and the drain electrode of PMOS pipe MBP9 is connected to the negative-phase input of resistance R L7 and described N type amplifier, forms buffer structure; N type amplifier 1 be biased to bias voltage VREF_NOP; The other end ground connection of resistance R L7, the drain electrode output offset voltage VREF3 of PMOS pipe MBOP1;

The grid leak of NMOS pipe MBN8 links to each other and forms bias voltage VREF2, and the drain electrode of the output of bias voltage VREF2 and PMOS pipe MBP8 links to each other; The source electrode of PMOS pipe MBP8 connects IO voltage, and the grid of PMOS pipe MBP8 extremely links to each other with the grid leak of PMOS pipe MBP7; The source electrode of PMOS pipe MBP7 connects IO voltage, the grid leak of PMOS pipe MBP7 is extremely continuous, and the grid of PMOS pipe MBP7 links to each other with the drain electrode of the grid of PMOS pipe MBP8, NMOS pipe MBN7, the source ground of NMOS pipe MBN7, and the grid of NMOS pipe MBN7 connects bias voltage VREF1.

7. driver according to claim 6 is characterized in that, between the bias voltage VREF3 output of described biasing module and kernel low pressure successively by series resistance R1, resistance R 2, resistance R 3, resistance R 4 ground connection; Insert kernel low pressure between resistance R 2 and resistance R 3, and the output between described resistance R 1 and the resistance R 2 inserts the normal phase input end of described N type operational amplifier, the output of described resistance R 3 and resistance R 4 inserts the normal phase input end of described P type operational amplifier.

8. driver according to claim 6 is characterized in that, described prime amplifier comprises: PMOS pipe MN3, PMOS pipe MN4, NMOS pipe MN1, NMOS pipe MN2 and NMOS pipe MN0; Receive the grid that NMOS manages MN1 and NMOS pipe MN2 respectively through the differential signal that described differential conversion module forms, NMOS pipe MN1 links to each other with the source electrode of NMOS pipe MN2, and connecing the drain electrode that NMOS manages MN0, the grid of NMOS pipe MN0 meets described bias voltage VREF1, the source ground of NMOS pipe MN0; The drain electrode of NMOS pipe MN1 and NMOS pipe MN2 connects the source electrode of PMOS pipe MN3 and PMOS pipe MN4 respectively, and the grid of PMOS pipe MN3 and PMOS pipe MN4 meets described bias voltage VREF2, and the drain electrode of PMOS pipe MN3 and PMOS pipe MN4 connects the output of described prime amplifier;

The drain electrode of PMOS pipe MN3 and PMOS pipe MN4 is connected to the drain electrode of high-voltage tube MPP1 respectively together by resistance R 1 and resistance R 2; The source electrode of high-voltage tube MPP1 connects IO voltage.

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