CN100530966C - Receiver of low voltage difference signal - Google Patents
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- CN100530966C CN100530966C CNB200710163784XA CN200710163784A CN100530966C CN 100530966 C CN100530966 C CN 100530966C CN B200710163784X A CNB200710163784X A CN B200710163784XA CN 200710163784 A CN200710163784 A CN 200710163784A CN 100530966 C CN100530966 C CN 100530966C
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Abstract
The invention discloses a low-voltage differential signal (LVDS) receiver, realized on an integrate circuit, comprising an input-stage circuit (that receives differential signal of a full-width common-mode voltage, and converts the signal into a current signal), a current source circuit (connected to the input-stage circuit to provide current source) and a current mirror circuit (connected to the input-stage circuit and the current source circuit to provide a plurality of bias-voltage signals to the current source circuit and export a voltage signal to a buffer).
Description
Technical field
What the present invention relates to is a kind of signal receiver, particularly be a kind of receiver of low voltage difference signal.
Background technology
Now the demand of high speed data transfer just being promoted interfacing develops to the direction of high speed, serial, difference, low-power consumption and point-to-point interface, and the low voltage difference signal (low voltage differential signal LVDS) possesses all these characteristics.Low voltage difference signal (LVDS) has obtained using widely in the system that signal integrality, low jitter and common mode characteristic are had relatively high expectations.The low voltage differential signal is a kind of general transmission signal standard, and its high-speed transfer that is used in communication system and display interface device etc. is used.
On coffret, need much to organize low voltage difference signal (LVDS) transmitter, the low voltage difference signal (LVDS) of each group all needs an acceptor circuit to be used for receiving and amplifying small differential signal, imports chip internal at last into and does other signal and handle.
General low voltage difference signal (LVDS) receiver only utilizes two N type metal-oxide-semiconductor (MOS)s (NMOS) or two P type metal-oxide-semiconductor (MOS)s (PMOS) induction differential signal, can't receive fully for the differential signal of lower or higher common-mode voltage (common mode voltage).And a kind of " LVDSI/OInterfaceforGb/s-per-pinOperationin3.5umCMOS " that is delivered by IEEE solid-state circuit periodical, it discloses a kind of low voltage difference signal (LVDS) receiver and uses front-end amplifier (preamplifier) to receive and amplify small differential signal, utilizes regenerative circuit (regenerative circuit) to be pulled to full width output again.Each front-end amplifier needs extra bias circuit to drive running, and bias circuit occupies very big ratio for the power consumption of chip.
In addition, in high-speed data signal transmission circuit, transmitter is delivered to other end receiver by transmission line with signal and is received, when transmitter is closed no longer drive signal, have the differential noise (differentialnoise) that surpasses 20mV and be sent to receiver by transmission line and cause interference, influence receiving terminal circuit and operate.
General fail-safe (failsafe) circuit is by electric resistance partial pressure (offset voltage), form small voltage difference as the bucking voltage of receiving terminal to overcome differential noise, being illustrated in figure 1 as to have now has a pull-up resistor RPU and a drop-down resistance R PD to be connected two online actions of making dividing potential drop of transmission before low voltage difference signal receiver 1, and the shortcoming that this kind fail-safe circuit can produce comprises: the fail-safe circuit that is formed bucking voltage by electric resistance partial pressure, need extra resistance to form dividing potential drop, and this divider resistance is if go up realization at circuit board (PCB), then not only increase the complexity of board circuit, also can increase manufacturing cost; The another one shortcoming then is to have only one-way by the formed compensation of divider resistance, also be that receiver input anode has a bucking voltage forever greater than the input negative terminal, cause work period (duty-cycle) skew of receiver output signal, especially serious when low-frequency signal transmits.
Summary of the invention
In order to address the above problem, one of the object of the invention provides a kind of receiver of low voltage difference signal, it has a N type metal-oxide-semiconductor (MOS) (hereinafter to be referred as NMOS) input to importing receiving a small differential signal with a P type metal-oxide-semiconductor (MOS) (hereinafter to be referred as PMOS), the differential signal of common-mode voltage that so can the sensing full width, can the lower or higher differential signal of complete reception common-mode voltage, rail-to-rail receiver signal receiving ability is increased.
Another purpose of the present invention provides a kind of receiver of low voltage difference signal, it utilizes the circuit of receiver to be connected to form self-bias voltage, saves extra bias circuit, reduces current drain, except reaching the function of power saving, also can reduce layout (layout) area; The connection of the circuit of receiver is with current mirror mode delivered current signal in addition, avoids using repeatedly (Cascode) circuit of string, and Vdd that must be bigger just can operate smoothly, so make the present invention to operate under low-voltage.
Another purpose of the present invention provides a kind of receiver of low voltage difference signal, the differential voltage that it is exported receiver respectively, amplify the switch of controlling the MOS assembly again with individual other amplifier, cause unwanted effect to overcome differential noise, and can not impact simultaneously for the reflector output driving current of the other end.
In order to achieve the above object, the receiver of the low voltage difference signal of one embodiment of the invention, it is to be implemented on the integrated circuit, and comprise: an input stage circuit, it comprises one first differential signal loader and one second differential signal loader, the described first differential signal loader is in order to convert the low voltage difference signal to one first current signal, and the described second differential signal loader is in order to convert described low voltage difference signal to one second current signal;
The wherein said first differential signal loader receives one first predetermined voltage range of differential signal common-mode voltage and one second predetermined voltage range of described second differential signal loader reception differential signal common-mode voltage is only overlapped;
The wherein said first differential signal loader comprises one first pair pmos transistor, two source electrodes of described first pair pmos transistor are connected and two grids of described first pair pmos transistor receive described low voltage difference signal, and the described second differential signal loader comprises one first pair nmos transistor, and two source electrodes of described first pair nmos transistor are connected and two grids of described first pair nmos transistor receive described low voltage difference signal;
Wherein said low voltage difference signal comprises one first input voltage signal and one second input voltage signal;
One current source circuit connects input stage circuit, current source circuit according to several bias voltage signals to produce one group of required operating current of input stage circuit; And one current mirroring circuit connect current source circuit and input stage circuit, current mirroring circuit receives first current signal and second current signal producing an output voltage signal, and current mirroring circuit also produces several bias voltage signals to current source circuit according to first current signal and second current signal; Wherein, described current mirroring circuit comprises one first bias point and produces that one first bias voltage signal, one second bias point produce one second bias voltage signal, one the 3rd bias point produces one the 3rd bias voltage signal, produces one the 4th bias voltage signal with one the 4th bias point;
Also comprise a fail-safe circuit, it connects described current mirroring circuit, when the absolute value of the difference of described first input voltage signal and the described second input voltage signal during greater than a predetermined value, described fail-safe circuit is converted to one second predeterminated voltage value with described output voltage signal by one first original predeterminated voltage value;
Wherein said fail-safe circuit comprises: one the 3rd current source provides one the 3rd operating current; One the 3rd input amplifying circuit receives described second bias voltage signal and described output voltage signal, amplifies signal to produce one group the 3rd; One the 3rd Current Control assembly, described the 3rd Current Control assembly optionally produces one group of the 3rd Control current to described the 3rd bias point and described the 4th bias point according to described the 3rd operating current and described one group of the 3rd amplification signal; One the 4th current source provides one the 4th operating current; One the 4th input amplifying circuit receives described the 4th bias voltage signal and described output voltage signal, amplifies signal to produce one group the 4th; One the 4th Current Control assembly, described the 4th Current Control assembly optionally produces one group of the 4th Control current to described first bias point and described second bias point according to described the 4th operating current and described one group of the 4th amplification signal.
Description of drawings
Figure 1 shows that existing low voltage difference signal receiver front-end circuit schematic diagram;
Figure 2 shows that the circuit diagram of low voltage difference signal receiver according to an embodiment of the invention;
Fig. 3 A and Fig. 3 B are depicted as the fail-safe circuit diagram of one embodiment of the invention low voltage difference signal receiver;
Fig. 4 is that input voltage difference and the output voltage according to one embodiment of the invention low voltage difference signal receiver concerns schematic diagram.
Description of reference numerals: 1-low voltage difference signal receiver; The RPU-pull-up resistor; The RPD-pull down resistor; 10,20-differential signal loader; 30,40-current source circuit; 50,60-input amplifying circuit; Vip, Vin-low voltage difference signal; The Von-output; M1～M16-metal-oxide-semiconductor (MOS); Mn, Mp-metal-oxide-semiconductor (MOS); Mn1, Mn2-metal-oxide-semiconductor (MOS); Mp1, Mp2-metal-oxide-semiconductor (MOS); M21～M28-metal-oxide-semiconductor (MOS).
Embodiment
Below in conjunction with accompanying drawing, be described in more detail with other technical characterictic and advantage the present invention is above-mentioned.
The present invention discloses low voltage difference signal (LVDS) receiver, and the low voltage difference signal receiver comprises: an input stage circuit receives the low voltage difference signal and converts thereof into two current signals; One current source circuit connects input stage circuit, and produces the required operating current of input stage circuit according to several bias voltage signals; And one current mirroring circuit connect current source circuit and input stage circuit, and the received current signal produces the output voltage signal, in addition current mirroring circuit according to current signal to produce several bias voltage signals to current source circuit.
Figure 2 shows that the circuit diagram of one embodiment of the invention low voltage difference signal receiver.Input stage circuit comprises two differential signal loaders 10 and 20, differential signal loader 10 is in order to convert the low voltage difference signal to a current signal, differential signal loader 10 comprises a pair of PMOS transistor M3, M4, and two source electrodes of PMOS transistor M3, M4 are connected and its two grid receives low voltage difference signal Vip and Vin; Another differential signal loader 20 is in order to convert low voltage difference signal Vip and Vin to a current signal, differential signal loader 20 comprises pair of NMOS transistors M9, M10, and two source electrodes of nmos pass transistor M9, M10 are connected and its two grid receives low voltage difference signal Vip and Vin.
One current source circuit 30 produces the required operating current of differential signal loader 10, and it comprises a pair of PMOS transistor M1, M2, and two source electrodes of PMOS transistor M1, M2 are connected to two drain electrodes of a voltage source and PMOS transistor M1, M2 and are connected; And another current source circuit 40 comprises pair of NMOS transistors M11, M12, two source electrodes of nmos pass transistor M11, M12 be connected to a voltage source and nmos pass transistor M11, M12 two the drain electrode join.
Current mirroring circuit comprises: a current mirror group is between differential signal loader 10 and differential signal loader 20, and the current mirror group produces a sum total current signal I14 according to the current signal of differential signal loader 10,20; Another current mirror group is between differential signal loader 10 and differential signal loader 20, and it produces another sum total current signal I23 according to the current signal of differential signal loader 10,20.Current mirroring circuit produces output voltage signal Von according to sum total current signal I14, I23.
The current mirror group comprises: current mirror M5 received current signal I1 is to produce a reflection current signal, and another current mirror M8 connects current mirror M5, and current mirror M8 produces sum total current signal I14 according to current signal I4 and reflection current signal.Current mirror M5 produces the bias voltage signal to current source circuit 30 according to current signal I1, and current mirror M8 produces the bias voltage signal to current source circuit 40 according to current signal I4 with the reflection current signal.
Another current mirror group comprises: current mirror M7 received current signal I3 is to produce a reflection current signal, and another current mirror M6 connects current mirror M7, and current mirror M6 produces another sum total current signal I23 according to current signal I2 and reflection current signal.Current mirror M7 produces the bias voltage signal to current source circuit 40 according to current signal I3, and current mirror M6 produces the bias voltage signal to current source circuit 30 according to current signal I2 with the reflection current signal.
Figure 2 shows that the circuit diagram of one embodiment of the invention low voltage difference signal receiver.In the present embodiment, one input stage circuit receives differential signal Vip, the Vin of the common-mode voltage of a full width, input stage circuit comprises that PMOS input can receive differential signal Vip, the Vin of the common-mode voltage of a fixed voltage scope to M3, M4, and convert thereof into current signal, and one NMOS input can receive differential signal Vip, the Vin of the common-mode voltage of a fixed voltage scope to M9, M10, and convert thereof into current signal, wherein the PMOS input has the nonoverlapping effect of part to M3, M4 and NMOS input to the common-mode voltage range of receiving of M9, M10.
One NMOS current mirroring circuit M5, M14 connect PMOSM3 received current signal and flow to PMOSM8 again, and PMOS current mirroring circuit M7, M13 connection NMOSM9 received current signal flows to NMOSM6 more in addition.Wherein NMOSM6 connection PMOSM4 and PMOSM13 are as being connected into diode load (diode-connectedload), and also the current signal lump of PMOSM4 and NMOSM9 generation can be got up is sent to output end vo n by NMOSM6 and the formed current mirror of NMOSM16; Under same situation, PMOSM8 gets up the current signal lump of NMOSM10 and PMOSM3 generation and is sent to output end vo n by PMOSM8 and the formed current mirror of PMOSM15.
The above-mentioned explanation that continues, in the present embodiment, current source has two, and one is PMOSM1 and the formed current source of M2, and its bias voltage is provided by NMOSM5 and M6; Another is NMOSM11 and the formed current source of M12, and its bias voltage is provided by PMOSM7 and M8.Last current source signal exports a buffer (not shown) of being made up of inverter (inverter) to by PMOSM15 and NMOSM16, by buffer current signal is pulled to full width output, as the input signal of next stage circuit, the next stage circuit can be the buffer that several reverser serial connections form.
NMOSM5 and M6 have passive as load with initiatively as the function of current mirror, wherein during the M6 passive state respectively as the first order load of PMOSM4 input and the second level load of NMOSM9 input; And a relative side, PMOSM7 and M8 have passive as load with initiatively as the function of current mirror, wherein during the M8 passive state respectively as the first order load of NMOSM10 input and the second level load of PMOSM3 input.
Therefore, the present invention discloses rail-to-rail (rail-to-rail) receiver with low voltage difference signal (LVDS) of self-bias voltage, one input stage circuit receives the differential signal of the common-mode voltage of a full width, and convert thereof into current signal, input stage circuit comprises that PMOS input can receive the differential signal of the common-mode voltage of a fixed voltage scope to M3 and M4, and one NMOS input can receive the differential signal of the common-mode voltage of a fixed voltage scope to M9 and M10, wherein the PMOS input has the nonoverlapping effect of part to the common-mode voltage range of receiving that M3 and M4 and NMOS import M9 and M10.For the too high or too low common-mode voltage signal (common-mode voltage) of input, can be received M9, M10 M3, M4 and NMOS input by the PMOS input respectively, common mode differential signal that so can the sensing full width, can the lower or higher signal of complete reception, rail-to-rail receiver signal receiving ability is increased.
One current source circuit connects input stage circuit, comprises that a pair of PMOS current source circuit M1 and M2 provide the current source of PMOS input to M3 and M4, provides the current source of NMOS input to M9 and M10 with a pair of NMOS current source circuit M11 and M12.One bias circuit connects input stage circuit and current source circuit, comprise that a pair of NMOS bias circuit M5 and M6 provide the bias voltage signal of PMOS current source circuit M1 and M2, provide the bias voltage signal of NMOS current source circuit M11 and M12 with a pair of PMOS bias circuit M7 and M8.
One output-stage circuit comprises that a NMOS output precision M16 connects PMOSM13 and is connected NMOSM14 and the formed current mirror of NMOS bias circuit M5 with a PMOS output precision M15 with the formed current mirror of PMOS bias circuit M7, PMOS output precision M15 and NMOS output precision M16 are serially connected, and connect an output end vo n at last and export voltage signal to a buffer.
Above-mentioned current mirror M5 electrical couplings current mirror M6, current mirror M7 electrical couplings current mirror M8, and current mirror M6 and current mirror M8 are coupled to a Coupling point and export an output voltage signal Von, and have a buffer (not shown) to receive output voltage signal Von, and produce an amplification voltage signal.
In addition, the low voltage difference signal is divided into two input voltage signals, low voltage difference signal receiver of the present invention comprises that also a fail-safe circuit connects current mirroring circuit 30,40, when the absolute value of two input voltage signal differences during greater than a predetermined value, the fail-safe circuit is changed another predeterminated voltage value with the output voltage signal by original predeterminated voltage value.In addition, when the absolute value of two input voltage signal differences during less than predetermined value, it is original predeterminated voltage value that the fail-safe circuit is kept the output voltage signal.
See also fail-safe (failsafe) the circuit connection diagram that Fig. 3 A and Fig. 3 B are depicted as the receiver of one embodiment of the invention low voltage difference signal.Contact V1, V2, V3, V4 and the Von of the V1 of the V2 of Fig. 3 A, V3, V4 and Von and Fig. 3 B, V2, V4 and Von connection layout 2, provide fixing current source by current source Mn and Mp, and its current value size is determined by required bucking voltage (offset voltage).
The fail-safe circuit comprises: an input amplifying circuit 50 receives bias voltage signal and the output voltage signal Von that bias point V2 produces, amplify signal to produce one, Current Control assembly Mn1, the drain electrode end of Mn2 (drain) respectively with M7, the gate terminal of M8 (gate) links to each other, and the gate terminal of M21 (gate) links to each other with the gate terminal (gate) of M16, and the gate terminal of M22 (gate) links to each other with drain electrode end (drain) Von of M16, so make Current Control assembly Mn1, Mn2 optionally produces two Control current to bias point V3 and bias point V4 according to operating current and amplification signal.In addition, a current source NMOSMn provides input amplifying circuit 50 1 operating currents.
One input amplifying circuit 60 receives bias voltage signal and the output voltage signal Von that bias point V4 produces, amplify signal to produce one, the drain electrode end (drain) of Current Control assembly Mp1, Mp2 links to each other with the gate terminal (gate) of M5, M6 respectively, and the gate terminal of M25 (gate) links to each other with the gate terminal (gate) of M15, and the gate terminal of M26 (gate) links to each other with drain electrode end (drain) Von of M15, so make Current Control assembly Mp1, Mp2 according to operating current and amplification signal, optionally produce two Control current to bias point V1 and bias point V2.In addition, a current source PMOS Mp provides input amplifying circuit 60 1 operating currents.
According to above-mentioned, the differential voltage signal V2 and the Von of receiver end output are inputed to M21 and M22, input to M25 and M26 with V4 and Von, again respectively by other one-stage amplifier M23 and M24, M27 and the amplification of M28 circuit, its output voltage is controlled Mn1 and Mn2 respectively, and the conducting of Mp1 and Mp2 whether.
Please consult Fig. 4 simultaneously and concern schematic diagram for input voltage difference and output voltage according to one embodiment of the invention low voltage difference signal receiver.In the foregoing circuit, as Vip during greater than bucking voltage of Vin (offset voltage) Voffset, the electric current of the M6 that flows through, M7 makes that respectively greater than the electric current of M5, M8 V2 can be greater than V4 greater than Von and Von; As V2 during greater than Von, Mn2 conducting, Mn1 can be closed, and the electric current of being flowed through by Mn can be through the Mn2 M8 that flows through, be increased to the electric current of M8 identical with the electric current of M7.In like manner, as Von during greater than V4, also the electric current of M5 can be increased to identical with the electric current of M6, this moment by current mirroring circuit M8 and M15, with M6 and M16, the feasible M15 that flows through is identical with the total current of M16.
As Vip during greater than bucking voltage of Vin+Voffset, and the M15 that flows through is identical with the total current of M16, just can with " Vip-Vin " and with bucking voltage of changing voltage displacement (offset voltage) of Von after just conversion; In another case, Vin is during greater than bucking voltage of Vip-Voffset, and the M15 that flows through is identical with the total current of M16, just can with " Vip-Vin " and with the bucking voltage of changing voltage displacement (offsetvoltage) of Von after just conversion.So, the conversion that is not stopped by Vip and Vin, and also and then conversion of bucking voltage except overcoming the interference that differential noise brings, can keep the integrality of receiver output work period (duty-cycle).
According to above-mentioned, the differential voltage that the present invention exports receiver respectively, amplify the switch of controlling the MOS assembly again with individual other amplifier, cause unwanted effect, and can not impact for the reflector output driving current of the other end simultaneously to overcome differential noise.
Comprehensively above-mentioned, the present invention utilizes the NMOS input to importing receiving an input voltage signal with PMOS simultaneously, can sense full width common-mode voltage signal (common-mode voltage), and utilize reverser to connect output, differential signal after amplifying is pulled to full width output, utilizes the circuit of receiver to be connected to form self-bias voltage again, save extra bias circuit, reduce Dian Liu Xiao Mao, reach the function of power saving; The connection of the circuit of receiver is with current mirror mode delivered current signal in addition, and Vdd operating voltage that must be bigger when avoiding utilizing string to change (Cascode) circuit is so make the present invention to operate under low-voltage.
The above only is preferred embodiment of the present invention, only is illustrative for the purpose of the present invention, and nonrestrictive.Those skilled in the art is understood, and can carry out many changes to it in the spirit and scope that claim of the present invention limited, revise, even equivalence, but all will fall within the scope of protection of the present invention.
Claims (12)
1, a kind of receiver of low voltage difference signal, it is characterized in that: it comprises:
One input stage circuit, it comprises one first differential signal loader and one second differential signal loader, the described first differential signal loader is in order to convert a low voltage difference signal to one first current signal, and the described second differential signal loader is in order to convert described low voltage difference signal to one second current signal;
The wherein said first differential signal loader receives one first predetermined voltage range of differential signal common-mode voltage and one second predetermined voltage range of described second differential signal loader reception differential signal common-mode voltage is only overlapped;
The wherein said first differential signal loader comprises one first pair pmos transistor, two source electrodes of described first pair pmos transistor are connected and two grids of described first pair pmos transistor receive described low voltage difference signal, and the described second differential signal loader comprises one first pair nmos transistor, and two source electrodes of described first pair nmos transistor are connected and two grids of described first pair nmos transistor receive described low voltage difference signal;
Wherein said low voltage difference signal comprises one first input voltage signal and one second input voltage signal;
One current source circuit connects described input stage circuit, and a plurality of bias voltage signals of described current source circuit foundation are to produce one group of required operating current of described input stage circuit;
One current mirroring circuit connects described current source circuit and described input stage circuit, described current mirroring circuit receives described first current signal and described second current signal producing an output voltage signal, and described current mirroring circuit also produces extremely described current source circuit of described a plurality of bias voltage signal according to described first current signal and described second current signal; Wherein, described current mirroring circuit comprises one first bias point and produces that one first bias voltage signal, one second bias point produce one second bias voltage signal, one the 3rd bias point produces one the 3rd bias voltage signal, produces one the 4th bias voltage signal with one the 4th bias point;
Also comprise a fail-safe circuit, it connects described current mirroring circuit, when the absolute value of the difference of described first input voltage signal and the described second input voltage signal during greater than a predetermined value, described fail-safe circuit is converted to one second predeterminated voltage value with described output voltage signal by one first original predeterminated voltage value;
Wherein said fail-safe circuit comprises: one the 3rd current source provides one the 3rd operating current; One the 3rd input amplifying circuit receives described second bias voltage signal and described output voltage signal, amplifies signal to produce one group the 3rd; One the 3rd Current Control assembly, described the 3rd Current Control assembly optionally produces one group of the 3rd Control current to described the 3rd bias point and described the 4th bias point according to described the 3rd operating current and described one group of the 3rd amplification signal; One the 4th current source provides one the 4th operating current; One the 4th input amplifying circuit receives described the 4th bias voltage signal and described output voltage signal, amplifies signal to produce one group the 4th; One the 4th Current Control assembly, described the 4th Current Control assembly optionally produces one group of the 4th Control current to described first bias point and described second bias point according to described the 4th operating current and described one group of the 4th amplification signal.
2, the receiver of low voltage difference signal according to claim 1 is characterized in that: described one group of operating current comprises one first group of operating current and one second group of operating current, and described current source circuit comprises:
One first current source circuit produces the required described first group of operating current of the described first differential signal loader; And
One second current source circuit produces the required described second group of operating current of the described second differential signal loader.
3, the receiver of low voltage difference signal according to claim 2, it is characterized in that: described first current source circuit comprises one second pair pmos transistor, two source electrodes of described second pair pmos transistor be connected to one first scheduled voltage and described second pair pmos transistor two the drain electrode be connected, and described second current source circuit comprises one second pair nmos transistor, two source electrodes of described second pair nmos transistor be connected to a low level and described second pair nmos transistor two the drain electrode join.
4, the receiver of low voltage difference signal according to claim 2 is characterized in that: described current mirroring circuit comprises:
One first current mirror group is between described first differential signal loader and the described second differential signal loader, and the described first current mirror group produces one first sum total current signal according to described first current signal and described second current signal; And
One second current mirror group is between described first differential signal loader and the described second differential signal loader, and the described second current mirror group produces one second sum total current signal according to described first current signal and described second current signal;
Wherein said current mirroring circuit produces described output voltage signal according to described first sum total current signal and the described second sum total current signal.
5, the receiver of low voltage difference signal according to claim 4, it is characterized in that: described first current signal comprises one the 3rd electron current signal and one the 4th electron current signal, described second current signal comprises one the 5th electron current signal and one the 6th electron current signal, and the described first current mirror group comprises:
One the 3rd current mirror receives described the 3rd electron current signal to produce one first reflection current signal; And
One the 4th current mirror connects described the 3rd current mirror, and described the 4th current mirror produces the described first sum total current signal according to described the 6th electron current signal and the described first reflection current signal.
6, the receiver of low voltage difference signal according to claim 5, it is characterized in that: described a plurality of bias voltage signals comprise one first bias voltage signal, one second bias voltage signal, one the 3rd bias voltage signal and one the 4th bias voltage signal, described the 3rd current mirror produces the described first bias voltage signal to described first current source circuit according to described the 3rd electron current signal, and described the 4th current mirror produces described the 4th bias voltage signal to described second current source circuit according to described the 6th electron current signal and the described first reflection current signal.
7, the receiver of low voltage difference signal according to claim 6 is characterized in that: the described second current mirror group comprises:
One the 5th current mirror receives described the 5th electron current signal to produce one second reflection current signal; And
One the 6th current mirror connects described the 5th current mirror, and described the 6th current mirror produces the described second sum total current signal according to described the 4th electron current signal and the described second reflection current signal.
8, the receiver of low voltage difference signal according to claim 7, it is characterized in that: described the 5th current mirror produces described the 3rd bias voltage signal to described second current source circuit according to described the 5th electron current signal, and described the 6th current mirror produces the described second bias voltage signal to described first current source circuit according to described the 4th electron current signal and the described second reflection current signal.
9, the receiver of low voltage difference signal according to claim 8, it is characterized in that: further described the 6th current mirror of described the 3rd current mirror electrical couplings, described the 5th current mirror of described the 4th current mirror electrical couplings, and described the 4th current mirror and described the 6th current mirror are coupled to a Coupling point.
10, the receiver of low voltage difference signal according to claim 9 is characterized in that: described output voltage signal is exported from described Coupling point.
11, the receiver of low voltage difference signal according to claim 1 is characterized in that: also comprise a buffer and produce an amplification voltage signal according to described output voltage signal.
12, the receiver of low voltage difference signal according to claim 1, it is characterized in that: when the absolute value of the difference of described first input voltage signal and the described second input voltage signal during less than described predetermined value, it is original described first predeterminated voltage value that described fail-safe circuit is kept described output voltage signal.
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| CNB200710163784XA CN100530966C (en) | 2007-11-01 | 2007-11-01 | Receiver of low voltage difference signal |
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| CNB200710163784XA CN100530966C (en) | 2007-11-01 | 2007-11-01 | Receiver of low voltage difference signal |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN101741373B (en) * | 2008-11-05 | 2014-04-30 | 中兴通讯股份有限公司 | Low voltage differential signal driver adaptive to various IO power supplies |
| JP6140573B2 (en) * | 2012-09-03 | 2017-05-31 | 株式会社メガチップス | Output buffer circuit |
| CN103780244B (en) * | 2012-10-17 | 2017-06-23 | 联咏科技股份有限公司 | Interface circuit |
| CN112394767B (en) * | 2020-11-26 | 2022-04-05 | 辽宁大学 | Low-voltage differential driver circuit with controllable substrate potential |
| CN113872588B (en) * | 2021-08-31 | 2024-05-28 | 北京时代民芯科技有限公司 | Cold backup and failure protection circuit suitable for LVDS receiving stage |
-
2007
- 2007-11-01 CN CNB200710163784XA patent/CN100530966C/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| CN101162901A (en) | 2008-04-16 |
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