CN109379064A - A kind of current comparator - Google Patents
A kind of current comparator Download PDFInfo
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- CN109379064A CN109379064A CN201811390578.7A CN201811390578A CN109379064A CN 109379064 A CN109379064 A CN 109379064A CN 201811390578 A CN201811390578 A CN 201811390578A CN 109379064 A CN109379064 A CN 109379064A
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/22—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral
- H03K5/24—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude
- H03K5/2472—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude using field effect transistors
- H03K5/2481—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude using field effect transistors with at least one differential stage
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Abstract
The present invention discloses a kind of current comparator, including electric current makees poor grade, gain stage and output stage；It is common-source common-gate current mirror that electric current, which makees poor grade, and the metal-oxide-semiconductor that current input terminal connection grid leak is shorted is capable of increasing so that the equivalent input impedance of current comparator reduces and compares speed；Gain stage introduces the common-source amplifier of the current source load with feedback, and current source bias voltage is generated by high threshold voltage pipe, can reduce biasing tube current, saves power consumption；Output stage introduces self biased differential amplifier, can be obviously improved the driving capability of output comparator.Show that the present invention has the characteristics that high-precision and high driving ability according to theory analysis and simulation result.
Description
Technical field
The present invention relates to IC design fields, and in particular to a kind of high-precision current comparator.
Background technique
With the fast development of integrated circuit technique, system on chip, which has been obtained, to be widely applied.In most of on pieces
There is the figure of current comparator in system, such as data converter chip, power supply chip, or even the digital isolator for industry
Chip etc..The speed of current comparator, precision, the indexs such as wow and flutter will affect the performance of whole system to a certain extent.
Traditional current comparator can use multistage gain grade to realize biggish gain and biggish driving capability
Or multistage inverter series structure, but plural serial stage can restrict the precision and speed of comparator.
Summary of the invention
In view of this, proposing that a kind of structure is simple, easily present invention solves the technical problem that be to overcome the shortcomings of existing methods
In realization, precision is high, the strong current comparator of driving capability.
To solve the above problems, the present invention is realized by following technological means:
A kind of current comparator, including electric current make poor grade, gain stage and output stage, including electric current make poor grade, gain stage and
Output stage, including positive current input terminal INP, power end VDD, positive reference current input terminal Iref+, reverse phase reference current are defeated
Enter to hold Iref-, negative-phase sequence curent input terminal INN, ground terminal GND, output end OUT；
Electric current makees poor grade, including two pairs of common-source common-gate current mirrors, for receiving positive input current and anti-phase input electric current,
Positive reference current and reverse phase reference current, and export positive input current and anti-phase input electric current makees difference；
Gain stage, including voltage dividing bias circuit, single-stage common-source amplifier, phase inverter make poor grade output for receiving electric current
Make spill current, and current signal is converted into voltage signal, the voltage of two-way reverse phase is exported after voltage signal is amplified
Signal；
Output stage, is used as self biased differential amplifier, and the differential configuration biased each other including two is defeated for reception gain grade
Two-way voltage signal out is compared, and the comparison result according to two voltage signals executes output.
Preferably, it includes NMOS tube N1~N4 and PMOS tube P1~P4 that the electric current, which makees poor grade,；Wherein, PMOS tube P1~
P4 constitutes PMOS common-source common-gate current mirror, and NMOS tube N1~N4 constitutes NMOS common-source common-gate current mirror；The source electrode of PMOS tube P1 with
The source electrode of PMOS tube P2 connects power supply vdd terminal simultaneously；The grid of PMOS tube P1 and drain electrode connect, and connect PMOS tube P2's simultaneously
Grid, the source electrode of PMOS tube P3 and positive current input terminal INP；The drain electrode of PMOS tube P2 is connect with the source electrode of PMOS tube P4；
The grid of PMOS tube P3 and drain electrode connect, and connect the grid of reverse phase reference current input terminal Iref- and PMOS tube P4 simultaneously；
The drain electrode of the drain electrode connection NMOS tube N4 of PMOS tube P4, this tie point make the output of poor grade as electric current；The grid of NMOS tube N3
It is connected with drain electrode, and connects the grid of positive reference current input terminal Iref+ and NMOS tube N4 simultaneously；The source electrode of NMOS tube N4 with
The drain electrode of NMOS tube N2 connects；The grid of NMOS tube N1 and drain electrode connect, and connect the source electrode of NMOS tube N3, NMOS tube N2 simultaneously
Grid and negative-phase sequence curent input terminal INN；The source electrode of NMOS tube N1 and the source electrode of NMOS tube N2 are all connected with ground terminal GND.
Preferably, the gain stage includes PMOS tube P5~P8 and NMOS tube N5~N8；Wherein, PMOS tube P6 and NMOS
Pipe N6 constitutes single-stage common-source amplifier, and PMOS tube P7 and NMOS tube N7 constitute voltage dividing bias circuit, PMOS tube P8 and NMOS tube N8
Constitute phase inverter；The drain electrode of PMOS tube P5, the source electrode of NMOS tube N6~N8 are all connected with ground terminal GND；The drain electrode of NMOS tube N5, PMOS
The source electrode of pipe P6~P8 is connected to power end VDD simultaneously；The source electrode of PMOS tube P5 and the source electrode of NMOS tube N5, the grid of NMOS tube N6
Pole connection, this tie point simultaneously connect the output that electric current makees poor grade；The grid of NMOS tube N5 is connect with the grid of PMOS tube P5, this company
Contact connects the tie point of the drain electrode of PMOS tube P6 and the drain electrode of NMOS tube N6, the grid of PMOS tube P8 and NMOS tube N8's simultaneously
The tie point of grid, this tie point export the first output as gain stage；The grid of the grid connection PMOS tube P7 of PMOS tube P6
Pole and drain electrode, the grid of NMOS tube N7 and drain electrode；The drain electrode of NMOS tube N8 is connect with the drain electrode of PMOS tube P8, this tie point conduct
Second output of gain stage.
Preferably, the output stage includes NMOS tube N9~N11 and PMOS tube P9~P11；Wherein, PMOS tube P9~
P11 constitutes a PMOS differential configuration, and NMOS tube N9~N11 constitutes NMOS differential structure；The source electrode and ground terminal GND of NMOS tube N9
Connection；The grid of NMOS tube N9 is connect with the grid of PMOS tube P9, the drain electrode of NMOS tube N10, the drain electrode of PMOS tube P10；NMOS
The drain electrode of pipe N9 is connect with the source electrode of the source electrode of NMOS tube N10, NMOS tube N11；The grid of NMOS tube N10 is with PMOS tube P10's
Grid connection, and the first output of gain stage is connected simultaneously；The grid of NMOS tube N11 is connect with the grid of PMOS tube P11, and same
When connection gain stage second output；The drain electrode of NMOS tube N11 is connect with the drain electrode of PMOS tube P11, and connects electric current ratio simultaneously
Compared with the output end OUT of device；The source electrode of PMOS tube P10 is connect with the drain electrode of the source electrode of PMOS tube P11, PMOS tube P9；PMOS tube P9
Source electrode connect power supply vdd terminal.
Preferably, the substrate of PMOS tube P1~P11 is all connected with power supply vdd terminal, and the substrate of N1~N11 of NMOS tube is all connected with
The ground end GND.
Preferably, PMOS tube P7 and NMOS tube N7 is the metal-oxide-semiconductor of normal voltage 5V, remaining PMOS tube and NMOS tube are
The metal-oxide-semiconductor of normal voltage 1.8V.
Compared with prior art, the present invention has a characteristic that
1, the positive current input terminal INP of current comparator connects drain electrode with negative-phase sequence curent input terminal INN, grid is shorted
Metal-oxide-semiconductor, electric current, which makees poor grade introducing common-source common-gate current mirror, keeps the equivalent input impedance of current comparator smaller, can increase electric current
The speed of comparator；
2, the common-source amplifier of the current source load with feedback is introduced in gain stage, and current source bias voltage is by high threshold
Threshold voltage pipe generates, and can reduce biasing tube current, saves power consumption；
3, output stage introduces self biased differential amplifier, can be obviously improved output driving ability.
The scheme that the present invention is mentioned, working principle and theory analysis are described in detail in a specific embodiment,
It has the beneficial effect that
(1) precision is higher, and circuit structure is simple；
(2) driving capability is larger.
Detailed description of the invention
Fig. 1 is the circuit diagram of current comparator proposed by the invention；
Fig. 2 is the precision simulation figure of current comparator proposed by the invention.
Specific embodiment
With reference to the accompanying drawings and examples, the technical schemes of the invention are described in detail:
A kind of current comparator, physical circuit is as shown in Figure 1, include that electric current makees poor grade, gain stage and output stage；Described
Current comparator ontology is made of PMOS tube P1~P11 and NMOS tube N1~N11；
Wherein, electric current makees poor grade, including NMOS tube N1~N4 and PMOS tube P1~P4；
Gain stage, including NMOS tube N5~N8 and PMOS tube P5~P8；
Output stage, including NMOS tube N9~N11 and PMOS tube P9~P11；
Each circuit forms connection relationship are as follows:
Wherein the source electrode of PMOS tube P1 is connected with the source electrode of PMOS tube P2 and connects power end VDD；The grid of PMOS tube P1
It is connected with drain electrode, and connects the grid of PMOS tube P2, the source electrode of PMOS tube P3 and positive current input terminal INP simultaneously；PMOS
The drain electrode of pipe P2 is connected with the source electrode of PMOS tube P4；The grid of PMOS tube P3 and drain electrode connect, and connect reverse phase benchmark electricity simultaneously
Flow the grid of input terminal Iref- and PMOS tube P4；The drain electrode of the drain electrode connection NMOS tube N4 of PMOS tube P4, this tie point is electric current
Spill current Iout is made in the output of output stage, output；The grid of NMOS tube N3 and drain electrode connect, and connect positive reference current simultaneously
The grid of input terminal Iref+ and NMOS tube N4；The source electrode of NMOS tube N4 is connected with the drain electrode of NMOS tube N2；The grid of NMOS tube N1
It is connected with drain electrode, and connects the source electrode of NMOS tube N3, the grid of NMOS tube N2 and negative-phase sequence curent input terminal INN simultaneously；NMOS
The source electrode of pipe N1 and the source electrode of NMOS tube N2 are all connected with ground terminal GND；
The drain electrode of PMOS tube P5, the source electrode of NMOS tube N6~N8 are all connected with ground terminal GND；The grid of PMOS tube P5, NMOS tube
The grid of N5, the drain electrode of NMOS tube N6, the drain electrode of PMOS tube P6, PMOS tube P8 grid connected with the grid of NMOS tube N8, this
Connecting node is connection B point, B point and the first output as gain stage, and connect in output stage the grid of NMOS tube N10 and
The grid of PMOS tube P10；The drain electrode of NMOS tube N5 and the source electrode of PMOS tube P6~P8 are all connected with power end VDD；NMOS tube N5's
Source electrode connects the grid of the source electrode of PMOS tube P5, NMOS tube N6, this tie point is connection A point, and A point connects electric current and makees the defeated of poor grade
Out, it receives and makees difference output electric current Iout；The grid of PMOS tube P7 and drain electrode, the grid of NMOS tube N7 and drain electrode connect, and simultaneously
Connect the grid of PMOS tube P6；The drain electrode of NMOS tube N8 is connected with the drain electrode of PMOS tube P8, this tie point is connection C point, and C point is simultaneously
The second output as gain stage；
The source electrode of NMOS tube N9 is connect with ground terminal GND；The grid of NMOS tube N9, the grid of PMOS tube P9, NMOS tube N10
Drain electrode is connected with the drain electrode of PMOS tube P10, this tie point is connection D point；The drain electrode of NMOS tube N9, NMOS tube N10 source electrode with
The source electrode of NMOS tube N11 connects；The grid of NMOS tube N10 and the grid of PMOS tube P10, and connection B point, NMOS tube are connected simultaneously
The grid of N11 is connect with the grid of PMOS tube P11, and connects connection C point simultaneously；The drain electrode of NMOS tube N11 is with PMOS tube P11's
Drain electrode connection, and the output end OUT of current comparator is connected simultaneously；The source electrode of PMOS tube P10, PMOS tube P11 source electrode with
The drain electrode of PMOS tube P9 connects；The source electrode of PMOS tube P9 connects power end VDD；
It should be noted that the substrate of PMOS tube P1~P11 is all connected with power end VDD, the substrate of NMOS tube N1~N11 is equal
Connect ground terminal GND.
Wherein, PMOS tube P7 and NMOS tube N7 is the metal-oxide-semiconductor of normal voltage 5V, remaining PMOS tube and NMOS tube are standard
The metal-oxide-semiconductor of voltage 1.8V.
The operation principle of the present invention is that:
As shown in Figure 1, the course of work of the present invention, which can regard electric current as, makees poor grade, gain stage and output stage stage by stage to signal
It is handled:
Electric current makees poor grade: PMOS tube P1~P4 constitutes PMOS common-source common-gate current mirror, and NMOS tube N1~N4 constitutes NMOS tube
Common-source common-gate current mirror；Error compared to fundamental current mirror, the current mirror replica current is small, and precision is high.Reverse phase reference current
Input terminal Iref- and positive reference current input terminal Iref+ inputs two-way reference current, and the size of current of two inputs is equal, side
To opposite；The NMOS tube and PMOS tube phase that negative-phase sequence curent input terminal INN and positive current input terminal INP is shorted with grid leak respectively
Even so that current comparator it is equivalent input impedance it is smaller, be capable of increasing electric current and compare speed；According to current mirror basic function,
It can be concluded that electric current, which makees poor grade, exports electric current are as follows:
Iout=Inp-Inn
In above formula, Iout is that electric current makees poor grade output current value, and Inp is positive phase current input terminal INP input current value,
Inn is negative-phase sequence curent input terminal INN input current value；Output electric current Iout can pour into gain stage.
Gain stage: NMOS tube N7 and PMOS tube P7 be preferably grid leak be shorted normal voltage 5V metal-oxide-semiconductor, PMOS tube P7 with
NMOS tube N7 constitutes voltage dividing bias circuit in structure, can provide bias voltage for PMOS tube P6 work, and with it is normal
Rule metal-oxide-semiconductor is compared, and the type selecting of NMOS tube N7 and PMOS tube P7 can reduce the electric current of biasing circuit, reduces power consumption；NMOS tube N6
Single-stage common-source amplifier is constituted with PMOS tube P6, wherein NMOS tube N6 is amplifier tube, and PMOS tube P6 is current source load, is compared
It is worked in traditional circuit in the metal-oxide-semiconductor load of linear zone, the connection structure of PMOS tube P6 and NMOS tube N6, which can provide, more to increase
Benefit；NMOS tube N5 and PMOS tube P5 is metal-oxide-semiconductor negative-feedback, for increasing gain；PMOS tube P8 and NMOS tube N8 constitutes phase inverter,
For reverse phase processing；
Electric current makees poor grade output and makees spill current Iout, and current signal handles through gain stage and obtains voltage signal, B point in A point
Gain voltage signal is obtained, C point obtains reverse voltage signal；It is positive if electric current makees poor grade output electric current Iout, A point voltage meeting
It is raised, due to the effect of common-source amplifier (for inverting amplifier), B point voltage can be pulled low；Simultaneously as the work of phase inverter
With the voltage of C point can be raised；Opposite, it is negative if making poor grade output electric current Iout, A point voltage can be pulled low, B point electricity
Pressure can be raised, and the voltage of C point can be pulled low；The B point voltage and C point voltage of gain stage pour into output stage respectively；
Output stage: as a self biased differential amplifier, PMOS tube P9~P11 constitutes a PMOS differential configuration and NMOS tube
N9~N11 constitutes a NMOS differential structure, they are biased each other；PMOS tube P9 connects PMOS tube P10 with the grid of NMOS tube N9
With the drain electrode of NMOS tube N10, feedback loop is formed, it is adaptive to can be realized difference amplifier tail current；NMOS tube N9 and
PMOS tube P9 works in linear zone, can provide maximum output voltage swing；
Output stage distinguishes the voltage signal of the output of reception gain grade B point and the output of C point, when the raising of B point voltage, D point voltage
It can reduce, so that PMOS tube P9 pipe is connected, PMOS tube P9 drain current increases, and while B point boost in voltage, C point voltage is reduced,
So that PMOS tube P11 is connected, the drain current of PMOS tube P9 by the drain electrode of PMOS tube P11 be output to output end OUT be given to it is negative
Capacitor is carried, NMOS tube N9 is turned off at this time, no drain current；
Opposite, when B point voltage reduces, D point voltage can be increased, so that NMOS tube N9 is connected, NMOS tube N9 drain current
Increase, simultaneously C point voltage increases, so that NMOS tube N11 is connected, then the high current in output end OUT external load passes through
Cross NMOS tube N11 and NMOS tube N9 leakage；
The introducing of self biased differential amplifier greatly improves the driving capability of current comparator；The implementation of circuit
Are as follows: electric current makees poor grade output and makees spill current Iout, and gain stage response makees spill current Iout and exports B point voltage and C point voltage, defeated
Grade compares the output for realizing electric current comparison result according to the pressure drop that the two o'clock of gain stage exports out；Specifically, current comparator is just
Often work, when positive input current Inp is higher than anti-phase input electric current Inn, i.e. output makees spill current Iout and is positive, and rings through gain stage
It should export, output B point voltage is lower than C point voltage, then output stage exports low level in the output end OUT of current comparator；On the contrary
, when positive input current Inp is lower than anti-phase input electric current Inn, i.e. output makees spill current Iout and is negative, gain stage output, B point
Voltage is higher than C point voltage, then output end OUT exports high level.
It is designed and emulates using precision of the SMIC 0.18um CMOS technology to structure of the invention, Fig. 2 show this
Embodiment related electric current under 1.8V supply voltage compares the simulation waveform of precision, is positive input current Inp, anti-phase input
Electric current Inn and corresponding output end OUT voltage oscillogram, as seen from the figure, simulation result shows the essence of invented current comparator
Degree is less than 12nA；The simulation result illustrates the validity of the above measure.
In conclusion the present invention is compared with traditional current comparator, higher using precision, circuit structure is simple, simultaneously
With biggish driving capability.
The above is only the preferred embodiment of the present invention, those skilled in the art in the invention can also be to above-mentioned specific
Embodiment is changed and is modified.Therefore, the invention is not limited to specific control modes disclosed and described above, to this
Some modifications and changes of invention should also be as falling into the scope of the claims of the present invention.In addition, although this specification
In use some specific terms, these terms are merely for convenience of description, does not limit the present invention in any way.
Claims (6)
1. a kind of current comparator, it is characterised in that: defeated including the poor grade of electric current work, gain stage and output stage, including positive phase current
Enter to hold INP, power end VDD, positive reference current input terminal Iref+, reverse phase reference current input terminal Iref-, negative-phase sequence curent defeated
Enter to hold INN, ground terminal GND, output end OUT；
Electric current makees poor grade, including two common-source common-gate current mirrors, for receiving positive input current and anti-phase input electric current, positive
Reference current and reverse phase reference current, and export positive input current and anti-phase input electric current makees difference；
Gain stage, single-stage common-source amplifier, phase inverter including voltage dividing bias circuit, with current source load, for receiving electricity
Spill current is made in the poor grade output of stream work, and current signal is converted to voltage signal, exports two-way after voltage signal is amplified
The voltage signal of reverse phase；
Output stage is used as self biased differential amplifier, the differential configuration biased each other including two, for the output of reception gain grade
Two-way voltage signal is compared, and the comparison result according to two voltage signals executes output.
2. current comparator according to claim 1, it is characterised in that: the electric current make poor grade include NMOS tube N1~
N4 and PMOS tube P1~P4；Wherein, PMOS tube P1~P4 constitutes PMOS common-source common-gate current mirror, and NMOS tube N1~N4 constitutes NMOS
Common-source common-gate current mirror；The source electrode of PMOS tube P1 connect power end VDD with the source electrode of PMOS tube P2 simultaneously；The grid of PMOS tube P1
It is connected with drain electrode, and connects the grid of PMOS tube P2, the source electrode of PMOS tube P3 and positive current input terminal INP simultaneously；PMOS
The drain electrode of pipe P2 is connect with the source electrode of PMOS tube P4；The grid of PMOS tube P3 and drain electrode connect, and connect reverse phase benchmark electricity simultaneously
Flow the grid of input terminal Iref- and PMOS tube P4；The drain electrode of the drain electrode connection NMOS tube N4 of PMOS tube P4, this tie point is as electricity
Stream makees the output of poor grade；The grid of NMOS tube N3 and drain electrode connect, and connect simultaneously positive reference current input terminal Iref+ and
The grid of NMOS tube N4；The source electrode of NMOS tube N4 is connect with the drain electrode of NMOS tube N2；The grid of NMOS tube N1 and drain electrode connect, and
The source electrode of NMOS tube N3, the grid of NMOS tube N2 and negative-phase sequence curent input terminal INN are connected simultaneously；The source electrode of NMOS tube N1 and
The source electrode of NMOS tube N2 is all connected with ground terminal GND.
3. current comparator according to claim 1, it is characterised in that: the gain stage include PMOS tube P5~P8 and
NMOS tube N5~N8；Wherein, PMOS tube P6 and NMOS tube N6 constitutes single-stage common-source amplifier, and PMOS tube P7 and NMOS tube N7 are constituted
Voltage dividing bias circuit, PMOS tube P8 and NMOS tube N8 constitute phase inverter；The drain electrode of PMOS tube P5, the source electrode of NMOS tube N6~N8 are equal
Connect ground terminal GND；The drain electrode of NMOS tube N5, the source electrode of PMOS tube P6~P8 connect power end VDD simultaneously；The source electrode of PMOS tube P5
It is connect with the grid of the source electrode of NMOS tube N5, NMOS tube N6, this tie point connects the output that electric current makees poor grade；The grid of NMOS tube N5
Pole is connect with the grid of PMOS tube P5, this tie point connects the connection of the drain electrode of PMOS tube P6 and the drain electrode of NMOS tube N6 simultaneously
The tie point of the grid of point, the grid of PMOS tube P8 and NMOS tube N8, this tie point export the first output as gain stage；
The grid of the grid connection PMOS tube P7 of PMOS tube P6 and drain electrode, the grid of NMOS tube N7 and drain electrode；The drain electrode of NMOS tube N8 with
The drain electrode of PMOS tube P8 connects, second output of this tie point as gain stage.
4. current comparator according to claim 1, it is characterised in that: the output stage includes NMOS tube N9~N11
With PMOS tube P9~P11；Wherein, PMOS tube P9~P11 constitutes PMOS differential configuration, and NMOS tube N9~N11 constitutes NMOS differential
Structure；The source electrode of NMOS tube N9 is connect with ground terminal GND；The leakage of the grid, NMOS tube N10 of the grid and PMOS tube P9 of NMOS tube N9
The drain electrode connection of pole, PMOS tube P10；The drain electrode of NMOS tube N9 is connect with the source electrode of the source electrode of NMOS tube N10, NMOS tube N11；
The grid of NMOS tube N10 is connect with the grid of PMOS tube P10, and connects the first output of gain stage simultaneously；The grid of NMOS tube N11
Pole is connect with the grid of PMOS tube P11, and connects the second output of gain stage simultaneously；The drain electrode of NMOS tube N11 and PMOS tube P11
Drain electrode connection, and connect the output end OUT of current comparator simultaneously；The source electrode of the source electrode of PMOS tube P10 and PMOS tube P11,
The drain electrode of PMOS tube P9 connects；The source electrode of PMOS tube P9 connects power supply vdd terminal.
5. circuit comparator according to any one of claims 1 to 4, it is characterised in that: the substrate of PMOS tube P1~P11
It is all connected with power end VDD, the substrate of N1~N11 of NMOS tube is all connected with ground terminal GND.
6. current comparator according to claim 5, it is characterised in that: PMOS tube P7 and NMOS tube N7 is normal voltage 5V
Metal-oxide-semiconductor, remaining PMOS tube and NMOS tube are the metal-oxide-semiconductor of normal voltage 1.8V.
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| CN201811390578.7A CN109379064B (en) | 2018-11-21 | 2018-11-21 | Current comparator |
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| CN201811390578.7A CN109379064B (en) | 2018-11-21 | 2018-11-21 | Current comparator |
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| CN109861673A (en) * | 2019-03-14 | 2019-06-07 | 广州金升阳科技有限公司 | A kind of current comparator |
| CN110247645A (en) * | 2019-05-24 | 2019-09-17 | 广州金升阳科技有限公司 | A kind of voltage comparator |
| CN110247661A (en) * | 2019-06-26 | 2019-09-17 | 桂林电子科技大学 | A kind of fully differential high-speed low-power-consumption comparator |
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| CN111010155A (en) * | 2019-12-31 | 2020-04-14 | 北京轩宇空间科技有限公司 | Comparator and electronic device |
| CN112398476A (en) * | 2019-08-13 | 2021-02-23 | 天津大学青岛海洋技术研究院 | Low-power consumption comparator with low delay distortion characteristic |
| CN112835403A (en) * | 2019-11-22 | 2021-05-25 | 圣邦微电子（北京）股份有限公司 | Control circuit capable of reducing micro-power consumption comparator output stage transient current |
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| CN109861673B (en) * | 2019-03-14 | 2024-04-12 | 广州金升阳科技有限公司 | Current comparator |
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| CN112835403A (en) * | 2019-11-22 | 2021-05-25 | 圣邦微电子（北京）股份有限公司 | Control circuit capable of reducing micro-power consumption comparator output stage transient current |
| CN112835403B (en) * | 2019-11-22 | 2022-02-18 | 圣邦微电子（北京）股份有限公司 | Control circuit capable of reducing micro-power consumption comparator output stage transient current |
| CN111010155A (en) * | 2019-12-31 | 2020-04-14 | 北京轩宇空间科技有限公司 | Comparator and electronic device |
| CN111010155B (en) * | 2019-12-31 | 2023-10-24 | 北京轩宇空间科技有限公司 | Comparator and electronic device |
| WO2022121362A1 (en) * | 2020-12-07 | 2022-06-16 | 长鑫存储技术有限公司 | Cascode structure, output structure, amplifier and driving circuit |
| CN114665849B (en) * | 2022-02-23 | 2023-04-07 | 电子科技大学 | High-precision current comparator |
| CN114665849A (en) * | 2022-02-23 | 2022-06-24 | 电子科技大学 | High-precision current comparator |
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