CN109861673A - A kind of current comparator - Google Patents
A kind of current comparator Download PDFInfo
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- CN109861673A CN109861673A CN201910193238.3A CN201910193238A CN109861673A CN 109861673 A CN109861673 A CN 109861673A CN 201910193238 A CN201910193238 A CN 201910193238A CN 109861673 A CN109861673 A CN 109861673A
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- 239000004065 semiconductor Substances 0.000 claims abstract description 19
- 238000007493 shaping process Methods 0.000 claims abstract description 5
- 230000005611 electricity Effects 0.000 claims description 13
- 239000000758 substrate Substances 0.000 claims description 7
- 230000003321 amplification Effects 0.000 claims description 4
- 238000003199 nucleic acid amplification method Methods 0.000 claims description 4
- 238000010586 diagram Methods 0.000 description 7
- 238000000034 method Methods 0.000 description 4
- 238000004088 simulation Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- OUXCBPLFCPMLQZ-WOPPDYDQSA-N 4-amino-1-[(2r,3s,4s,5r)-4-hydroxy-5-(hydroxymethyl)-3-methyloxolan-2-yl]-5-iodopyrimidin-2-one Chemical compound C[C@H]1[C@H](O)[C@@H](CO)O[C@H]1N1C(=O)N=C(N)C(I)=C1 OUXCBPLFCPMLQZ-WOPPDYDQSA-N 0.000 description 1
- 238000004458 analytical method Methods 0.000 description 1
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- 238000011161 development Methods 0.000 description 1
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Abstract
The invention discloses a kind of current comparators, including the input stage, amplifying stage and the output stage that sequentially electrically connect and current input terminal, power end, ground terminal, output end and biased electrical pressure side；Input stage, single-stage common-source amplifier including metal-oxide-semiconductor voltage dividing bias circuit and with feedback, metal-oxide-semiconductor voltage dividing bias circuit is used to the current signal that current input terminal inputs being converted into voltage signal, exports after then providing certain voltage gain by the single-stage common-source amplifier with feedback；Amplifying stage, including single-stage differential amplifier and two concatenated phase inverters, single-stage differential amplifier are used to amplify the difference of the voltage signal of voltage signal and input stage output at current input terminal, export after being then further amplified by two concatenated phase inverters；Output stage, including Schmidt trigger, the voltage signal shaping for exporting to amplifying stage enhance circuit anti-interference ability.The present invention has the characteristics that simple structure, high-precision and high anti-jamming capacity.
Description
Technical field
The present invention relates to IC design fields, and in particular to a kind of current comparator.
Background technique
With the fast development of semiconductor integrated circuit technology, system on chip, which has been obtained, to be widely applied.Electric current ratio
Analog current signal can be converted into digital signal compared with device, there is the figure of current comparator in most of systems on chip；
The indexs such as speed, precision, imbalance and the delay of current comparator are all vital for whole system.
Traditional current comparator is as shown in Figure 1, include input stage and gain stage, input stage uses metal-oxide-semiconductor M1~M8 group
At current-mirror structure, the multi-stage cascade amplifier that gain stage is made of metal-oxide-semiconductor M9~M22 constitutes.It is illustrated in figure 2 conventional junction
The precision simulation figure of the current comparator of structure.
Since traditional comparator gain stage uses multi-stage cascade, and gain is not high enough, and anti-interference process is not done in output, because
This is larger in the presence of delay, precision is low and poor anti jamming capability series of problems.
Summary of the invention
In view of this, present invention solves the technical problem that be to overcome the shortcomings of existing methods, propose that a kind of structure is simple, easily
In realization, high-precision, jamproof current comparator.
To solve the above problems, the present invention is realized by following technological means:
A kind of current comparator, it is characterised in that: including input stage, amplifying stage and the output stage sequentially electrically connected, and
Current input terminal IIN, power end VDD, ground terminal GND, output end VOUT and biased electrical pressure side VB；
Input stage, the single-stage common-source amplifier including metal-oxide-semiconductor voltage dividing bias circuit and with feedback, metal-oxide-semiconductor bias pressure
Circuit is used to the current input terminal IIN current signal inputted being converted into voltage signal, then total by the single-stage with feedback
Source amplifier exports after providing certain voltage gain；
Amplifying stage, including single-stage differential amplifier and two concatenated phase inverters, single-stage differential amplifier are used for electric current
The difference amplification of the voltage signal of voltage signal and input stage output at input terminal IIN, then passes through two concatenated reverse phases
Device exports after being further amplified；
Output stage, including Schmidt trigger, the voltage signal shaping for exporting to amplifying stage enhance circuit anti-interference
Ability.
More preferably, current input terminal IIN is connected to the source electrode of metal-oxide-semiconductor in metal-oxide-semiconductor voltage dividing bias circuit.
A kind of specific embodiment as input stage, it is characterised in that: including NMOS tube N1~N3 and PMOS tube P1
~P3；Wherein, NMOS tube N1, NMOS tube N2, PMOS tube P1, PMOS tube P2 constitute the single-stage common-source amplifier with feedback,
PMOS tube P3, NMOS tube N3 constitute metal-oxide-semiconductor voltage dividing bias circuit；The drain electrode of NMOS tube N1 and the source of PMOS tube P2, PMOS tube P3
Pole electrically connects, and electrically connects power end VDD simultaneously；The source electrode of NMOS tube N1, the source electrode of PMOS tube P1, the grid of NMOS tube N2 are same
When be electrically coupled to current input terminal IIN；The drain electrode and PMOS tube of the grid of NMOS tube N1, the grid of PMOS tube P1, NMOS tube N2
The drain electrode of P2 electrically connects, output of this tie point as input stage；The grid of PMOS tube P3, drain electrode and NMOS tube N3 grid,
Drain electrode electrically connects, and electrically connects the grid of PMOS tube P2 simultaneously；The drain electrode of PMOS tube P1, NMOS tube N2~N3 source electrode Electricity Federation
It connects, and Electricity Federation ground terminal GND simultaneously.
A kind of specific embodiment as amplifying stage, it is characterised in that: including NMOS tube N4~N8, PMOS tube P4~
P7；Wherein NMOS tube N4~N6 and PMOS tube P4~P5 constitutes single-stage differential amplifier, and NMOS tube N7 and PMOS tube P6 constitute anti-
Phase device, NMOS tube N8 and PMOS tube P7 constitute phase inverter；The source electrode of PMOS tube P4~P7 electrically connects power end VDD；PMOS tube
Grid, drain electrode and the drain electrode of NMOS tube N4 of P4 electrically connects, and is electrically coupled to the grid of PMOS tube P5 simultaneously；The grid of NMOS tube N4
Pole and current input terminal IIN are electrically connected, the output of the grid of NMOS tube N5 and input stage electrically connects；The source electrode of NMOS tube N4,
The drain electrode of the source electrode and NMOS tube N6 of NMOS tube N5 electrically connects；The drain electrode of PMOS tube P5, the drain electrode of NMOS tube N5, PMOS tube P6
The grid of grid and NMOS tube N7 electrically connect；The grid of NMOS tube N6 is electrically connected with biased electrical pressure side VB；NMOS tube N6~N8's
The equal Electricity Federation ground terminal GND of source electrode；The drain electrode of PMOS tube P6, the drain electrode of NMOS tube N7, the grid of PMOS tube P7 and NMOS tube N8
Grid electrically connects；The drain electrode of PMOS tube P7 and the drain electrode of NMOS tube N8 electrically connect, output of this tie point as amplifying stage.
A kind of specific embodiment as output stage, it is characterised in that: including NMOS tube N9~N11, PMOS tube P8
~P10；PMOS tube P8, PMOS tube P9, NMOS tube N9, NMOS tube N10 grid electrically connect, and be electrically coupled to amplifying stage simultaneously
Output；The drain electrode of the source electrode and NMOS tube N11 of PMOS tube P8 electrically connects, and electrically connects power end VDD simultaneously；The leakage of PMOS tube P8
The source electrode of pole, the source electrode of PMOS tube P9 and PMOS tube P10 electrically connects；The drain electrode of PMOS tube P9, the drain electrode of NMOS tube N9, NMOS tube
The grid of N11 and the grid of PMOS tube P10 electrically connect, and electrically connect output end VOUT simultaneously；The source electrode of NMOS tube N9, NMOS tube
The drain electrode of N10, the source electrode of NMOS tube N11 electrically connect；The drain electrode of the source electrode and PMOS tube P10 of NMOS tube N10 electrically connects, and simultaneously
It is electrically coupled to ground terminal GND.
More preferably, the substrate of PMOS tube P1~P10 electrically connects power end VDD, and the substrate of N1~N11 of NMOS tube is electric
Couple ground terminal GND.
More preferably, the normal voltage of PMOS tube P3 and NMOS tube N3 is high compared with remaining PMOS tube and NMOS tube.
Compared with prior art, the present invention has a characteristic that
1, include common-source amplifier in input stage, comparator gain can be improved；
2, the common-source amplifier in input stage has feedback function, can increase gain, improves the precision of comparator；
3, the metal-oxide-semiconductor voltage dividing bias circuit in input stage can choose the higher metal-oxide-semiconductor of normal voltage, so as to reduce
Electric current saves power consumption；
4, input stage increases gain using differential amplifier, can be further improved comparator precision；
5, output stage uses Schmidt trigger, can enhance circuit anti-interference ability, carries out shaping to output signal.
The scheme that the present invention is mentioned, working principle and theory analysis are described in detail in a specific embodiment,
It has the beneficial effect that
(1) precision is high, and delay is small, and circuit structure is simple；
(2) strong antijamming capability.
Detailed description of the invention
Fig. 1 is the circuit diagram of the current comparator of traditional structure；
Fig. 2 is the precision simulation figure of the current comparator of traditional structure；
Fig. 3 is the functional schematic block diagram of circuit comparator of the invention；
Fig. 4 is the circuit diagram of the current comparator of the embodiment of the present invention；
Fig. 5 is the precision simulation figure of the current comparator of the embodiment of the present invention.
Specific embodiment
Fig. 3 show the functional schematic block diagram of circuit comparator of the invention, including sequentially electrically connect input stage, amplification
Grade and output stage and current input terminal IIN, power end VDD, ground terminal GND, output end VOUT and biased electrical pressure side VB.In order to
The objectives, technical solutions, and advantages of the present invention are more clearly understood, it is with reference to the accompanying drawings and embodiments, further to the present invention
It is described in detail.It should be appreciated that the specific embodiments described herein are merely illustrative of the present invention, it is not used to limit this hair
It is bright.
Fig. 4 is the circuit diagram of the current comparator of the embodiment of the present invention, and the current comparator ontology is by PMOS
Pipe P1~P10 and NMOS tube N1~N11 is constituted；
Wherein, input stage, including NMOS tube N1~N3 and PMOS tube P1~P3；
Amplifying stage, including NMOS tube N4~N8 and PMOS tube P4~P7；
Output stage, including NMOS tube N9~N11 and PMOS tube P8~P11；
Each circuit forms connection relationship are as follows:
N1, N2, P1, P2 constitute the single-stage common-source amplifier with feedback, and P3, N3 constitute metal-oxide-semiconductor voltage dividing bias circuit；N1
Drain electrode and the source electrode of P2, P3 electrically connect, and electrically connect power end VDD simultaneously；The source electrode of N1, the source electrode of P1, the grid of N2 are same
When be electrically coupled to current input terminal IIN, be electrically coupled to the grid of amplifying stage N4；The grid of N1, the grid of P1, the drain electrode of N2 and P2
Drain electrode electrically connect, output of this tie point as input stage is electrically coupled to the grid of amplifying stage N5；The grid of P3, drain electrode and
The grid of N3, drain electrode electrically connect, and electrically connect the grid of P2 simultaneously；The drain electrode of P1, the source electrode of N2~N3 electrically connect, and electric simultaneously
Couple ground terminal GND.
NMOS tube N4~N6 and PMOS tube P4~P5 constitutes single-stage differential amplifier, and NMOS tube N7 and PMOS tube P6 constitute anti-
Phase device, NMOS tube N8 and PMOS tube P7 constitute phase inverter；The source electrode of P4~P7 electrically connects power end VDD；The grid of P4, drain electrode
Drain electrode with N4 electrically connects, and is electrically coupled to the grid of P5 simultaneously；The grid and current input terminal IIN of N4 electrically connect, the grid of N5
The output of pole and input stage electrically connects；The drain electrode of the source electrode of N4, the source electrode of N5 and N6 electrically connects；The drain electrode of P5, the drain electrode of N5, P6
Grid and the grid of N7 electrically connect；The grid of N6 is electrically connected with biased electrical pressure side VB；The equal Electricity Federation ground terminal of the source electrode of N6~N8
GND；The drain electrode of P6, the drain electrode of N7, the grid of P7 and N8 grid electrically connect；The drain electrode of P7 and the drain electrode of N8 electrically connect, this company
Output of the contact as amplifying stage, is connected to the grid of output stage P8, P9, N9 and N10.
Entire output stage is sluggish flip-flop circuit structure (a kind of for the device of schmidt trigger)；The grid of P8, P9, N9, N10
Pole electrically connects, and is electrically coupled to the drain electrode of amplifying stage P7, N8；The drain electrode of the source electrode and N11 of P8 electrically connects, and electrically connects electricity simultaneously
Source VDD；The source electrode of the drain electrode of P8, the source electrode of P9 and P10 electrically connects；The drain electrode of P9, the drain electrode of N9, the grid of N11 and P10
Grid electrically connects, and electrically connects output end VOUT simultaneously；The drain electrode of source electrode, N10 of N9, the source electrode of N11 electrically connect；The source of N10
The drain electrode of pole and P10 electrically connects, and is electrically coupled to ground terminal GND simultaneously.
The present embodiment is electrically connected the substrate of PMOS tube P1~P10 using the general connection method of substrate in integrated circuit
Power end VDD, the equal Electricity Federation ground terminal GND of the substrate of N1~N11 of NMOS tube.
In order to reduce biasing circuit power consumption, the normal voltage of the PMOS tube P3 and NMOS tube N3 of the present embodiment are compared with remaining
PMOS tube and NMOS tube are high.
The working principle of the present embodiment are as follows:
As shown in figure 4, the present embodiment course of work can regard as input stage, amplifying stage and output stage stage by stage to signal into
Row processing:
Input stage: N2 and P2 constitutes common-source amplifier, can improve comparator gain；N1 and P1 is the anti-of common-source amplifier
Feedback, can increase gain, improve the precision of comparator；P3 and N3 is the higher metal-oxide-semiconductor of normal voltage, and grid leak, which is shorted, constitutes resistance
Bleeder circuit provides bias voltage to P2, and power consumption is lower；Since current input terminal IIN is connected to the source electrode of N1 and P1, because
This input impedance is lower, can reduce delay time；If input current is positive, input terminal voltage be will increase, due to common source
The effect of amplifier, A point voltage can reduce；Opposite, if input current is negative, input terminal voltage can be reduced, A point voltage
It will increase.
Amplifying stage: N4~N6 and P4~P5 constitutes single-stage differential amplifier, and P6 and N7 constitute phase inverter, and P7 and N8 constitute anti-
Phase device；If current input terminal IIN voltage increases, A point voltage can be reduced, then due to the effect of differential amplifier, B point voltage meeting
Increase, C point voltage will increase close to VDD current potential after two-stage phase inverter；Opposite, if input current is negative, electricity
Flowing input terminal IIN voltage reduces, and A point voltage will increase, and B point voltage can reduce, and C point voltage can reduce after two-stage phase inverter
To close to GND current potential；Differential amplifier is capable of increasing circuit gain, improves the precision of comparator.
Output stage: being made of PMOS tube P8~P10 and NMOS tube N9~N11, and output stage integrated circuit is a sluggish touching
Device is sent out, the anti-interference ability of circuit can be enhanced, shaping is carried out to signal；If C point current potential is high level, low electricity is exported
It is flat；Opposite, if C point current potential is low level, export high level.
It is designed and emulates using precision of the SMIC 0.18um CMOS technology to the current comparator of the present embodiment, scheme
5 show gained analogous diagram, include current input terminal IIN current waveform figure and output end VOUT voltage oscillogram, emulation in figure
The result shows that the precision of current comparator about 5nA；And analogous diagram shown in Fig. 2 shows the current comparator precision of traditional structure about
32nA；The simulation result illustrates that the above measure improves the validity of current comparator precision.
The above is only the preferred embodiment of the present invention, it is noted that above-mentioned preferred embodiment is not construed as pair
Limitation of the invention, for those skilled in the art, without departing from the spirit and scope of the present invention, also
Several equivalent replacements, improvements and modifications can be made, these equivalent replacements, improvements and modifications also should be regarded as protection model of the invention
It encloses, is no longer repeated here with embodiment, protection scope of the present invention should be defined by the scope defined by the claims..
In addition, all relationships such as " electrically connecting " and " connection " being related in patent application document, not singly refer to structure
Part directly connects, and referring to can be according to specific implementation situation, and by adding or reducing couple auxiliary, Lai Zucheng more preferably couples knot
Structure, the place for being clearly intended merely to emphasize this meaning with the place of " electrically connecting ", but use " connection " being not precluded etc. in the present invention
Also has such meaning.
Claims (7)
1. a kind of current comparator, it is characterised in that: including input stage, amplifying stage and the output stage sequentially electrically connected, Yi Ji electricity
Flow input terminal IIN, power end VDD, ground terminal GND, output end VOUT and biased electrical pressure side VB；
Input stage, the single-stage common-source amplifier including metal-oxide-semiconductor voltage dividing bias circuit and with feedback, metal-oxide-semiconductor voltage dividing bias circuit
Current signal for inputting current input terminal IIN is converted into voltage signal, is then put by the single-stage common source with feedback
Big device exports after providing certain voltage gain；
Amplifying stage, including single-stage differential amplifier and two concatenated phase inverters, single-stage differential amplifier is for inputting electric current
The difference amplification for holding the voltage signal at the place IIN and the voltage signal of input stage output, then pass through two concatenated phase inverters into
It is exported after the amplification of one step；
Output stage, including Schmidt trigger, the voltage signal shaping for exporting to amplifying stage enhance circuit anti-interference energy
Power.
2. current comparator according to claim 1, it is characterised in that: it is inclined that current input terminal IIN is connected to metal-oxide-semiconductor partial pressure
The source electrode of metal-oxide-semiconductor in circuits.
3. current comparator according to claim 1, it is characterised in that: the input stage include NMOS tube N1~N3 and
PMOS tube P1~P3；Wherein, NMOS tube N1, NMOS tube N2, PMOS tube P1, PMOS tube P2 constitute the single-stage common source with feedback and put
Big device, PMOS tube P3, NMOS tube N3 constitute metal-oxide-semiconductor voltage dividing bias circuit；The drain electrode of NMOS tube N1 and PMOS tube P2, PMOS tube P3
Source electrode electrically connect, and electrically connect power end VDD simultaneously；The source electrode of NMOS tube N1, the source electrode of PMOS tube P1, NMOS tube N2 grid
Pole is electrically coupled to current input terminal IIN simultaneously；The grid of NMOS tube N1, the grid of PMOS tube P1, NMOS tube N2 drain electrode and
The drain electrode of PMOS tube P2 electrically connects, output of this tie point as input stage；The grid of PMOS tube P3, drain electrode and NMOS tube N3
Grid, drain electrode electrically connect, and electrically connect the grid of PMOS tube P2 simultaneously；The drain electrode of PMOS tube P1, NMOS tube N2~N3 source electrode
It electrically connects, and Electricity Federation ground terminal GND simultaneously.
4. current comparator according to claim 1, it is characterised in that: the amplifying stage includes NMOS tube N4~N8,
PMOS tube P4~P7；Wherein NMOS tube N4~N6 and PMOS tube P4~P5 constitutes single-stage differential amplifier, NMOS tube N7 and PMOS
Pipe P6 constitutes phase inverter, and NMOS tube N8 and PMOS tube P7 constitute phase inverter；The source electrode of PMOS tube P4~P7 electrically connects power end
VDD；Grid, drain electrode and the drain electrode of NMOS tube N4 of PMOS tube P4 electrically connects, and is electrically coupled to the grid of PMOS tube P5 simultaneously；
The grid and current input terminal IIN of NMOS tube N4 electrically connect, the output of the grid of NMOS tube N5 and input stage electrically connects；NMOS tube
The drain electrode of the source electrode, the source electrode and NMOS tube N6 of NMOS tube N5 of N4 electrically connects；The drain electrode of PMOS tube P5, the drain electrode of NMOS tube N5,
The grid of PMOS tube P6 and the grid of NMOS tube N7 electrically connect；The grid of NMOS tube N6 is electrically connected with biased electrical pressure side VB；NMOS
The equal Electricity Federation ground terminal GND of the source electrode of pipe N6~N8；The drain electrode of PMOS tube P6, the drain electrode of NMOS tube N7, PMOS tube P7 grid and
The grid of NMOS tube N8 electrically connects；The drain electrode of PMOS tube P7 and the drain electrode of NMOS tube N8 electrically connect, this tie point is as amplifying stage
Output.
5. current comparator according to claim 1, it is characterised in that: the output stage includes NMOS tube N9~N11,
PMOS tube P8~P10；PMOS tube P8, PMOS tube P9, NMOS tube N9, NMOS tube N10 grid electrically connect, and be electrically coupled to simultaneously
The output of amplifying stage；The drain electrode of the source electrode and NMOS tube N11 of PMOS tube P8 electrically connects, and electrically connects power end VDD simultaneously；PMOS
The source electrode of the drain electrode of pipe P8, the source electrode of PMOS tube P9 and PMOS tube P10 electrically connects；The drain electrode of PMOS tube P9, the leakage of NMOS tube N9
The grid of pole, the grid of NMOS tube N11 and PMOS tube P10 electrically connects, and electrically connects output end VOUT simultaneously；The source of NMOS tube N9
Pole, the drain electrode of NMOS tube N10, NMOS tube N11 source electrode electrically connect；The source electrode of NMOS tube N10 and the drain electrode Electricity Federation of PMOS tube P10
It connects, and is electrically coupled to ground terminal GND simultaneously.
6. according to claim 1 to circuit comparator described in 5 any one, it is characterised in that: the substrate of PMOS tube P1~P10
Electrically connect power end VDD, the equal Electricity Federation ground terminal GND of the substrate of N1~N11 of NMOS tube.
7. according to claim 1 to current comparator described in 5 any one, it is characterised in that: PMOS tube P3 and NMOS tube N3
Normal voltage it is high compared with remaining PMOS tube and NMOS tube.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910193238.3A CN109861673B (en) | 2019-03-14 | 2019-03-14 | Current comparator |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910193238.3A CN109861673B (en) | 2019-03-14 | 2019-03-14 | Current comparator |
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| Publication Number | Publication Date |
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| CN109861673A true CN109861673A (en) | 2019-06-07 |
| CN109861673B CN109861673B (en) | 2024-04-12 |
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| CN113241105A (en) * | 2021-05-19 | 2021-08-10 | 北京大学 | Self-adaptive auxiliary strength circuit |
| CN113965086A (en) * | 2021-10-21 | 2022-01-21 | 中国电子科技集团公司第二十四研究所 | Multi-input current type PWM comparator circuit |
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| CN113965086B (en) * | 2021-10-21 | 2023-09-05 | 中国电子科技集团公司第二十四研究所 | Multi-input current type PWM comparator circuit |
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| Publication number | Publication date |
|---|---|
| CN109861673B (en) | 2024-04-12 |
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