CN103414438A - Error amplifier circuit - Google Patents
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Abstract
The invention belongs to the technical field of electronics, and relates to an integrated circuit design technology, in particular to a novel current injection/pulling error amplifier circuit. The error amplifier circuit comprises a first transconductance amplifier, a second transconductance amplifier, a first image current source, a second image current source and a first capacitor C1, wherein the input end of the first transconductance amplifier is a first input end Vref of the error amplifier circuit, the output end of the first transconductance amplifier is connected with the first image current source, the input end of the second transconductance amplifier is a second input end Vin of the error amplifier circuit, the output end of the second transconductance amplifier is connected with the second image current source, and the output end of the first image current source and the output end of the second image current source are connected with one end of the first capacitor C1 to serve as an output end Vea of the error amplifier circuit. The error amplifier circuit has the advantages of being capable of adjusting the output voltage, improving the response speed and response accuracy of a system and improving the stability of the system, and is particularly suitable for an error amplifier.
Description
Technical Field
The invention relates to the integrated circuit technology, in particular to a novel current-pouring/pulling error amplifier circuit.
Background
The error amplifier is always the core circuit of the converter in the switching power supply, and has important influence on the fast, accurate and stable operation of the system.
As shown in fig. 1, the conventional error amplifier includes bias PMOS transistors M6 and M7, input PMOS transistors M1 and M2, and NMOS transistors M3, M4 and M5; the PMOS transistor M1 and the source electrode of the M2 are connected to form a differential pair and connected to the source electrode of the M6 transistor, and the M6 transistor provides tail current for the operational amplifier; the gates of the PMOS transistors M1 and M2 are respectively used as the non-inverting input end V of the error amplifierin1And an inverting input terminal Vin2(ii) a The gates of the NMOS tubes M3 and M4 are connected to form a current mirror structure; the grid of the NMOS transistor M5 is connected with the drain terminal of the M1 transistor, the drain terminal of the M5 transistor is connected with the drain terminal of the PMOS transistor M7 to be used as the output terminal of the error amplifier, and the output voltage V isout；
The traditional error amplifier is designed into a voltage type, so that high gain of a loop is ensured, enough phase margin can be obtained to stabilize a system, but the output current of the amplifier is small, transient response is slow, and the design of a compensation network is complex. Therefore, designing a fast transient response and high precision error amplifier becomes a hot spot of current research.
The invention designs a transconductance type current input/output error amplifier which is novel in structure, high in precision and high in performance, can sample small voltage and output large current, and realizes quick transient response of a system. The input stage adopts a high-precision transconductance type amplifying circuit, and the dominant pole is close to the origin, so that the gain of the amplifier is improved. The output stage uses a current source and a current sink to respectively sink/pull current into/out of the capacitor C1.
Disclosure of Invention
The invention provides an error amplifier circuit aiming at solving the technical problem of the traditional error amplifier.
The technical scheme adopted by the invention for solving the technical problems is as follows: an error amplifier circuit is characterized by comprising a first transconductance amplifier, a second transconductance amplifier, a first mirror current, a second mirror current and a first capacitor C1, wherein the input end of the first transconductance amplifier is a first input end Vref of the error amplifier circuit, the output end of the first mirror current is connected with the first mirror current, the input end of the second transconductance amplifier is a second input end Vin of the error amplifier circuit, the output end of the second mirror current is connected with the second mirror current, the output end of the first mirror current and the output end of the second mirror current are connected with one end of a first capacitor C1 to serve as an output end Vea of the error amplifier circuit, and the other end of the first capacitor C1 is grounded.
Specifically, the first transconductance amplifier comprises a first operational amplifier AMP1, a second capacitor C2, a first resistor R1 and a first NMOS transistor N1, the second transconductance amplifier comprises a second operational amplifier AMP2, a third operational amplifier AMP3, a third capacitor C3, a second resistor R2, a third resistor R3, a fourth resistor R4 and a second NMOS transistor N2, the first mirror current comprises a first PMOS transistor P1, a second PMOS transistor P2, a third PMOS transistor P3 and a fourth PMOS transistor P4, and the second mirror current comprises a third NMOS transistor N3, a fourth NMOS transistor N4, a fifth NMOS transistor N5 and a sixth NMOS transistor N6; wherein,
the same-direction input end of the first operational amplifier AMP1 is a first input end Vref of the error amplifier circuit, the reverse-direction input end is connected with one end of a first resistor R1 and the source electrode of a first NMOS transistor N1, and the output end is connected with one end of a second capacitor C2 and the grid electrode of the first NMOS transistor N1;
the same-direction input end of the second operational amplifier AMP2 is a second input end Vin of the error amplifier circuit, the reverse-direction input end is connected with one end of a fourth resistor R4 and the source electrode of the second NMOS transistor N2, and the output end is connected with one end of a third capacitor C3 and the grid electrode of the second NMOS transistor N2;
the drain electrode of the second NMOS transistor N2 and one end of the second resistor R2 are connected with the inverting input end of the third operational amplifier AMP3, one end of the third resistor R3 and the drain electrode of the third NMOS transistor N3 are connected with the homonymous input end of the third operational amplifier AMP3, and the output end of the third operational amplifier AMP3 is connected with the gate electrode of the third NMOS transistor N3 and the gate electrode of the fourth NMOS transistor N4;
the grid and the drain of a first PMOS tube P1 are connected with the drain of a first NMOS tube N1 and the grid of a second PMOS tube P2, the source is connected with the drain of a third PMOS tube P3, the grid and the drain of the third PMOS tube P3 and the grid and the drain of a fourth PMOS tube P4 are connected with the source of a second PMOS tube P2;
the drain electrode of the second PMOS tube P2, the source electrode of the fourth NMOS tube N4 and one end of the first capacitor C1 are connected to serve as the output end Vea of the error amplifier circuit;
the source electrode of the third NMOS transistor N3 is connected with the drain electrode of the fifth NMOS transistor N5, the source electrode of the fourth NMOS transistor N4, the grid electrode of the fifth NMOS transistor N5 and the grid electrode and the drain electrode of the sixth NMOS transistor N6 are connected;
the source electrode of the third PMOS tube P3, the source electrode of the fourth PMOS tube P4, the other end of the second resistor R2, the other end of the third resistor R3 and the substrates of all the PMOS tubes are connected with a power supply VDD;
the other end of the first resistor R1, the other end of the second capacitor C2, the other end of the third capacitor C3, the other end of the fourth resistor R4, the source of the fifth NMOS transistor N5, the source of the sixth NMOS transistor N6 and the substrates of all the NMOS transistors are grounded.
Specifically, the first operational amplifier AMP1 includes a fifth PMOS transistor P5, a sixth PMOS transistor P6, a seventh PMOS transistor P7, an eighth PMOS transistor P8, a ninth PMOS transistor P9, a tenth PMOS transistor P10, an eleventh PMOS transistor P11, a twelfth PMOS transistor P12, a thirteenth PMOS transistor P13, a fourteenth PMOS transistor P14, a seventh NMOS transistor N7, an eighth NMOS transistor N8, a ninth NMOS transistor N9, a tenth NMOS transistor N10, a fifth resistor R5, and a first bias current source Ibias 1; wherein,
the grid electrode of the fifth PMOS pipe P5 is connected with the same-direction input end of the first operational amplifier AMP1, the drain electrode of the fifth PMOS pipe P5 is connected with the source electrode of the seventh NMOS pipe N7 and the drain electrode of the eighth NMOS pipe N8, the grid electrode of the sixth PMOS pipe P6 is connected with the reverse-direction input end of the operational amplifier AMP, and the drain electrode of the sixth PMOS pipe P6 is connected with the source electrode of the ninth NMOS pipe N9 and the drain electrode of the tenth NMOS pipe N10;
the drain electrode of the seventh NMOS transistor N7 is connected with one end of a fifth resistor R5, the gate electrode of an eighth NMOS transistor N8 and the gate electrode of a ninth NMOS transistor N9, and the other end of the fifth resistor R5 is connected with the gate electrode of a seventh NMOS transistor N7, the gate electrode of an eighth NMOS transistor N8 and the drain electrode of a seventh PMOS transistor P7;
the grid electrode of the seventh PMOS tube P7, the grid electrode of the eighth PMOS tube P8, the grid electrode of the fourteenth PMOS tube P14, the grid electrode and the drain electrode of the twelfth PMOS tube P12 and the anode of the first bias current source Ibias1 are connected, the source electrode of the twelfth PMOS tube P12 is connected with the drain electrode and the grid electrode of the eleventh PMOS tube P11, the grid electrode of the thirteenth PMOS tube P13, the grid electrode of the ninth PMOS tube P9 and the grid electrode of the tenth PMOS tube P10, the drain electrode of the thirteenth PMOS tube P13 is connected with the source electrode of the fourteenth PMOS tube P14, and the drain electrode of the fourteenth PMOS tube P14 is connected with the source electrode of the fifth PMOS tube P5 and the source electrode of the sixth PMOS tube P6;
the source electrode of the seventh PMOS tube P7 is connected with the drain electrode of the ninth PMOS tube P9, and the source electrode of the eighth PMOS tube P8 is connected with the drain electrode of the tenth PMOS tube P10;
the drain electrode of the eighth PMOS transistor P8 and the source electrode of the tenth NMOS transistor N10 are connected as the output end of the first operational amplifier AMP 1;
the source electrode of the ninth PMOS tube P9, the source electrode of the tenth PMOS tube P10, the source electrode of the eleventh PMOS tube P11, the source electrode of the thirteenth PMOS tube P13 and the substrates of all the PMOS tubes are connected with a power supply VDD;
the cathode of the first bias current source Ibias1, the source of the eighth NMOS transistor N8, the source of the ninth NMOS transistor N9, and the substrates of all the NMOS transistors are grounded GND.
Specifically, the second amplifier AMP2 and the first operational amplifier AMP1 have the same structure.
Specifically, the third amplifier AMP3 includes a fifteenth PMOS transistor P15, a sixteenth PMOS transistor P16, a seventeenth PMOS transistor P17, an eighteenth PMOS transistor P18, a nineteenth PMOS transistor P19, a twentieth PMOS transistor P20, a twenty-first PMOS transistor P21, a twenty-second PMOS transistor P22, an eleventh NMOS transistor N11, a twelfth NMOS transistor N12, a thirteenth NMOS transistor N13, a fourteenth NMOS transistor N14, a fifteenth NMOS transistor N15, a sixteenth NMOS transistor N16, a seventeenth NMOS transistor N17, an eighteenth NMOS transistor N18, a nineteenth NMOS transistor N19, a twentieth NMOS transistor N20, a twenty-first NMOS transistor N21, a twenty-second NMOS transistor N22, a sixth resistor R6, a seventh resistor R7, and a second bias current source Ibias 2; wherein,
the gate of the eleventh NMOS transistor N11 is the same-direction input end of the third amplifier AMP3, the drain is connected to the source of the fifteenth PMOS transistor P15 and the drain of the eighteenth PMOS transistor P18, the source is connected to the source of the twelfth NMOS transistor N12 and the drain of the fourteenth NMOS transistor N14, the gate of the twelfth NMOS transistor N12 is the opposite-direction input end of the third amplifier AMP3, and the drain is connected to the source of the sixteenth PMOS transistor P16 and the drain of the seventeenth PMOS transistor P17;
the grid electrode of a seventeenth PMOS tube P17, the grid electrode of an eighteenth PMOS tube P18, the grid electrode of a twentieth PMOS tube P20, the grid electrode and the drain electrode of a nineteenth PMOS tube P19 are connected with the source electrode of a twenty-first PMOS tube P21, the grid electrode of a fifteenth PMOS tube P15, the grid electrode of a sixteenth PMOS tube P16, the grid electrode of a twenty-second PMOS tube P22, the grid electrode and the drain electrode of the twenty-first PMOS tube P21 are connected with the positive electrode of a second bias current source Ibias2, and the drain electrode of the twentieth PMOS tube P20 is connected with the source electrode of a twenty-second PMOS tube P22;
the grid and the drain of a thirteenth NMOS tube N13, the grid of a fourteenth NMOS tube N14, one end of a sixth resistor R6 and the drain of a twenty-second PMOS tube P22 are connected, the source of the thirteenth NMOS tube N13 and the drain of a fifteenth NMOS tube N15 are connected, the drain of the thirteenth NMOS tube N13, the other end of the sixth resistor R6, the grid of the fifteenth NMOS tube N15 and the grid of a sixteenth NMOS tube N16 are connected, and the source of the fourteenth NMOS tube N14 and the drain of the sixteenth NMOS tube N16 are connected;
the grid and the drain of a seventeenth NMOS transistor N17, the grid of an eighteenth NMOS transistor N18, one end of a seventh resistor R7 are connected with the drain of a twenty-second PMOS transistor P22, the source of the seventeenth NMOS transistor N17 is connected with the drain of a nineteenth NMOS transistor N19, the drain of a seventeenth NMOS transistor N17, the other end of the seventh resistor R7, the grid of the nineteenth NMOS transistor N19 is connected with the grid of a twenty NMOS transistor N20, and the source of the eighteenth NMOS transistor N18 is connected with the drain of a twentieth NMOS transistor N20;
the drain electrode of the sixteenth PMOS tube P16 and the source electrode of the eighteenth NMOS tube N18 are connected as the output end of a third amplifier AMP 3;
the source electrode of the seventeenth PMOS tube P17, the source electrode of the eighteenth PMOS tube P18, the source electrode of the nineteenth PMOS tube P19, the source electrode of the twentieth PMOS tube P20 and the substrates of all the PMOS tubes are connected with a power supply VDD;
the cathode of the second bias current source Ibias2, the source of the fifteenth NMOS transistor N15, the source of the sixteenth NMOS transistor N16, the source of the nineteenth NMOS transistor N19, the source of the twentieth NMOS transistor N20 and the substrates of all the NMOS transistors are grounded.
Compared with the traditional error amplifier, the invention has the beneficial effects that the invention provides a novel error amplifier structure, two transconductance amplifiers are adopted to convert voltage into current, the current is respectively mirrored to two current sources, and the current is respectively poured into/pulled out of the capacitor C1, so that the output voltage is adjusted, the response speed and the precision of the system are improved, the stability of the system is improved, the input transconductance is constant, the output resistance and the low-frequency gain are in a proper range, the power supply rejection ratio is high, the offset voltage is small, and the output voltage can be effectively locked.
Drawings
FIG. 1 is a schematic diagram of a conventional error amplifier circuit;
FIG. 2 is a logic block diagram of an error amplifier circuit of the present invention;
FIG. 3 is a circuit diagram of an error amplifier circuit according to the present invention;
FIG. 4 is a schematic diagram of the first amplifier AMP1 according to the present invention;
fig. 5 is a schematic circuit diagram of the third amplifier AMP3 according to the present invention.
Detailed Description
The technical scheme of the invention is described in detail in the following with the accompanying drawings:
as shown in fig. 2, the error amplifier circuit according to the present invention includes a first transconductance amplifier, a second transconductance amplifier, a first mirror current, a second mirror current, and a first capacitor C1, wherein an input terminal of the first transconductance amplifier is a first input terminal Vref of the error amplifier circuit, an output terminal of the first transconductance amplifier is connected to the first mirror current, an input terminal of the second transconductance amplifier is a second input terminal Vin of the error amplifier circuit, an output terminal of the second transconductance amplifier is connected to the second mirror current, an output terminal of the first mirror current and an output terminal of the second mirror current are connected to one end of a first capacitor C1 to be an output terminal Vea of the error amplifier circuit, and the other end of the first capacitor C1 is grounded.
As shown in fig. 3, the first transconductance amplifier includes a first operational amplifier AMP1, a second capacitor C2, a first resistor R1 and a first NMOS transistor N1, the second transconductance amplifier includes a second operational amplifier AMP2, a third operational amplifier AMP3, a third capacitor C3, a second resistor R2, a third resistor R3, a fourth resistor R4 and a second NMOS transistor N2, the first mirror current includes a first PMOS transistor P1, a second PMOS transistor P2, a third PMOS transistor P3 and a fourth PMOS transistor P4, the second mirror current includes a third NMOS transistor N3, a fourth NMOS transistor N4, a fifth NMOS transistor N5 and a sixth NMOS transistor N6; wherein,
the same-direction input end of the first operational amplifier AMP1 is a first input end Vref of the error amplifier circuit, the reverse-direction input end is connected with one end of a first resistor R1 and the source electrode of a first NMOS transistor N1, and the output end is connected with one end of a second capacitor C2 and the grid electrode of the first NMOS transistor N1;
the same-direction input end of the second operational amplifier AMP2 is a second input end Vin of the error amplifier circuit, the reverse-direction input end is connected with one end of a fourth resistor R4 and the source electrode of the second NMOS transistor N2, and the output end is connected with one end of a third capacitor C3 and the grid electrode of the second NMOS transistor N2;
the drain electrode of the second NMOS transistor N2 and one end of the second resistor R2 are connected with the inverting input end of the third operational amplifier AMP3, one end of the third resistor R3 and the drain electrode of the third NMOS transistor N3 are connected with the homonymous input end of the third operational amplifier AMP3, and the output end of the third operational amplifier AMP3 is connected with the gate electrode of the third NMOS transistor N3 and the gate electrode of the fourth NMOS transistor N4;
the grid and the drain of a first PMOS tube P1 are connected with the drain of a first NMOS tube N1 and the grid of a second PMOS tube P2, the source is connected with the drain of a third PMOS tube P3, the grid and the drain of the third PMOS tube P3 and the grid and the drain of a fourth PMOS tube P4 are connected with the source of a second PMOS tube P2;
the drain electrode of the second PMOS tube P2, the source electrode of the fourth NMOS tube N4 and one end of the first capacitor C1 are connected to serve as the output end Vea of the error amplifier circuit;
the source electrode of the third NMOS transistor N3 is connected with the drain electrode of the fifth NMOS transistor N5, the source electrode of the fourth NMOS transistor N4, the grid electrode of the fifth NMOS transistor N5 and the grid electrode and the drain electrode of the sixth NMOS transistor N6 are connected;
the source electrode of the third PMOS tube P3, the source electrode of the fourth PMOS tube P4, the other end of the second resistor R2, the other end of the third resistor R3 and the substrates of all the PMOS tubes are connected with a power supply VDD;
the other end of the first resistor R1, the other end of the second capacitor C2, the other end of the third capacitor C3, the other end of the fourth resistor R4, the source of the fifth NMOS transistor N5, the source of the sixth NMOS transistor N6 and the substrates of all the NMOS transistors are grounded.
As shown in fig. 4, the first operational amplifier AMP1 includes a fifth PMOS transistor P5, a sixth PMOS transistor P6, a seventh PMOS transistor P7, an eighth PMOS transistor P8, a ninth PMOS transistor P9, a tenth PMOS transistor P10, an eleventh PMOS transistor P11, a twelfth PMOS transistor P12, a thirteenth PMOS transistor P13, a fourteenth PMOS transistor P14, a seventh NMOS transistor N7, an eighth NMOS transistor N8, a ninth NMOS transistor N9, a tenth NMOS transistor N10, a fifth resistor R5, and a first bias current source Ibias 1; wherein,
a fifth PMOS tube P5 and a sixth PMOS tube P6 form a PMOS input differential pair, the grid electrode of the fifth PMOS tube P5 is connected with the homodromous input end of the first operational amplifier AMP1, the drain electrode of the fifth PMOS tube P5 is connected with the source electrode of the seventh NMOS tube N7 and the drain electrode of the eighth NMOS tube N8, the grid electrode of the sixth PMOS tube P6 is connected with the inverting input end of the operational amplifier AMP, and the drain electrode of the sixth PMOS tube P3583 is connected with the source electrode of the ninth NMOS tube N9 and the drain electrode of the tenth NMOS tube N10;
the drain electrode of the seventh NMOS transistor N7 is connected with one end of a fifth resistor R5, the gate electrode of an eighth NMOS transistor N8 and the gate electrode of a ninth NMOS transistor N9, and the other end of the fifth resistor R5 is connected with the gate electrode of a seventh NMOS transistor N7, the gate electrode of an eighth NMOS transistor N8 and the drain electrode of a seventh PMOS transistor P7;
the grid electrode of the seventh PMOS tube P7, the grid electrode of the eighth PMOS tube P8, the grid electrode of the fourteenth PMOS tube P14, the grid electrode and the drain electrode of the twelfth PMOS tube P12 and the anode of the first bias current source Ibias1 are connected, the source electrode of the twelfth PMOS tube P12 is connected with the drain electrode and the grid electrode of the eleventh PMOS tube P11, the grid electrode of the thirteenth PMOS tube P13, the grid electrode of the ninth PMOS tube P9 and the grid electrode of the tenth PMOS tube P10, the drain electrode of the thirteenth PMOS tube P13 is connected with the source electrode of the fourteenth PMOS tube P14, and the drain electrode of the fourteenth PMOS tube P14 is connected with the source electrode of the fifth PMOS tube P5 and the source electrode of the sixth PMOS tube P6;
the source electrode of the seventh PMOS tube P7 is connected with the drain electrode of the ninth PMOS tube P9, and the source electrode of the eighth PMOS tube P8 is connected with the drain electrode of the tenth PMOS tube P10;
the drain electrode of the eighth PMOS transistor P8 and the source electrode of the tenth NMOS transistor N10 are connected as the output end of the first operational amplifier AMP 1;
the source electrode of the ninth PMOS tube P9, the source electrode of the tenth PMOS tube P10, the source electrode of the eleventh PMOS tube P11, the source electrode of the thirteenth PMOS tube P13 and the substrates of all the PMOS tubes are connected with a power supply VDD;
the cathode of the first bias current source Ibias1, the source of the eighth NMOS transistor N8, the source of the ninth NMOS transistor N9, and the substrates of all the NMOS transistors are grounded GND.
The second amplifier AMP2 and the first operational amplifier AMP1 have the same structure, and the specific structure is the structure of the first operational amplifier AMP1 described above in the present invention, which is not described again.
As shown in fig. 5, the third amplifier AMP3 includes a fifteenth PMOS transistor P15, a sixteenth PMOS transistor P16, a seventeenth PMOS transistor P17, an eighteenth PMOS transistor P18, a nineteenth PMOS transistor P19, a twentieth PMOS transistor P20, a twenty-first PMOS transistor P21, a twenty-second PMOS transistor P22, an eleventh NMOS transistor N11, a twelfth NMOS transistor N12, a thirteenth NMOS transistor N13, a fourteenth NMOS transistor N14, a fifteenth NMOS transistor N15, a sixteenth NMOS transistor N16, a seventeenth NMOS transistor N17, an eighteenth NMOS transistor N18, a nineteenth NMOS transistor N19, a twentieth NMOS transistor N20, a twenty-first NMOS transistor N21, a twenty-second NMOS transistor N22, a sixth resistor R6, a seventh resistor R7, and a second bias current source Ibias 2; wherein,
the gate of the eleventh NMOS transistor N11 is the same-direction input end of the third amplifier AMP3, the drain is connected to the source of the fifteenth PMOS transistor P15 and the drain of the eighteenth PMOS transistor P18, the source is connected to the source of the twelfth NMOS transistor N12 and the drain of the fourteenth NMOS transistor N14, the gate of the twelfth NMOS transistor N12 is the opposite-direction input end of the third amplifier AMP3, and the drain is connected to the source of the sixteenth PMOS transistor P16 and the drain of the seventeenth PMOS transistor P17;
the grid electrode of a seventeenth PMOS tube P17, the grid electrode of an eighteenth PMOS tube P18, the grid electrode of a twentieth PMOS tube P20, the grid electrode and the drain electrode of a nineteenth PMOS tube P19 are connected with the source electrode of a twenty-first PMOS tube P21, the grid electrode of a fifteenth PMOS tube P15, the grid electrode of a sixteenth PMOS tube P16, the grid electrode of a twenty-second PMOS tube P22, the grid electrode and the drain electrode of the twenty-first PMOS tube P21 are connected with the positive electrode of a second bias current source Ibias2, and the drain electrode of the twentieth PMOS tube P20 is connected with the source electrode of a twenty-second PMOS tube P22;
the grid and the drain of a thirteenth NMOS tube N13, the grid of a fourteenth NMOS tube N14, one end of a sixth resistor R6 and the drain of a twenty-second PMOS tube P22 are connected, the source of the thirteenth NMOS tube N13 and the drain of a fifteenth NMOS tube N15 are connected, the drain of the thirteenth NMOS tube N13, the other end of the sixth resistor R6, the grid of the fifteenth NMOS tube N15 and the grid of a sixteenth NMOS tube N16 are connected, and the source of the fourteenth NMOS tube N14 and the drain of the sixteenth NMOS tube N16 are connected;
the grid and the drain of a seventeenth NMOS transistor N17, the grid of an eighteenth NMOS transistor N18, one end of a seventh resistor R7 are connected with the drain of a twenty-second PMOS transistor P22, the source of the seventeenth NMOS transistor N17 is connected with the drain of a nineteenth NMOS transistor N19, the drain of a seventeenth NMOS transistor N17, the other end of the seventh resistor R7, the grid of the nineteenth NMOS transistor N19 is connected with the grid of a twenty NMOS transistor N20, and the source of the eighteenth NMOS transistor N18 is connected with the drain of a twentieth NMOS transistor N20;
the drain electrode of the sixteenth PMOS tube P16 and the source electrode of the eighteenth NMOS tube N18 are connected as the output end of a third amplifier AMP 3;
the source electrode of the seventeenth PMOS tube P17, the source electrode of the eighteenth PMOS tube P18, the source electrode of the nineteenth PMOS tube P19, the source electrode of the twentieth PMOS tube P20 and the substrates of all the PMOS tubes are connected with a power supply VDD;
the cathode of the second bias current source Ibias2, the source of the fifteenth NMOS transistor N15, the source of the sixteenth NMOS transistor N16, the source of the nineteenth NMOS transistor N19, the source of the twentieth NMOS transistor N20 and the substrates of all the NMOS transistors are grounded.
The working principle and the process of the invention are as follows:
for convenience of illustration, the first mirror current is a constant mirror current source, and the second mirror current is a controlled mirror current sink.
The first transconductance amplifier inputs a voltage signal VrefIs converted into an electric current I1Let us consider that the gain of the first operational amplifier AMP1 is sufficiently large and the output current is sufficiently large
The second capacitor C2 is used to reduce the frequency of the dominant pole of the loop to achieve a phase margin of 60 deg. The PMOS transistors P1-P4 form a circuit which is a Wilson current mirror and is a constant mirror current source, and the purpose of the constant mirror current source is to convert the current I1Performs accurate amplification and provides a large output resistance. The expression of the output resistance of the Wilson current mirror is Rout＝ro3.(1+gm3.ro4)。
The second operational amplifier AMP2 in the second transconductance amplifier is identical to the first operational amplifier AMP1 in the first transconductance amplifier in design, because this makes the constant mirror current source as symmetrical as possible to the input of the controlled mirror current sink to reduce the input offset voltage of the error amplifier.
The second transconductance amplifier converts the input voltage signal VrefIs converted into an electric current I4Similarly, the gain of the second operational amplifier AMP2 is considered to be large enough to output current
The third capacitor C3 is used to reduce the frequency of the dominant pole of the loop to achieve a phase margin of 60 deg. The third operational amplifier AMP3 is used for summing and negatively feeding I by current sampling voltage2Input current I accurately copied to Wilson current source formed by NMOS tube3In which I4＝I3＝I2. And the output of the Wilson current source is used for achieving the purpose of matching with a mirror current source circuit.
Constant mirror current source output current IsourceAnd controlled mirror current sink output current IsinkThe current comparison is performed and the first capacitor C1 is charged or discharged, thereby changing the error amplifier output VeaA voltage.
In conclusion, the error amplifier has a novel structure, and the output voltage is adjusted by charging and discharging the first capacitor C1 through the current comparison of the mirror current source and the mirror current sink, so that the response speed and the accuracy of the system are improved, and the stability of the system is improved. And input transconductance is constant, output resistance and low-frequency gain are in a proper range, the power supply rejection ratio is high, offset voltage is small, and output voltage can be effectively locked.
Claims (5)
1. An error amplifier circuit is characterized by comprising a first transconductance amplifier, a second transconductance amplifier, a first mirror current, a second mirror current and a first capacitor C1, wherein the input end of the first transconductance amplifier is a first input end Vref of the error amplifier circuit, the output end of the first mirror current is connected with the first mirror current, the input end of the second transconductance amplifier is a second input end Vin of the error amplifier circuit, the output end of the second mirror current is connected with the second mirror current, the output end of the first mirror current and the output end of the second mirror current are connected with one end of a first capacitor C1 to serve as an output end Vea of the error amplifier circuit, and the other end of the first capacitor C1 is grounded.
2. The error amplifier circuit of claim 1, wherein the first transconductance amplifier comprises a first operational amplifier AMP1, a second capacitor C2, a first resistor R1, and a first NMOS transistor N1, wherein the second transconductance amplifier comprises a second operational amplifier AMP2, a third operational amplifier AMP3, a third capacitor C3, a second resistor R2, a third resistor R3, a fourth resistor R4, and a second NMOS transistor N2, wherein the first mirror current comprises a first PMOS transistor P1, a second PMOS transistor P2, a third PMOS transistor P3, and a fourth PMOS transistor P4, wherein the second mirror current comprises a third NMOS transistor N3, a fourth NMOS transistor N4, a fifth NMOS transistor N5, and a sixth NMOS transistor N6; wherein,
the same-direction input end of the first operational amplifier AMP1 is a first input end Vref of the error amplifier circuit, the reverse-direction input end is connected with one end of a first resistor R1 and the source electrode of a first NMOS transistor N1, and the output end is connected with one end of a second capacitor C2 and the grid electrode of the first NMOS transistor N1;
the same-direction input end of the second operational amplifier AMP2 is a second input end Vin of the error amplifier circuit, the reverse-direction input end is connected with one end of a fourth resistor R4 and the source electrode of the second NMOS transistor N2, and the output end is connected with one end of a third capacitor C3 and the grid electrode of the second NMOS transistor N2;
the drain electrode of the second NMOS transistor N2 and one end of the second resistor R2 are connected with the inverting input end of the third operational amplifier AMP3, one end of the third resistor R3 and the drain electrode of the third NMOS transistor N3 are connected with the homonymous input end of the third operational amplifier AMP3, and the output end of the third operational amplifier AMP3 is connected with the gate electrode of the third NMOS transistor N3 and the gate electrode of the fourth NMOS transistor N4;
the grid and the drain of a first PMOS tube P1 are connected with the drain of a first NMOS tube N1 and the grid of a second PMOS tube P2, the source is connected with the drain of a third PMOS tube P3, the grid and the drain of the third PMOS tube P3 and the grid and the drain of a fourth PMOS tube P4 are connected with the source of a second PMOS tube P2;
the drain electrode of the second PMOS tube P2, the source electrode of the fourth NMOS tube N4 and one end of the first capacitor C1 are connected to serve as the output end Vea of the error amplifier circuit;
the source electrode of the third NMOS transistor N3 is connected with the drain electrode of the fifth NMOS transistor N5, the source electrode of the fourth NMOS transistor N4, the grid electrode of the fifth NMOS transistor N5 and the grid electrode and the drain electrode of the sixth NMOS transistor N6 are connected;
the source electrode of the third PMOS tube P3, the source electrode of the fourth PMOS tube P4, the other end of the second resistor R2, the other end of the third resistor R3 and the substrates of all the PMOS tubes are connected with a power supply VDD;
the other end of the first resistor R1, the other end of the second capacitor C2, the other end of the third capacitor C3, the other end of the fourth resistor R4, the source of the fifth NMOS transistor N5, the source of the sixth NMOS transistor N6 and the substrates of all the NMOS transistors are grounded.
3. The error amplifier circuit as claimed in claim 2, wherein the first operational amplifier AMP1 comprises a fifth PMOS transistor P5, a sixth PMOS transistor P6, a seventh PMOS transistor P7, an eighth PMOS transistor P8, a ninth PMOS transistor P9, a tenth PMOS transistor P10, an eleventh PMOS transistor P11, a twelfth PMOS transistor P12, a thirteenth PMOS transistor P13, a fourteenth PMOS transistor P14, a seventh NMOS transistor N7, an eighth NMOS transistor N8, a ninth NMOS transistor N9, a tenth NMOS transistor N10, a fifth resistor R5 and a first bias current source Ibias 1; wherein,
the grid electrode of the fifth PMOS pipe P5 is connected with the same-direction input end of the first operational amplifier AMP1, the drain electrode of the fifth PMOS pipe P5 is connected with the source electrode of the seventh NMOS pipe N7 and the drain electrode of the eighth NMOS pipe N8, the grid electrode of the sixth PMOS pipe P6 is connected with the reverse-direction input end of the operational amplifier AMP, and the drain electrode of the sixth PMOS pipe P6 is connected with the source electrode of the ninth NMOS pipe N9 and the drain electrode of the tenth NMOS pipe N10;
the drain electrode of the seventh NMOS transistor N7 is connected with one end of a fifth resistor R5, the gate electrode of an eighth NMOS transistor N8 and the gate electrode of a ninth NMOS transistor N9, and the other end of the fifth resistor R5 is connected with the gate electrode of a seventh NMOS transistor N7, the gate electrode of an eighth NMOS transistor N8 and the drain electrode of a seventh PMOS transistor P7;
the grid electrode of the seventh PMOS tube P7, the grid electrode of the eighth PMOS tube P8, the grid electrode of the fourteenth PMOS tube P14, the grid electrode and the drain electrode of the twelfth PMOS tube P12 and the anode of the first bias current source Ibias1 are connected, the source electrode of the twelfth PMOS tube P12 is connected with the drain electrode and the grid electrode of the eleventh PMOS tube P11, the grid electrode of the thirteenth PMOS tube P13, the grid electrode of the ninth PMOS tube P9 and the grid electrode of the tenth PMOS tube P10, the drain electrode of the thirteenth PMOS tube P13 is connected with the source electrode of the fourteenth PMOS tube P14, and the drain electrode of the fourteenth PMOS tube P14 is connected with the source electrode of the fifth PMOS tube P5 and the source electrode of the sixth PMOS tube P6;
the source electrode of the seventh PMOS tube P7 is connected with the drain electrode of the ninth PMOS tube P9, and the source electrode of the eighth PMOS tube P8 is connected with the drain electrode of the tenth PMOS tube P10;
the drain electrode of the eighth PMOS transistor P8 and the source electrode of the tenth NMOS transistor N10 are connected as the output end of the first operational amplifier AMP 1;
the source electrode of the ninth PMOS tube P9, the source electrode of the tenth PMOS tube P10, the source electrode of the eleventh PMOS tube P11, the source electrode of the thirteenth PMOS tube P13 and the substrates of all the PMOS tubes are connected with a power supply VDD;
the cathode of the first bias current source Ibias1, the source of the eighth NMOS transistor N8, the source of the ninth NMOS transistor N9, and the substrates of all the NMOS transistors are grounded GND.
4. The error amplifier circuit of claim 3, wherein the second amplifier AMP2 and the first operational amplifier AMP1 are identical in structure.
5. The error amplifier circuit of claim 4, wherein the third amplifier AMP3 comprises a fifteenth PMOS transistor P15, a sixteenth PMOS transistor P16, a seventeenth PMOS transistor P17, an eighteenth PMOS transistor P18, a nineteenth PMOS transistor P19, a twentieth PMOS transistor P20, a twenty-first PMOS transistor P21, a twenty-second PMOS transistor P22, an eleventh NMOS transistor N11, a twelfth NMOS transistor N12, a thirteenth NMOS transistor N13, a fourteenth NMOS transistor N14, a fifteenth NMOS transistor N15, a sixteenth NMOS transistor N16, a seventeenth NMOS transistor N17, an eighteenth NMOS transistor N18, a nineteenth NMOS transistor N19, a twentieth NMOS transistor N20, a twenty-first NMOS transistor N21, a twenty-second NMOS transistor N22, a sixth resistor R6, a seventh resistor R7 and a second bias current source Ibias 2; wherein,
the gate of the eleventh NMOS transistor N11 is the same-direction input end of the third amplifier AMP3, the drain is connected to the source of the fifteenth PMOS transistor P15 and the drain of the eighteenth PMOS transistor P18, the source is connected to the source of the twelfth NMOS transistor N12 and the drain of the fourteenth NMOS transistor N14, the gate of the twelfth NMOS transistor N12 is the opposite-direction input end of the third amplifier AMP3, and the drain is connected to the source of the sixteenth PMOS transistor P16 and the drain of the seventeenth PMOS transistor P17;
the grid electrode of a seventeenth PMOS tube P17, the grid electrode of an eighteenth PMOS tube P18, the grid electrode of a twentieth PMOS tube P20, the grid electrode and the drain electrode of a nineteenth PMOS tube P19 are connected with the source electrode of a twenty-first PMOS tube P21, the grid electrode of a fifteenth PMOS tube P15, the grid electrode of a sixteenth PMOS tube P16, the grid electrode of a twenty-second PMOS tube P22, the grid electrode and the drain electrode of the twenty-first PMOS tube P21 are connected with the positive electrode of a second bias current source Ibias2, and the drain electrode of the twentieth PMOS tube P20 is connected with the source electrode of a twenty-second PMOS tube P22;
the grid and the drain of a thirteenth NMOS tube N13, the grid of a fourteenth NMOS tube N14, one end of a sixth resistor R6 and the drain of a twenty-second PMOS tube P22 are connected, the source of the thirteenth NMOS tube N13 and the drain of a fifteenth NMOS tube N15 are connected, the drain of the thirteenth NMOS tube N13, the other end of the sixth resistor R6, the grid of the fifteenth NMOS tube N15 and the grid of a sixteenth NMOS tube N16 are connected, and the source of the fourteenth NMOS tube N14 and the drain of the sixteenth NMOS tube N16 are connected;
the grid and the drain of a seventeenth NMOS transistor N17, the grid of an eighteenth NMOS transistor N18, one end of a seventh resistor R7 are connected with the drain of a twenty-second PMOS transistor P22, the source of the seventeenth NMOS transistor N17 is connected with the drain of a nineteenth NMOS transistor N19, the drain of a seventeenth NMOS transistor N17, the other end of the seventh resistor R7, the grid of the nineteenth NMOS transistor N19 is connected with the grid of a twenty NMOS transistor N20, and the source of the eighteenth NMOS transistor N18 is connected with the drain of a twentieth NMOS transistor N20;
the drain electrode of the sixteenth PMOS tube P16 and the source electrode of the eighteenth NMOS tube N18 are connected as the output end of a third amplifier AMP 3;
the source electrode of the seventeenth PMOS tube P17, the source electrode of the eighteenth PMOS tube P18, the source electrode of the nineteenth PMOS tube P19, the source electrode of the twentieth PMOS tube P20 and the substrates of all the PMOS tubes are connected with a power supply VDD;
the cathode of the second bias current source Ibias2, the source of the fifteenth NMOS transistor N15, the source of the sixteenth NMOS transistor N16, the source of the nineteenth NMOS transistor N19, the source of the twentieth NMOS transistor N20 and the substrates of all the NMOS transistors are grounded.
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| CN105811905A (en) * | 2014-12-29 | 2016-07-27 | 意法半导体研发(深圳)有限公司 | Low-dropout amplifier |
| CN108736834A (en) * | 2018-05-23 | 2018-11-02 | 中国电子科技集团公司第二十四研究所 | A kind of high linearity time amplifier that charged inhibits |
| CN109861673A (en) * | 2019-03-14 | 2019-06-07 | 广州金升阳科技有限公司 | A kind of current comparator |
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| CN112671237A (en) * | 2021-03-17 | 2021-04-16 | 四川蕊源集成电路科技有限公司 | Circuit structure and method for improving response of current mode BUCK type direct current converter |
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| CN115173817A (en) * | 2022-09-05 | 2022-10-11 | 深圳市单源半导体有限公司 | Differential amplification circuit, error amplification circuit and trimming method thereof |
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