CN103414438A - Error amplifier circuit - Google Patents

Abstract

The invention belongs to the technical field of electronics, and relates to an integrated circuit design technology, in particular to a novel current injection/pulling error amplifier circuit. The error amplifier circuit comprises a first transconductance amplifier, a second transconductance amplifier, a first image current source, a second image current source and a first capacitor C1, wherein the input end of the first transconductance amplifier is a first input end Vref of the error amplifier circuit, the output end of the first transconductance amplifier is connected with the first image current source, the input end of the second transconductance amplifier is a second input end Vin of the error amplifier circuit, the output end of the second transconductance amplifier is connected with the second image current source, and the output end of the first image current source and the output end of the second image current source are connected with one end of the first capacitor C1 to serve as an output end Vea of the error amplifier circuit. The error amplifier circuit has the advantages of being capable of adjusting the output voltage, improving the response speed and response accuracy of a system and improving the stability of the system, and is particularly suitable for an error amplifier.

Description

An error amplifier circuit

technical field

The invention relates to integrated circuit technology, in particular to a novel current sinking/pulling out error amplifier circuit.

Background technique

The error amplifier has always been the core circuit of the converter in the switching power supply, which has an important influence on the fast, accurate and stable operation of the system.

The traditional error amplifier is shown in Figure 1. The traditional error amplifier includes bias PMOS transistors M6 and M7, input PMOS transistors M1 and M2, and NMOS transistors M3, M4 and M5; where the sources of PMOS transistors M1 and M2 are connected to form a differential pair , and connected to the source of the M6 tube, the M6 tube provides the tail current for the op amp; the gates of the PMOS tubes M1 and M2 are respectively used as the positive phase input terminal V _in1 and the negative phase input terminal V _in2 of the error amplifier; the gates of the NMOS tubes M3 and M4 The gates are connected to form a current mirror structure; the gate of the NMOS tube M5 is connected to the drain of the M1 tube, and the drain of the M5 tube is connected to the drain of the PMOS tube M7 as the output of the error amplifier, and the output voltage V _out ;

The traditional error amplifier is designed as a voltage type, which ensures high loop gain and sufficient phase margin to stabilize the system. However, the output current of the amplifier is small and the transient response is slow, and the design of the compensation network is complicated. Therefore, designing an error amplifier with fast transient response and high precision has become a hot research topic at present.

The invention designs a transconductance type current sinking/pulling out error amplifier with novel structure, high precision and high performance, which can sample small voltage and output large current, and realize fast transient response of the system. The input stage uses a high-precision transconductance amplifier circuit, and the main pole is close to the origin, which improves the amplifier gain. The output stage uses a current source and a current sink to sink/source current to/from the capacitor C1 respectively.

Contents of the invention

The technical problem to be solved by the present invention is to propose an error amplifier circuit for the above-mentioned problems of the traditional error amplifier.

The technical solution adopted by the present invention to solve the above technical problems is: an error amplifier circuit, characterized in that it includes a first transconductance amplifier, a second transconductance amplifier, a first mirror current, a second mirror current and a first capacitor C1 , the input terminal of the first transconductance amplifier is the first input terminal Vref of the error amplifier circuit, the output terminal is connected to the first mirror current, and the input terminal of the second transconductance amplifier is the second input terminal Vin of the error amplifier circuit 1. The output terminal is connected to the second mirror current, the output terminal of the first mirror current and the output terminal of the second mirror current are connected to one end of the first capacitor C1 as the output terminal Vea of the error amplifier circuit, and the other end of the first capacitor C1 is grounded.

Specifically, the first transconductance amplifier includes a first operational amplifier AMP1, a second capacitor C2, a first resistor R1, and a first NMOS transistor N1, and the second transconductance amplifier includes a second operational amplifier AMP2, a third operational The amplifier AMP3, the third capacitor C3, the second resistor R2, the third resistor R3, the fourth resistor R4 and the second NMOS transistor N2, the first mirror current includes the first PMOS transistor P1, the second PMOS transistor P2, the third PMOS transistor P3 and fourth PMOS transistor P4, the second mirror current includes a third NMOS transistor N3, a fourth NMOS transistor N4, a fifth NMOS transistor N5, and a sixth NMOS transistor N6; wherein,

The non-inverting input terminal of the first operational amplifier AMP1 is the first input terminal Vref of the error amplifier circuit, the inverting input terminal is connected to one end of the first resistor R1 and the source of the first NMOS transistor N1, and the output terminal is connected to the second capacitor C2 One end of is connected to the gate of the first NMOS transistor N1;

The non-inverting input terminal of the second operational amplifier AMP2 is the second input terminal Vin of the error amplifier circuit, the inverting input terminal is connected to one end of the fourth resistor R4 and the source of the second NMOS transistor N2, and the output terminal is connected to the third capacitor C3 One end of is connected to the gate of the second NMOS transistor N2;

The drain of the second NMOS transistor N2 and one end of the second resistor R2 are connected to the inverting input end of the third operational amplifier AMP3, and one end of the third resistor R3 and the drain of the third NMOS transistor N3 are connected to the same terminal of the third operational amplifier AMP3. To the input end, the output end of the third operational amplifier AMP3 is connected to the gate of the third NMOS transistor N3 and the gate of the fourth NMOS transistor N4;

The gate and drain of the first PMOS transistor P1 are connected to the drain of the first NMOS transistor N1 and the gate of the second PMOS transistor P2, the source is connected to the drain of the third PMOS transistor P3, and the gate of the third PMOS transistor P3 , the gate and drain of the fourth PMOS transistor P4 are connected to the source of the second PMOS transistor P2;

The drain of the second PMOS transistor P2, the source of the fourth NMOS transistor N4 and one end of the first capacitor C1 are connected as the output terminal Vea of the error amplifier circuit;

The source of the third NMOS transistor N3 is connected to the drain of the fifth NMOS transistor N5, the source of the fourth NMOS transistor N4, the gate of the fifth NMOS transistor N5, and the gate and drain of the sixth NMOS transistor N6 are connected;

The source of the third PMOS transistor P3, the source of the fourth PMOS transistor P4, the other end of the second resistor R2, the other end of the third resistor R3 and the substrates of all PMOS transistors are connected to the power supply VDD;

The other end of the first resistor R1, the other end of the second capacitor C2, the other end of the third capacitor C3, the other end of the fourth resistor R4, the source of the fifth NMOS transistor N5, the source of the sixth NMOS transistor N6 and The substrates of all NMOS transistors are grounded.

Specifically, the first operational amplifier AMP1 includes a fifth PMOS transistor P5, a sixth PMOS transistor P6, a seventh PMOS transistor P7, an eighth PMOS transistor P8, a ninth PMOS transistor P9, a tenth PMOS transistor P10, and an eleventh PMOS transistor P10. PMOS transistor P11, twelfth PMOS transistor P12, thirteenth PMOS transistor P13, fourteenth PMOS transistor P14, seventh NMOS transistor N7, eighth NMOS transistor N8, ninth NMOS transistor N9, tenth NMOS transistor N10, Five resistors R5 and the first bias current source Ibias1; where,

The gate of the fifth PMOS transistor P5 is connected to the non-inverting input terminal of the first operational amplifier AMP1, the drain is connected to the source of the seventh NMOS transistor N7 and the drain of the eighth NMOS transistor N8, and the gate of the sixth PMOS transistor P6 is connected to The inverting input terminal and the drain of the operational amplifier AMP are connected to the source of the ninth NMOS transistor N9 and the drain of the tenth NMOS transistor N10;

The drain of the seventh NMOS transistor N7 is connected to one end of the fifth resistor R5, the gate of the eighth NMOS transistor N8, and the gate of the ninth NMOS transistor N9, and the other end of the fifth resistor R5 is connected to the gate of the seventh NMOS transistor N7 , the gate of the eighth NMOS transistor N8 and the drain of the seventh PMOS transistor P7;

The gate of the seventh PMOS transistor P7, the gate of the eighth PMOS transistor P8, the gate of the fourteenth PMOS transistor P14, the gate and the drain of the twelfth PMOS transistor P12, and the anode of the first bias current source Ibias1 The source of the twelfth PMOS transistor P12 is connected to the drain and gate of the eleventh PMOS transistor P11, the gate of the thirteenth PMOS transistor P13, the gate of the ninth PMOS transistor P9, and the gate of the tenth PMOS transistor P10 Gate connection, the drain of the thirteenth PMOS transistor P13 is connected to the source of the fourteenth PMOS transistor P14, the drain of the fourteenth PMOS transistor P14 is connected to the source of the fifth PMOS transistor P5 and the source of the sixth PMOS transistor P6 source connection;

The source of the seventh PMOS transistor P7 is connected to the drain of the ninth PMOS transistor P9, and the source of the eighth PMOS transistor P8 is connected to the drain of the tenth PMOS transistor P10;

The drain of the eighth PMOS transistor P8 and the source of the tenth NMOS transistor N10 are connected as the output end of the first operational amplifier AMP1;

The source of the ninth PMOS transistor P9, the source of the tenth PMOS transistor P10, the source of the eleventh PMOS transistor P11, the source of the thirteenth PMOS transistor P13 and the substrates of all PMOS transistors are connected to the power supply VDD;

The cathode of the first bias current source Ibias1 , the source of the eighth NMOS transistor N8 , the source of the ninth NMOS transistor N9 and the substrates of all NMOS transistors are grounded to GND.

Specifically, the structure of the second amplifier AMP2 is the same as that of the first operational amplifier AMP1.

Specifically, the third amplifier AMP3 includes a fifteenth PMOS transistor P15, a sixteenth PMOS transistor P16, a seventeenth PMOS transistor P17, an eighteenth PMOS transistor P18, a nineteenth PMOS transistor P19, a twentieth PMOS transistor P20, twenty-first PMOS transistor P21, twenty-second PMOS transistor P22, eleventh NMOS transistor N11, twelfth NMOS transistor N12, thirteenth NMOS transistor N13, fourteenth NMOS transistor N14, fifteenth NMOS Tube N15, sixteenth NMOS tube N16, seventeenth NMOS tube N17, eighteenth NMOS tube N18, nineteenth NMOS tube N19, twentieth NMOS tube N20, twenty-first NMOS tube N21, twenty-second NMOS transistor N22, the sixth resistor R6, the seventh resistor R7 and the second bias current source Ibias2; wherein,

The gate of the eleventh NMOS transistor N11 is the non-inverting input terminal of the third amplifier AMP3, the drain is connected to the source of the fifteenth PMOS transistor P15 and the drain of the eighteenth PMOS transistor P18, and the source is connected to the twelfth NMOS transistor P18. The source of the transistor N12 is connected to the drain of the fourteenth NMOS transistor N14, the gate of the twelfth NMOS transistor N12 is the reverse input terminal of the third amplifier AMP3, and the drain is connected to the source of the sixteenth PMOS transistor P16 and the first Seventeen PMOS transistor P17 drain connection;

The gate of the seventeenth PMOS transistor P17, the gate of the eighteenth PMOS transistor P18, the gate of the twentieth PMOS transistor P20, the gate and the drain of the nineteenth PMOS transistor P19 and the twenty-first PMOS transistor P21 The gate of the fifteenth PMOS transistor P15, the gate of the sixteenth PMOS transistor P16, the gate of the twenty-second PMOS transistor P22, the gate and drain of the twenty-first PMOS transistor P21 are connected to The anode of the second bias current source Ibias2 is connected, and the drain of the twentieth PMOS transistor P20 is connected to the source of the twenty-second PMOS transistor P22;

The gate and drain of the thirteenth NMOS transistor N13, the gate of the fourteenth NMOS transistor N14, one end of the sixth resistor R6 are connected to the drain of the twenty-second PMOS transistor P22, and the source of the thirteenth NMOS transistor N13 pole and the drain of the fifteenth NMOS transistor N15, the drain of the thirteenth NMOS transistor N13, the other end of the sixth resistor R6, the gate of the fifteenth NMOS transistor N15, and the gate of the sixteenth NMOS transistor N16 connection, the source of the fourteenth NMOS transistor N14 is connected to the drain of the sixteenth NMOS transistor N16;

The gate and drain of the seventeenth NMOS transistor N17, the gate of the eighteenth NMOS transistor N18, one end of the seventh resistor R7 are connected to the drain of the twenty-second PMOS transistor P22, and the source of the seventeenth NMOS transistor N17 pole and the drain of the nineteenth NMOS transistor N19, the drain of the seventeenth NMOS transistor N17, the other end of the seventh resistor R7, the gate of the nineteenth NMOS transistor N19 and the gate of the twentieth NMOS transistor N20 connection, the source of the eighteenth NMOS transistor N18 is connected to the drain of the twentieth NMOS transistor N20;

The drain of the sixteenth PMOS transistor P16 and the source of the eighteenth NMOS transistor N18 are connected as the output terminal of the third amplifier AMP3;

The source of the seventeenth PMOS transistor P17, the source of the eighteenth PMOS transistor P18, the source of the nineteenth PMOS transistor P19, the source of the twentieth PMOS transistor P20 and the substrates of all PMOS transistors are connected to the power supply VDD ;

The cathode of the second bias current source Ibias2, the source of the fifteenth NMOS transistor N15, the source of the sixteenth NMOS transistor N16, the source of the nineteenth NMOS transistor N19, the source of the twentieth NMOS transistor N20 and The substrates of all NMOS transistors are grounded.

The beneficial effect of the present invention is that, compared with the traditional error amplifier, the present invention proposes a novel error amplifier structure, which uses two transconductance amplifiers to convert the voltage into current, and mirrors them to two current sources respectively, realizing respectively Sink/pull current to capacitor C1 to adjust the output voltage, improve the response speed and accuracy of the system, increase the stability of the system, and the input transconductance is constant, the output resistance and low-frequency gain are within the appropriate range, and the power supply is suppressed The ratio is high, the offset voltage is small, and the output voltage can be effectively locked.

Description of drawings

Fig. 1 is a schematic structural diagram of a traditional error amplifier circuit;

Fig. 2 is the logical block diagram of error amplifier circuit of the present invention;

Fig. 3 is the circuit structural representation of error amplifier circuit of the present invention;

Fig. 4 is the schematic diagram of the circuit structure of the first amplifier AMP1 of the present invention;

FIG. 5 is a schematic diagram of the circuit structure of the third amplifier AMP3 of the present invention.

Detailed ways

Below in conjunction with accompanying drawing, describe technical scheme of the present invention in detail:

As shown in Fig. 2, a kind of error amplifier circuit described in the present invention includes a first transconductance amplifier, a second transconductance amplifier, a first mirror current, a second mirror current and a first capacitor C1, the first transconductance The input terminal of the conductance amplifier is the first input terminal Vref of the error amplifier circuit, the output terminal is connected to the first mirror current, the input terminal of the second transconductance amplifier is the second input terminal Vin of the error amplifier circuit, and the output terminal is connected to the second For the mirror current, the output terminal of the first mirror current and the output terminal of the second mirror current are connected to one terminal of the first capacitor C1 as the output terminal Vea of the error amplifier circuit, and the other terminal of the first capacitor C1 is grounded.

As shown in Figure 3, the first transconductance amplifier includes a first operational amplifier AMP1, a second capacitor C2, a first resistor R1 and a first NMOS transistor N1, and the second transconductance amplifier includes a second operational amplifier AMP2, a third operational amplifier AMP3, the third capacitor C3, the second resistor R2, the third resistor R3, the fourth resistor R4 and the second NMOS transistor N2, the first mirror current includes the first PMOS transistor P1, the second PMOS transistor P2, and the third PMOS transistor P3 and the fourth PMOS transistor P4, the second mirror current includes the third NMOS transistor N3, the fourth NMOS transistor N4, the fifth NMOS transistor N5 and the sixth NMOS transistor N6; wherein,

The non-inverting input terminal of the first operational amplifier AMP1 is the first input terminal Vref of the error amplifier circuit, the inverting input terminal is connected to one end of the first resistor R1 and the source of the first NMOS transistor N1, and the output terminal is connected to the second capacitor C2 One end of is connected to the gate of the first NMOS transistor N1;

The non-inverting input terminal of the second operational amplifier AMP2 is the second input terminal Vin of the error amplifier circuit, the inverting input terminal is connected to one end of the fourth resistor R4 and the source of the second NMOS transistor N2, and the output terminal is connected to the third capacitor C3 One end of is connected to the gate of the second NMOS transistor N2;

The drain of the second NMOS transistor N2 and one end of the second resistor R2 are connected to the inverting input end of the third operational amplifier AMP3, and one end of the third resistor R3 and the drain of the third NMOS transistor N3 are connected to the same terminal of the third operational amplifier AMP3. To the input end, the output end of the third operational amplifier AMP3 is connected to the gate of the third NMOS transistor N3 and the gate of the fourth NMOS transistor N4;

The gate and drain of the first PMOS transistor P1 are connected to the drain of the first NMOS transistor N1 and the gate of the second PMOS transistor P2, the source is connected to the drain of the third PMOS transistor P3, and the gate of the third PMOS transistor P3 , the gate and drain of the fourth PMOS transistor P4 are connected to the source of the second PMOS transistor P2;

The drain of the second PMOS transistor P2, the source of the fourth NMOS transistor N4 and one end of the first capacitor C1 are connected as the output terminal Vea of the error amplifier circuit;

The source of the third NMOS transistor N3 is connected to the drain of the fifth NMOS transistor N5, the source of the fourth NMOS transistor N4, the gate of the fifth NMOS transistor N5, and the gate and drain of the sixth NMOS transistor N6 are connected;

The source of the third PMOS transistor P3, the source of the fourth PMOS transistor P4, the other end of the second resistor R2, the other end of the third resistor R3 and the substrates of all PMOS transistors are connected to the power supply VDD;

The other end of the first resistor R1, the other end of the second capacitor C2, the other end of the third capacitor C3, the other end of the fourth resistor R4, the source of the fifth NMOS transistor N5, the source of the sixth NMOS transistor N6 and The substrates of all NMOS transistors are grounded.

As shown in FIG. 4, the first operational amplifier AMP1 includes a fifth PMOS transistor P5, a sixth PMOS transistor P6, a seventh PMOS transistor P7, an eighth PMOS transistor P8, a ninth PMOS transistor P9, a tenth PMOS transistor P10, a tenth PMOS transistor One PMOS transistor P11, the twelfth PMOS transistor P12, the thirteenth PMOS transistor P13, the fourteenth PMOS transistor P14, the seventh NMOS transistor N7, the eighth NMOS transistor N8, the ninth NMOS transistor N9, the tenth NMOS transistor N10, The fifth resistor R5 and the first bias current source Ibias1; wherein,

The fifth PMOS transistor P5 and the sixth PMOS transistor P6 form a PMOS input differential pair, the gate of the fifth PMOS transistor P5 is connected to the same-inverting input terminal of the first operational amplifier AMP1, and the drain is connected to the source of the seventh NMOS transistor N7 and the The drains of the eight NMOS transistors N8, the gate of the sixth PMOS transistor P6 are connected to the inverting input terminal of the operational amplifier AMP, and the drains are connected to the source of the ninth NMOS transistor N9 and the drain of the tenth NMOS transistor N10;

The drain of the seventh NMOS transistor N7 is connected to one end of the fifth resistor R5, the gate of the eighth NMOS transistor N8, and the gate of the ninth NMOS transistor N9, and the other end of the fifth resistor R5 is connected to the gate of the seventh NMOS transistor N7 , the gate of the eighth NMOS transistor N8 and the drain of the seventh PMOS transistor P7;

The gate of the seventh PMOS transistor P7, the gate of the eighth PMOS transistor P8, the gate of the fourteenth PMOS transistor P14, the gate and the drain of the twelfth PMOS transistor P12, and the anode of the first bias current source Ibias1 The source of the twelfth PMOS transistor P12 is connected to the drain and gate of the eleventh PMOS transistor P11, the gate of the thirteenth PMOS transistor P13, the gate of the ninth PMOS transistor P9, and the gate of the tenth PMOS transistor P10 Gate connection, the drain of the thirteenth PMOS transistor P13 is connected to the source of the fourteenth PMOS transistor P14, the drain of the fourteenth PMOS transistor P14 is connected to the source of the fifth PMOS transistor P5 and the source of the sixth PMOS transistor P6 source connection;

The source of the seventh PMOS transistor P7 is connected to the drain of the ninth PMOS transistor P9, and the source of the eighth PMOS transistor P8 is connected to the drain of the tenth PMOS transistor P10;

The drain of the eighth PMOS transistor P8 and the source of the tenth NMOS transistor N10 are connected as the output end of the first operational amplifier AMP1;

The source of the ninth PMOS transistor P9, the source of the tenth PMOS transistor P10, the source of the eleventh PMOS transistor P11, the source of the thirteenth PMOS transistor P13 and the substrates of all PMOS transistors are connected to the power supply VDD;

The cathode of the first bias current source Ibias1 , the source of the eighth NMOS transistor N8 , the source of the ninth NMOS transistor N9 and the substrates of all NMOS transistors are grounded to GND.

The structure of the second amplifier AMP2 is the same as that of the first operational amplifier AMP1, and the specific structure is the same as that of the first operational amplifier AMP1 described above in the present invention, which will not be repeated here.

As shown in FIG. 5, the third amplifier AMP3 includes a fifteenth PMOS transistor P15, a sixteenth PMOS transistor P16, a seventeenth PMOS transistor P17, an eighteenth PMOS transistor P18, a nineteenth PMOS transistor P19, and a twentieth PMOS transistor. Tube P20, twenty-first PMOS tube P21, twenty-second PMOS tube P22, eleventh NMOS tube N11, twelfth NMOS tube N12, thirteenth NMOS tube N13, fourteenth NMOS tube N14, fifteenth NMOS tube N15, sixteenth NMOS tube N16, seventeenth NMOS tube N17, eighteenth NMOS tube N18, nineteenth NMOS tube N19, twenty-first NMOS tube N20, twenty-first NMOS tube N21, twenty-first Two NMOS transistors N22, the sixth resistor R6, the seventh resistor R7 and the second bias current source Ibias2; wherein,

The gate of the eleventh NMOS transistor N11 is the non-inverting input terminal of the third amplifier AMP3, the drain is connected to the source of the fifteenth PMOS transistor P15 and the drain of the eighteenth PMOS transistor P18, and the source is connected to the twelfth NMOS transistor P18. The source of the transistor N12 is connected to the drain of the fourteenth NMOS transistor N14, the gate of the twelfth NMOS transistor N12 is the reverse input terminal of the third amplifier AMP3, and the drain is connected to the source of the sixteenth PMOS transistor P16 and the first Seventeen PMOS transistor P17 drain connection;

The gate of the seventeenth PMOS transistor P17, the gate of the eighteenth PMOS transistor P18, the gate of the twentieth PMOS transistor P20, the gate and the drain of the nineteenth PMOS transistor P19 and the twenty-first PMOS transistor P21 The gate of the fifteenth PMOS transistor P15, the gate of the sixteenth PMOS transistor P16, the gate of the twenty-second PMOS transistor P22, the gate and drain of the twenty-first PMOS transistor P21 are connected to The anode of the second bias current source Ibias2 is connected, and the drain of the twentieth PMOS transistor P20 is connected to the source of the twenty-second PMOS transistor P22;

The gate and drain of the thirteenth NMOS transistor N13, the gate of the fourteenth NMOS transistor N14, one end of the sixth resistor R6 are connected to the drain of the twenty-second PMOS transistor P22, and the source of the thirteenth NMOS transistor N13 pole and the drain of the fifteenth NMOS transistor N15, the drain of the thirteenth NMOS transistor N13, the other end of the sixth resistor R6, the gate of the fifteenth NMOS transistor N15, and the gate of the sixteenth NMOS transistor N16 connection, the source of the fourteenth NMOS transistor N14 is connected to the drain of the sixteenth NMOS transistor N16;

The gate and drain of the seventeenth NMOS transistor N17, the gate of the eighteenth NMOS transistor N18, one end of the seventh resistor R7 are connected to the drain of the twenty-second PMOS transistor P22, and the source of the seventeenth NMOS transistor N17 pole and the drain of the nineteenth NMOS transistor N19, the drain of the seventeenth NMOS transistor N17, the other end of the seventh resistor R7, the gate of the nineteenth NMOS transistor N19 and the gate of the twentieth NMOS transistor N20 connection, the source of the eighteenth NMOS transistor N18 is connected to the drain of the twentieth NMOS transistor N20;

The drain of the sixteenth PMOS transistor P16 and the source of the eighteenth NMOS transistor N18 are connected as the output terminal of the third amplifier AMP3;

The source of the seventeenth PMOS transistor P17, the source of the eighteenth PMOS transistor P18, the source of the nineteenth PMOS transistor P19, the source of the twentieth PMOS transistor P20 and the substrates of all PMOS transistors are connected to the power supply VDD ;

The cathode of the second bias current source Ibias2, the source of the fifteenth NMOS transistor N15, the source of the sixteenth NMOS transistor N16, the source of the nineteenth NMOS transistor N19, the source of the twentieth NMOS transistor N20 and The substrates of all NMOS transistors are grounded.

Working principle and flow process of the present invention are:

For the convenience of description, the first mirror current in the following content is a constant mirror current source, and the second mirror current is a controlled mirror current sink.

第二电容C2的作用是降低环路主极点的频率，使相位裕度达到60deg。PMOS管P1至P4所构成的电路为威尔逊电流镜，为恒定镜像电流源，它的目的是将电流I₁进行精确的放大，并且提供一个很大的输出电阻。其威尔逊电流镜输出电阻表达式为R_out＝r_o3.(1+g_m3.r_o4)。The first transconductance amplifier converts the input voltage signal V _ref into current I ₁ , we consider that the gain of the first operational amplifier AMP1 is large enough, and the output current

The function of the second capacitor C2 is to reduce the frequency of the main pole of the loop, so that the phase margin reaches 60deg. The circuit formed by PMOS transistors P1 to P4 is a Wilson current mirror, which is a constant mirror current source. Its purpose is to accurately amplify the current I ₁ and provide a large output resistance. The expression of the output resistance of the Wilson current mirror is R _out =r _o3 .(1+g _m3 .r _o4 ).

The design of the second operational amplifier AMP2 in the second transconductance amplifier is exactly the same as that of the first operational amplifier AMP1 in the first transconductance amplifier, because this can make the input of the constant mirror current source and the controlled mirror current sink as symmetrical as possible , to reduce the input offset voltage of the error amplifier.

第三电容C3的作用是降低环路主极点的频率，使相位裕度达到60deg。第三运算放大器AMP3的作用是通过电流采样电压求和负反馈，将I₂精确复制到NMOS管构成的威尔逊电流源的输入电流I₃，其中I₄＝I₃＝I₂。并通过威尔逊电流源输出，达到与镜像电流源电路匹配的目的。The second transconductance amplifier converts the input voltage signal V _ref into the current I ₄ . Similarly, we consider that the gain of the second operational amplifier AMP2 is large enough, and the output current

The function of the third capacitor C3 is to reduce the frequency of the main pole of the loop, so that the phase margin reaches 60deg. The function of the third operational amplifier AMP3 is to accurately copy I ₂ to the input current I ₃ of the Wilson current source composed of NMOS transistors through current sampling and voltage summing negative feedback, where I ₄ =I ₃ =I ₂ . And output through the Wilson current source to achieve the purpose of matching with the mirror current source circuit.

The output current I _source of the constant mirror current source is compared with the output current I _sink of the controlled mirror current sink, and the first capacitor C1 is charged or discharged, thereby changing the voltage of the output terminal V _{ea of} the error amplifier.

In conclusion, it can be seen that the structure of the error amplifier of the present invention is novel, and the output voltage is adjusted by charging and discharging the first capacitor C1 by comparing the currents of the mirror current source and the mirror current sink, which improves the response speed and precision of the system and increases the system stability. And the input transconductance is constant, the output resistance and low-frequency gain are within the appropriate range, the power supply rejection ratio is high, the offset voltage is small, and the output voltage can be effectively locked.

Claims (5)

1. An error amplifier circuit is characterized by comprising a first transconductance amplifier, a second transconductance amplifier, a first mirror current, a second mirror current and a first capacitor C1, wherein the input end of the first transconductance amplifier is a first input end Vref of the error amplifier circuit, the output end of the first mirror current is connected with the first mirror current, the input end of the second transconductance amplifier is a second input end Vin of the error amplifier circuit, the output end of the second mirror current is connected with the second mirror current, the output end of the first mirror current and the output end of the second mirror current are connected with one end of a first capacitor C1 to serve as an output end Vea of the error amplifier circuit, and the other end of the first capacitor C1 is grounded.

2. The error amplifier circuit of claim 1, wherein the first transconductance amplifier comprises a first operational amplifier AMP1, a second capacitor C2, a first resistor R1, and a first NMOS transistor N1, wherein the second transconductance amplifier comprises a second operational amplifier AMP2, a third operational amplifier AMP3, a third capacitor C3, a second resistor R2, a third resistor R3, a fourth resistor R4, and a second NMOS transistor N2, wherein the first mirror current comprises a first PMOS transistor P1, a second PMOS transistor P2, a third PMOS transistor P3, and a fourth PMOS transistor P4, wherein the second mirror current comprises a third NMOS transistor N3, a fourth NMOS transistor N4, a fifth NMOS transistor N5, and a sixth NMOS transistor N6; wherein,

the same-direction input end of the first operational amplifier AMP1 is a first input end Vref of the error amplifier circuit, the reverse-direction input end is connected with one end of a first resistor R1 and the source electrode of a first NMOS transistor N1, and the output end is connected with one end of a second capacitor C2 and the grid electrode of the first NMOS transistor N1;

the same-direction input end of the second operational amplifier AMP2 is a second input end Vin of the error amplifier circuit, the reverse-direction input end is connected with one end of a fourth resistor R4 and the source electrode of the second NMOS transistor N2, and the output end is connected with one end of a third capacitor C3 and the grid electrode of the second NMOS transistor N2;

the drain electrode of the second NMOS transistor N2 and one end of the second resistor R2 are connected with the inverting input end of the third operational amplifier AMP3, one end of the third resistor R3 and the drain electrode of the third NMOS transistor N3 are connected with the homonymous input end of the third operational amplifier AMP3, and the output end of the third operational amplifier AMP3 is connected with the gate electrode of the third NMOS transistor N3 and the gate electrode of the fourth NMOS transistor N4;

the grid and the drain of a first PMOS tube P1 are connected with the drain of a first NMOS tube N1 and the grid of a second PMOS tube P2, the source is connected with the drain of a third PMOS tube P3, the grid and the drain of the third PMOS tube P3 and the grid and the drain of a fourth PMOS tube P4 are connected with the source of a second PMOS tube P2;

the drain electrode of the second PMOS tube P2, the source electrode of the fourth NMOS tube N4 and one end of the first capacitor C1 are connected to serve as the output end Vea of the error amplifier circuit;

the source electrode of the third NMOS transistor N3 is connected with the drain electrode of the fifth NMOS transistor N5, the source electrode of the fourth NMOS transistor N4, the grid electrode of the fifth NMOS transistor N5 and the grid electrode and the drain electrode of the sixth NMOS transistor N6 are connected;

the source electrode of the third PMOS tube P3, the source electrode of the fourth PMOS tube P4, the other end of the second resistor R2, the other end of the third resistor R3 and the substrates of all the PMOS tubes are connected with a power supply VDD;

the other end of the first resistor R1, the other end of the second capacitor C2, the other end of the third capacitor C3, the other end of the fourth resistor R4, the source of the fifth NMOS transistor N5, the source of the sixth NMOS transistor N6 and the substrates of all the NMOS transistors are grounded.

3. The error amplifier circuit as claimed in claim 2, wherein the first operational amplifier AMP1 comprises a fifth PMOS transistor P5, a sixth PMOS transistor P6, a seventh PMOS transistor P7, an eighth PMOS transistor P8, a ninth PMOS transistor P9, a tenth PMOS transistor P10, an eleventh PMOS transistor P11, a twelfth PMOS transistor P12, a thirteenth PMOS transistor P13, a fourteenth PMOS transistor P14, a seventh NMOS transistor N7, an eighth NMOS transistor N8, a ninth NMOS transistor N9, a tenth NMOS transistor N10, a fifth resistor R5 and a first bias current source Ibias 1; wherein,

the grid electrode of the fifth PMOS pipe P5 is connected with the same-direction input end of the first operational amplifier AMP1, the drain electrode of the fifth PMOS pipe P5 is connected with the source electrode of the seventh NMOS pipe N7 and the drain electrode of the eighth NMOS pipe N8, the grid electrode of the sixth PMOS pipe P6 is connected with the reverse-direction input end of the operational amplifier AMP, and the drain electrode of the sixth PMOS pipe P6 is connected with the source electrode of the ninth NMOS pipe N9 and the drain electrode of the tenth NMOS pipe N10;

the drain electrode of the seventh NMOS transistor N7 is connected with one end of a fifth resistor R5, the gate electrode of an eighth NMOS transistor N8 and the gate electrode of a ninth NMOS transistor N9, and the other end of the fifth resistor R5 is connected with the gate electrode of a seventh NMOS transistor N7, the gate electrode of an eighth NMOS transistor N8 and the drain electrode of a seventh PMOS transistor P7;

the grid electrode of the seventh PMOS tube P7, the grid electrode of the eighth PMOS tube P8, the grid electrode of the fourteenth PMOS tube P14, the grid electrode and the drain electrode of the twelfth PMOS tube P12 and the anode of the first bias current source Ibias1 are connected, the source electrode of the twelfth PMOS tube P12 is connected with the drain electrode and the grid electrode of the eleventh PMOS tube P11, the grid electrode of the thirteenth PMOS tube P13, the grid electrode of the ninth PMOS tube P9 and the grid electrode of the tenth PMOS tube P10, the drain electrode of the thirteenth PMOS tube P13 is connected with the source electrode of the fourteenth PMOS tube P14, and the drain electrode of the fourteenth PMOS tube P14 is connected with the source electrode of the fifth PMOS tube P5 and the source electrode of the sixth PMOS tube P6;

the source electrode of the seventh PMOS tube P7 is connected with the drain electrode of the ninth PMOS tube P9, and the source electrode of the eighth PMOS tube P8 is connected with the drain electrode of the tenth PMOS tube P10;

the drain electrode of the eighth PMOS transistor P8 and the source electrode of the tenth NMOS transistor N10 are connected as the output end of the first operational amplifier AMP 1;

the source electrode of the ninth PMOS tube P9, the source electrode of the tenth PMOS tube P10, the source electrode of the eleventh PMOS tube P11, the source electrode of the thirteenth PMOS tube P13 and the substrates of all the PMOS tubes are connected with a power supply VDD;

the cathode of the first bias current source Ibias1, the source of the eighth NMOS transistor N8, the source of the ninth NMOS transistor N9, and the substrates of all the NMOS transistors are grounded GND.

4. The error amplifier circuit of claim 3, wherein the second amplifier AMP2 and the first operational amplifier AMP1 are identical in structure.

5. The error amplifier circuit of claim 4, wherein the third amplifier AMP3 comprises a fifteenth PMOS transistor P15, a sixteenth PMOS transistor P16, a seventeenth PMOS transistor P17, an eighteenth PMOS transistor P18, a nineteenth PMOS transistor P19, a twentieth PMOS transistor P20, a twenty-first PMOS transistor P21, a twenty-second PMOS transistor P22, an eleventh NMOS transistor N11, a twelfth NMOS transistor N12, a thirteenth NMOS transistor N13, a fourteenth NMOS transistor N14, a fifteenth NMOS transistor N15, a sixteenth NMOS transistor N16, a seventeenth NMOS transistor N17, an eighteenth NMOS transistor N18, a nineteenth NMOS transistor N19, a twentieth NMOS transistor N20, a twenty-first NMOS transistor N21, a twenty-second NMOS transistor N22, a sixth resistor R6, a seventh resistor R7 and a second bias current source Ibias 2; wherein,

the gate of the eleventh NMOS transistor N11 is the same-direction input end of the third amplifier AMP3, the drain is connected to the source of the fifteenth PMOS transistor P15 and the drain of the eighteenth PMOS transistor P18, the source is connected to the source of the twelfth NMOS transistor N12 and the drain of the fourteenth NMOS transistor N14, the gate of the twelfth NMOS transistor N12 is the opposite-direction input end of the third amplifier AMP3, and the drain is connected to the source of the sixteenth PMOS transistor P16 and the drain of the seventeenth PMOS transistor P17;

the grid electrode of a seventeenth PMOS tube P17, the grid electrode of an eighteenth PMOS tube P18, the grid electrode of a twentieth PMOS tube P20, the grid electrode and the drain electrode of a nineteenth PMOS tube P19 are connected with the source electrode of a twenty-first PMOS tube P21, the grid electrode of a fifteenth PMOS tube P15, the grid electrode of a sixteenth PMOS tube P16, the grid electrode of a twenty-second PMOS tube P22, the grid electrode and the drain electrode of the twenty-first PMOS tube P21 are connected with the positive electrode of a second bias current source Ibias2, and the drain electrode of the twentieth PMOS tube P20 is connected with the source electrode of a twenty-second PMOS tube P22;

the grid and the drain of a thirteenth NMOS tube N13, the grid of a fourteenth NMOS tube N14, one end of a sixth resistor R6 and the drain of a twenty-second PMOS tube P22 are connected, the source of the thirteenth NMOS tube N13 and the drain of a fifteenth NMOS tube N15 are connected, the drain of the thirteenth NMOS tube N13, the other end of the sixth resistor R6, the grid of the fifteenth NMOS tube N15 and the grid of a sixteenth NMOS tube N16 are connected, and the source of the fourteenth NMOS tube N14 and the drain of the sixteenth NMOS tube N16 are connected;

the grid and the drain of a seventeenth NMOS transistor N17, the grid of an eighteenth NMOS transistor N18, one end of a seventh resistor R7 are connected with the drain of a twenty-second PMOS transistor P22, the source of the seventeenth NMOS transistor N17 is connected with the drain of a nineteenth NMOS transistor N19, the drain of a seventeenth NMOS transistor N17, the other end of the seventh resistor R7, the grid of the nineteenth NMOS transistor N19 is connected with the grid of a twenty NMOS transistor N20, and the source of the eighteenth NMOS transistor N18 is connected with the drain of a twentieth NMOS transistor N20;

the drain electrode of the sixteenth PMOS tube P16 and the source electrode of the eighteenth NMOS tube N18 are connected as the output end of a third amplifier AMP 3;

the source electrode of the seventeenth PMOS tube P17, the source electrode of the eighteenth PMOS tube P18, the source electrode of the nineteenth PMOS tube P19, the source electrode of the twentieth PMOS tube P20 and the substrates of all the PMOS tubes are connected with a power supply VDD;

the cathode of the second bias current source Ibias2, the source of the fifteenth NMOS transistor N15, the source of the sixteenth NMOS transistor N16, the source of the nineteenth NMOS transistor N19, the source of the twentieth NMOS transistor N20 and the substrates of all the NMOS transistors are grounded.

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