CN115173817A - Differential amplification circuit, error amplification circuit and trimming method thereof - Google Patents
Differential amplification circuit, error amplification circuit and trimming method thereof Download PDFInfo
- Publication number
- CN115173817A CN115173817A CN202211075684.2A CN202211075684A CN115173817A CN 115173817 A CN115173817 A CN 115173817A CN 202211075684 A CN202211075684 A CN 202211075684A CN 115173817 A CN115173817 A CN 115173817A
- Authority
- CN
- China
- Prior art keywords
- current mirror
- voltage
- differential pair
- coupled
- differential
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
- H03F1/30—Modifications of amplifiers to reduce influence of variations of temperature or supply voltage or other physical parameters
- H03F1/301—Modifications of amplifiers to reduce influence of variations of temperature or supply voltage or other physical parameters in MOSFET amplifiers
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/45—Differential amplifiers
- H03F3/45071—Differential amplifiers with semiconductor devices only
- H03F3/45076—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier
- H03F3/45179—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier using MOSFET transistors as the active amplifying circuit
- H03F3/45273—Mirror types
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Amplifiers (AREA)
Abstract
The invention provides a differential amplification circuit, an error amplification circuit and a trimming method thereof, wherein the differential amplification circuit comprises a first differential pair and a second differential pair, wherein the second differential pair is coupled with the first differential pair, and the second differential pair generates trimming voltage with the same value and the opposite direction as the offset voltage by adjusting the input signal of the second differential pair so as to offset the influence of the offset voltage. The differential amplification circuit, the error amplification circuit and the trimming method thereof can generate trimming voltage which is equal to the offset voltage in value and opposite in direction so as to offset the offset voltage.
Description
Technical Field
The invention relates to the technical field of electronics, in particular but not exclusively to a differential amplification circuit, an error amplification circuit and a trimming method thereof.
Background
A differential amplifier is an electronic amplifier that amplifies the difference between the voltages at two inputs with a fixed gain. FIG. 1 is a schematic diagram of a differential amplifier, where INP and INN are input signals of the differential amplifier, V A ，V B The point is the output voltage. Theoretically, when INP and INN are equal, the output voltage V A -V B =0, but the impurity concentration in the transistor is different due to process manufacturing variations, resulting in different gate voltages required when the transistor is turned on, and an offset voltage exists, such that V A -V B Not equal to 0, so that the circuit does not meet the requirement.
In view of the above, there is a need to provide a new structure or control method to solve at least some of the above problems.
Disclosure of Invention
At least in view of one or more problems in the background art, the present invention provides a differential amplifier circuit, an error amplifier circuit, and a trimming method thereof, which can generate a trimming voltage having a value equal to an offset voltage and an opposite direction to offset the offset voltage.
According to a first aspect of the present invention, an error amplifying circuit includes:
a first differential pair;
and the second differential pair is coupled with the first differential pair and generates a trimming voltage to offset the offset voltage when the first differential pair outputs the offset voltage, wherein the trimming voltage is a voltage which is equal to the offset voltage in value and opposite in direction.
Optionally, a ratio of a transconductance of the first differential pair to a transconductance of the second differential pair is constant.
Optionally, the differential amplifier circuit further includes a first current mirror, where the first current mirror includes two bias currents, and the two bias currents respectively flow through the first differential pair and the second differential pair.
Optionally, the differential amplifier circuit further includes a control circuit, and the control circuit is configured to generate a first signal, so that the second differential pair generates the trimming voltage according to the first signal.
Optionally, the control circuit comprises: the numerical control circuit is used for generating a second signal to control the numerical value of the trimming voltage; and the direction control circuit is coupled with the numerical control circuit and used for generating a third signal so as to control the direction of the trimming voltage.
Optionally, the numerical control circuit includes a second current mirror, the second current mirror includes at least two paths of bias currents, and each path of bias current of the second current mirror has a different current value, each path of bias current of the second current mirror flows through a corresponding switch, flows to the same resistor through the switch, and when any one of the switches is turned on, the bias current of the second current mirror corresponding to the branch is turned on.
Optionally, current value ratios of the bias currents of the second current mirrors of the respective adjacent branches are equal.
Optionally, the direction control circuit comprises: the first switch Guan Oujie is coupled to a reference ground, when the first switch 5363 and the second switch are turned on, the direction of the output voltage of the second current mirror is maintained, and the first signal is generated and transmitted to the second differential pair; the third switching tube is coupled with the output voltage of the second current mirror, the fourth switching tube is coupled with reference ground, and when the first switching tube and the second switching tube are turned off, the third switching tube and the fourth switching tube are turned on, the direction of the output voltage of the second current mirror is changed, and the first signal is generated and transmitted to the second differential pair.
According to a second aspect of the present invention, an error amplification circuit includes the error amplification circuit of the first aspect.
Optionally, the error amplifying circuit further comprises: a third current mirror, one end of which is coupled to the input voltage; a fourth current mirror, one end of which is coupled to the third current mirror, and the other end of which is coupled to the first differential pair; and one end of the fifth current mirror is coupled with the fourth current mirror, and the other end of the fifth current mirror is coupled with the reference ground.
According to a third aspect of the present invention, a method for trimming an offset voltage of a differential amplifier circuit comprises the following steps:
when the offset voltage exists in the differential amplification circuit, a trimming voltage is generated to offset the offset voltage, wherein the trimming voltage is equal to the offset voltage in value and opposite in direction.
The differential amplification circuit provided by the embodiment of the invention comprises a first differential pair and a second differential pair, wherein the second differential pair is coupled with the first differential pair, and the second differential pair generates trimming voltage which is equal to the offset voltage in value and opposite to the offset voltage in direction by adjusting the input signal of the second differential pair so as to offset the influence of the offset voltage.
Drawings
The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the principles of the invention. In the drawings:
FIG. 1 shows a block diagram of a differential amplifier;
FIG. 2 shows a block diagram of a differential amplification circuit according to an embodiment of the invention;
FIG. 3 illustrates a block diagram of a differential amplification circuit coupled to a current mirror according to an embodiment of the present invention;
FIG. 4 shows a block diagram of a control circuit according to an embodiment of the invention;
FIG. 5 is a schematic diagram of an error amplifier circuit;
FIG. 6 is a diagram showing the internal structure of an error amplifying circuit according to an embodiment of the present invention;
description of reference numerals:
100. a first differential pair; 200. a second differential pair; 300. a first current mirror; 400. a second current mirror; 500. a third current mirror; 600. a fourth current mirror; 700. and a fifth current mirror.
Detailed Description
For a further understanding of the present invention, reference will now be made to the following preferred embodiments of the invention in conjunction with the examples, but it is to be understood that the description is intended to further illustrate the features and advantages of the invention and is not intended to limit the scope of the claims which follow.
The description in this section is for several exemplary embodiments only, and the present invention is not limited only to the scope of the embodiments described. Combinations of different embodiments, and substitutions of features from different embodiments, or similar prior art means may be substituted for or substituted for features of the embodiments shown and described.
The term "coupled" or "connected" in this specification includes both direct and indirect connections. An indirect connection is a connection made through an intermediate medium, such as a conductor, wherein the electrically conductive medium may contain parasitic inductance or parasitic capacitance, or through an intermediate circuit or component as described in the embodiments in the specification; indirect connections may also include connections through other active or passive devices that perform the same or similar function, such as connections through switches, signal amplification circuits, follower circuits, and so on. "plurality" or "plurality" means two or more.
Fig. 2 is a block diagram illustrating a differential amplifier circuit having a trimming function according to an embodiment of the present invention. The first differential pair 100 includes PM1 and PM2, and PM1 and PM2 are a pair of MOS transistors with similar parameters (please refer to the description of the background art for the reason that the parameters are not completely consistent). The sources of PM1 and PM2 are coupled to the input voltage VDD through the resistor R1, and the drains of PM1 and PM2 are coupled to the ground reference through the resistors R2 and R3, respectively, where the resistances of the resistors R2 and R3 are equal. The gates of PM1 and PM2 form the input terminals of the first differential pair 100, and when the voltages of the input signals INP and INN are significantly lower than VDD, PM1 and PM2 are turned on, and at this time, even though the input signals INP and INN have the same parameters, the currents flowing through the drains of PM1 and PM2 are different due to the non-perfect agreement between PM1 and PM2, so that V is A -V B ≠0，V A -V B Characterized by the offset voltage of the first differential pair 100. It should be understood that the above-mentioned PM1, PM2, etc. are only examples of PMOS transistors, and the above-mentioned PMOS transistors can be replaced by other transistors with conducting characteristics, such as transistors, NMOS transistors, etc., and the same applies hereinafter.
Similarly, the second differential pair 200 is shown to include PM3 and PM4, where PM3 and PM4 are a pair of MOS transistors with similar parameters. The sources of PM3 and PM4 are coupled to the input voltage VDD through the resistor R4, and the drains of PM3 and PM4 are coupled to the ground reference through the resistors R2 and R3, respectively (i.e., the inputs of the first differential pair 100 and the second differential pair 200 are coupled to each other). The gates of PM3 and PM4 form the inputs of the second differential pair 200, and the inputs of the second differential pair 200 are coupled to the first signals (i.e., TRIMP and TRIMN in fig. 2). It should be noted that the connection manner of the differential pair (i.e. the two-terminal input and the two-terminal output) is only shown as an example, and the differential pair may be replaced by another connection manner, such as: double-ended input single-ended output, single-ended input double-ended output, or single-ended input single-ended output.
In one embodiment, the gates of PM1 and PM2 are coupled to ground, and the offset voltage V exists in the first differential pair 100 A -V B (ii) a The gate of PM3 is coupled to the first signal, and the second differential pair 200 is controlled to output the trimming voltage V by adjusting the first signal B -V A The trimming voltage is equal to the offset voltage in magnitude and opposite in polarity. Under the combined action of the first differential pair 100 and the second differential pair 200, the voltages at the two ends of the output terminal of the first differential pair 100 are equal, i.e. the influence of the offset voltage of the first differential pair 100 is eliminated.
The differential amplifier circuit provided in the embodiment of the present invention includes a first differential pair 100 and a second differential pair 200, wherein output terminals of the first differential pair 100 and the second differential pair 200 are coupled to each other, and the second differential pair 200 generates a trimming voltage having a same value and an opposite direction to an offset voltage by adjusting an input signal of the second differential pair 200, so as to cancel an influence of the offset voltage.
Further, as shown in fig. 3, the differential amplifier circuit further includes a first current mirror 300, and the first current mirror 300 is used for providing stable current input to the sources of PM1, PM2, PM3, and PM 4. In one embodiment, the first current mirror 300 includes 3 current branches. A current branch includes a MOS transistor PM5, the PM5 is coupled to a constant current source, and the current flowing through the current branch is the reference current of the first current mirror 300; a current branch includes a MOS transistor PM6, PM6 is coupled to the first differential pair 100, and the current flowing through the current branch is the bias current of the first current mirror 300; a current branch includes a MOS transistor PM7, PM7 is coupled to the second differential pair 200, and the current flowing through the current branch is the other bias current of the first current mirror 300. Therefore, the source input currents of PM1, PM2, PM3, and PM4 are stable, and will not change with the fluctuation of the input voltage VDD, so as to reduce the external interference, and facilitate more accurate trimming of the offset voltage of the first differential pair 100.
In one embodiment, the ratio of the transconductance of the first differential pair 100 to the transconductance of the second differential pair 200 is constant. By setting the transconductance of PM1 and PM2 as gm1,2 and the transconductance of PM3 and PM4 as gm3,4, the current flowing through PM6 and PM7 and the size of PM1/2 and PM3/4 are set so that gm3,4/gm11,12 is a fixed proportion which does not change along with the process deviation, thus achieving higher trimming precision.
Further, the differential amplification circuit further comprises a control circuit, and the control circuit generates the first signal. Specifically, the control circuit includes a numerical control circuit that generates the second signal to control the value of the trimming voltage and a direction control circuit that generates the third signal to control the direction of the trimming voltage, as the name suggests. Thus, the first signal is a coupled signal of the second signal and the third signal.
In an embodiment, a second current mirror 400 is included, where the second current mirror 400 includes at least two bias currents, and the current value ratios of the bias currents of the adjacent branches are equal. Each path of bias current flows through the corresponding switch, and flows to the same resistor through the switch, and when any one of the switches is turned on, the bias current of the second current mirror 400 of the corresponding branch is turned on. In one embodiment, taking fig. 4 as an example, the second current mirror 400 includes 4 current branches. A current branch includes a MOS transistor PM8, PM8 is coupled to a constant current source, and the current flowing through the current branch is the reference current of the second current mirror 400; a current branch comprises a MOS transistor PM9, and the current flowing through the current branch is the 1st bias current of the second current mirror 400; a current branch comprises a MOS transistor PM10, and the current flowing through the current branch is the 2 nd bias current of the second current mirror 400; a current branch including the MOS transistor PM11 flows through the current branch as the 3 rd bias current of the second current mirror 400. The dimensions of PM9, PM10, and PM11 are set so that the ratio of the 1st path bias current, the 2 nd path bias current, and the 3 rd path bias current of the second current mirror 400 is 1. The switch is a transistor with a control function, and specifically comprises MOS transistors PM12, PM13 and PM14. Wherein, sources of PM12, PM13, and PM14 are respectively coupled to PM9, PM10, and PM11, and drains of PM12, PM13, and PM14 are coupled to the resistor R5; the gates of PM12, PM13, and PM14 are controlled by an external signal S1. The external signal S1 has 8 states, 000, 001, 010, 011, 100, 101, 110, and 111, respectively. 0 and 1 represent the state of the MOS transistor, 0 represents on, 1 represents off, so in 8 states the ratio of the voltage at point VR is 0. In an embodiment, referring to fig. 2 and 4, the direction control circuit includes a first switch transistor (fig. 4NM 1), a second switch transistor (fig. 4NM 2), a third switch transistor (fig. 4NM 3), and a fourth switch transistor (fig. 4NM 4), and maintains the direction of the output voltage of the second current mirror 400 when the first switch transistor and the second switch transistor are turned on; when the third switch and the fourth switch are turned on, the direction of the output voltage of the second current mirror 400 is changed. Specifically, the first switch tube, the second switch tube, the third switch tube and the fourth switch tube are MOS tubes, the first switch tube and the second switch tube are connected and disconnected with each other, and can be regarded as a switch tube group, and the third switch tube and the fourth switch tube are connected and disconnected with each other, and can be regarded as another switch tube group. The sources of NM1 and NM2 are coupled to the input terminals of the second differential pair 200, the drains of NM1 and NM2 are coupled to the node VR and the ground, respectively, and the gates of NM1 and NM2 are coupled to the external signal S2. The sources of NM3 and NM4 are coupled to the input terminal of the second differential pair 200, the drains of NM3 and NM4 are coupled to the reference ground and the point VR, respectively, and the gates of NM3 and NM4 are coupled to the external signal S2. The external signal S2 is a pair of pulses, which are a high level and a low level, respectively, when the gates of NM1 and NM2 are coupled to the high level, the gates of NM3 and NM4 are coupled to the low level, at this time, NM1 and NM2 are turned on, NM3 and NM4 are turned off, and the input terminal of the second differential pair 200 receives a forward voltage; when the gates of NM1 and NM2 are coupled to a low level, the gates of NM3 and NM4 are coupled to a high level, NM1 and NM2 are turned off, NM3 and NM4 are turned on, and the input terminal of the second differential pair 200 receives an inverted voltage. It is to be understood that the direction control circuit is equivalent to multiplying the voltage at VR by 1 or-1, and the ratio of the voltages received by the second differential pair 200 is extended to-7: -6: -4: -3: -2: -1.
An embodiment of the present invention further provides an error amplifying circuit, which includes the differential amplifying circuit. Fig. 5 shows a schematic diagram of an error amplifier circuit, where an output of the error amplifier circuit is coupled to one of the input terminals of the first differential pair 100, and the error amplifier INP-INN =0 in a theoretical closed-loop operation, but there is an offset (i.e., INP-INN ≠ 0) at both input terminals due to process manufacturing variations, which may cause a reduction in circuit accuracy, resulting in a circuit that is not satisfactory.
Fig. 6 shows an internal structure diagram of an error amplifying circuit, in which MOS transistors PM15, PM16, PM17, and PM18 form a third current mirror 500, and one end of the third current mirror 500 is coupled to an input voltage VDD; the MOS transistors NM5 and NM6 form a fourth current mirror 600, one end of the fourth current mirror 600 is coupled to the third current mirror 500, and the other end is coupled to the first differential pair 100; the MOS transistors NM7 and NM8 form a fifth current mirror 700, and the fifth current mirror 700 is coupled between the first differential pair 100 and the ground reference. Assume that the currents output from the output terminals of the first differential pair 100 are respectivelyI 1 AndI 2 the current flowing into the inflow terminals of the MOS transistors NM5 and NM6 is respectivelyI 3 AndI 4 the PM18 tube of the MOS tube flows current ofI 5 . So that the current at point A is (I 1 + I 3 ) The current at point B isI 2 + I 4 ). Because the branch circuit of point a and the branch circuit of point B form a current mirror, if NM7 and NM8 have the same parameters, the two currents are equal, including:I 1 + I 3 = I 2 +I 4 . Therefore, the value of the current flowing through NM6I 4 = I 1 + I 3 - I 2 The current value of OUT output isI 5 -( I 1 + I 3 - I 2 )= I 5 + I 2 - I 1 - I 3 The output voltage value is（I 5 + I 2 - I 1 - I 3 ）×RWhere R is the equivalent resistance of NM 6. It has been mentioned above that PM17 and PM18 constitute a current mirror, and if NM17 and NM18 have the same parameters, the current flowing from the current mirrorI 3 AndI 5 are equal, thereby simplifying the above equation, the voltage of the OUT output is（I 2 -I 1 ）×ROnly with respect to the current output at the output of the first differential pair 100.
Referring to fig. 6, the current difference between PM1 and PM2 is eliminated by the current difference on PM3, PM 4. When DIS _ TRIM is 1, the trimming part does not work; when DIS _ TRIM is 0, the trimming section starts to operate. The current difference between PM3 and PM4 is generated by TRIMP-TRIMN ≠ 0. Meanwhile, the transconductance of PM1 and PM2 is set as gm1,2, and the transconductance of PM3 and PM4 is set as gm3,4, so that the current of PM6 and PM7 and the size of PM1/2 and PM3/4 can be set, and gm1,2/gm3,4 is a fixed proportion which does not change along with process deviation, thereby achieving higher trimming precision. In fig. 4, the current through PM9-PM11 produces a voltage drop across resistor R5 to obtain a voltage. When the gates of NM1 and NM2 are coupled to a high level and the gates of NM3 and NM4 are coupled to a low level, TRIMP is connected to VR end and TRIMN is connected to ground, and TRIMP-TRIMN is greater than 0; when the gates of NM1 and NM2 are coupled to a low level and the gates of NM3 and NM4 are coupled to a high level, TRIMN is connected to VR terminal and TRIMP is connected to ground, and TRIMP-TRIMN is less than 0. The external signal S2 is used to adjust the trimming direction, when INP-INN >0 in FIG. 6, TRIMP-TRIMN <0; when INP-INN <0, let TRIMP-TRIMN >0.
After the trimming direction is determined, the trimming voltage value is controlled by an external signal S1, in one embodiment, PM10: PM11: PM12= 1ua.
Based on the same invention concept, an embodiment of the present invention further provides a method for adjusting an offset voltage of a differential amplification circuit, including the following steps: when the offset voltage exists in the differential amplification circuit, a trimming voltage is generated to offset the offset voltage, wherein the trimming voltage is equal to the offset voltage in value and opposite in direction.
Those skilled in the art should understand that the logic controls such as "high" and "low", "set" and "reset", "and gate" and "or gate", "non-inverting input" and "inverting input" in the logic controls referred to in the specification or the drawings may be exchanged or changed, and the subsequent logic controls may be adjusted to achieve the same functions or purposes as the above-mentioned embodiments.
The description and applications of the invention herein are illustrative and are not intended to limit the scope of the invention to the embodiments described above. The descriptions related to the effects or advantages in the specification may not be reflected in practical experimental examples due to uncertainty of specific condition parameters or influence of other factors, and the descriptions related to the effects or advantages are not used for limiting the scope of the invention. Variations and modifications of the embodiments disclosed herein are possible, and alternative and equivalent various components of the embodiments will be apparent to those skilled in the art. It will be clear to those skilled in the art that the present invention may be embodied in other forms, structures, arrangements, proportions, and with other components, materials, and parts, without departing from the spirit or essential characteristics thereof. Other variations and modifications of the embodiments disclosed herein may be made without departing from the scope and spirit of the invention.
Claims (11)
1. A differential amplification circuit, comprising:
a first differential pair;
and the second differential pair is coupled with the first differential pair and generates a trimming voltage to offset the offset voltage when the first differential pair outputs the offset voltage, wherein the trimming voltage is a voltage which is equal to the offset voltage in value and opposite in direction.
2. The differential amplification circuit of claim 1, wherein: the ratio of the transconductance of the first differential pair to the transconductance of the second differential pair is constant.
3. The differential amplification circuit of claim 1, wherein: the current mirror comprises two bias currents, and the two bias currents respectively flow through the first differential pair and the second differential pair.
4. The differential amplification circuit of claim 1, wherein: the second differential pair is used for generating a first signal, so that the second differential pair generates the trimming voltage according to the first signal.
5. The differential amplification circuit of claim 4, wherein the control circuit comprises:
the numerical control circuit is used for generating a second signal so as to control the numerical value of the trimming voltage;
and the direction control circuit is coupled with the numerical control circuit and used for generating a third signal so as to control the direction of the trimming voltage.
6. The differential amplification circuit of claim 5, wherein: the numerical control circuit comprises a second current mirror, the second current mirror at least comprises two paths of bias currents, the current values of the bias currents of the second current mirror are different, the bias currents of the second current mirror flow through corresponding switches, the bias currents flow to the same resistor through the switches, and when any one of the switches is switched on, the bias currents of the second current mirror corresponding to the branch circuits are switched on.
7. The differential amplification circuit of claim 6, wherein: and the current value ratios of the bias currents of the second current mirrors of the adjacent branches are equal.
8. The differential amplification circuit of claim 7, wherein the direction control circuit comprises:
the first switch Guan Oujie is coupled to a reference ground, when the first switch 5363 and the second switch are turned on, the direction of the output voltage of the second current mirror is maintained, and the first signal is generated and transmitted to the second differential pair;
the third switching tube is coupled with the output voltage of the second current mirror, the fourth switching tube is coupled with reference ground, and when the first switching tube and the second switching tube are turned off, the third switching tube and the fourth switching tube are turned on, the direction of the output voltage of the second current mirror is changed, and the first signal is generated and transmitted to the second differential pair.
9. An error amplification circuit, characterized by: a differential amplifying circuit comprising any of claims 1-8.
10. The error amplification circuit of claim 9, further comprising:
a third current mirror, one end of which is coupled to the input voltage;
a fourth current mirror, one end of which is coupled to the third current mirror, and the other end of which is coupled to the first differential pair;
and one end of the fifth current mirror is coupled with the fourth current mirror, and the other end of the fifth current mirror is coupled with the reference ground.
11. A method for trimming offset voltage of a differential amplification circuit comprises the following steps:
when the offset voltage exists in the differential amplification circuit, a trimming voltage is generated to offset the offset voltage, wherein the trimming voltage is equal to the offset voltage in value and opposite in direction.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202211075684.2A CN115173817B (en) | 2022-09-05 | 2022-09-05 | Differential amplification circuit, error amplification circuit and trimming method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202211075684.2A CN115173817B (en) | 2022-09-05 | 2022-09-05 | Differential amplification circuit, error amplification circuit and trimming method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN115173817A true CN115173817A (en) | 2022-10-11 |
| CN115173817B CN115173817B (en) | 2022-12-02 |
Family
ID=83481394
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202211075684.2A Active CN115173817B (en) | 2022-09-05 | 2022-09-05 | Differential amplification circuit, error amplification circuit and trimming method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN115173817B (en) |
Citations (15)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20060022753A1 (en) * | 2004-07-30 | 2006-02-02 | International Business Machines Corporation | Method and apparatus for controlling common-mode output voltage in fully differential amplifiers |
| US20060038618A1 (en) * | 2004-08-18 | 2006-02-23 | Binan Wang | Precision current mirror and method for voltage to current conversion in low voltage applications |
| CN102427360A (en) * | 2011-12-15 | 2012-04-25 | 湖南追日光电科技有限公司 | Circuit structure for reading orthogonal rotating current of Hall sensor |
| JP2012147361A (en) * | 2011-01-14 | 2012-08-02 | Olympus Corp | Operational amplification circuit |
| US20120286827A1 (en) * | 2011-05-13 | 2012-11-15 | Fuji Electric Co., Ltd. | Voltage-to-current converter circuit |
| CN103178789A (en) * | 2011-12-20 | 2013-06-26 | 西安航天民芯科技有限公司 | Low-temperature drift detuning self-calibration operational amplifier circuit and design method thereof |
| CN103414438A (en) * | 2013-07-18 | 2013-11-27 | 电子科技大学 | Error amplifier circuit |
| CN104639071A (en) * | 2013-11-07 | 2015-05-20 | 上海华虹宏力半导体制造有限公司 | Operational amplifier |
| CN109787558A (en) * | 2018-12-28 | 2019-05-21 | 合肥中感微电子有限公司 | Pierce circuit and its method for repairing and regulating |
| CN210075200U (en) * | 2019-07-05 | 2020-02-14 | 成都博思微科技有限公司 | Self-calibration comparator offset voltage elimination circuit |
| CN111625043A (en) * | 2020-06-29 | 2020-09-04 | 启攀微电子（上海）有限公司 | Adjustable ultra-low power consumption full CMOS reference voltage current generation circuit |
| CN112886931A (en) * | 2021-01-28 | 2021-06-01 | 深圳市万微半导体有限公司 | Digital weighted current source circuit for eliminating offset error of operational amplifier |
| CN114070213A (en) * | 2020-08-05 | 2022-02-18 | 圣邦微电子（北京）股份有限公司 | Operational amplifier |
| CN114499416A (en) * | 2021-12-16 | 2022-05-13 | 深圳芯盛微电子有限公司 | Operational amplifier circuit and chip |
| CN114915282A (en) * | 2022-07-15 | 2022-08-16 | 深圳市单源半导体有限公司 | Discharge circuit with stable power and method thereof |
-
2022
- 2022-09-05 CN CN202211075684.2A patent/CN115173817B/en active Active
Patent Citations (15)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20060022753A1 (en) * | 2004-07-30 | 2006-02-02 | International Business Machines Corporation | Method and apparatus for controlling common-mode output voltage in fully differential amplifiers |
| US20060038618A1 (en) * | 2004-08-18 | 2006-02-23 | Binan Wang | Precision current mirror and method for voltage to current conversion in low voltage applications |
| JP2012147361A (en) * | 2011-01-14 | 2012-08-02 | Olympus Corp | Operational amplification circuit |
| US20120286827A1 (en) * | 2011-05-13 | 2012-11-15 | Fuji Electric Co., Ltd. | Voltage-to-current converter circuit |
| CN102427360A (en) * | 2011-12-15 | 2012-04-25 | 湖南追日光电科技有限公司 | Circuit structure for reading orthogonal rotating current of Hall sensor |
| CN103178789A (en) * | 2011-12-20 | 2013-06-26 | 西安航天民芯科技有限公司 | Low-temperature drift detuning self-calibration operational amplifier circuit and design method thereof |
| CN103414438A (en) * | 2013-07-18 | 2013-11-27 | 电子科技大学 | Error amplifier circuit |
| CN104639071A (en) * | 2013-11-07 | 2015-05-20 | 上海华虹宏力半导体制造有限公司 | Operational amplifier |
| CN109787558A (en) * | 2018-12-28 | 2019-05-21 | 合肥中感微电子有限公司 | Pierce circuit and its method for repairing and regulating |
| CN210075200U (en) * | 2019-07-05 | 2020-02-14 | 成都博思微科技有限公司 | Self-calibration comparator offset voltage elimination circuit |
| CN111625043A (en) * | 2020-06-29 | 2020-09-04 | 启攀微电子（上海）有限公司 | Adjustable ultra-low power consumption full CMOS reference voltage current generation circuit |
| CN114070213A (en) * | 2020-08-05 | 2022-02-18 | 圣邦微电子（北京）股份有限公司 | Operational amplifier |
| CN112886931A (en) * | 2021-01-28 | 2021-06-01 | 深圳市万微半导体有限公司 | Digital weighted current source circuit for eliminating offset error of operational amplifier |
| CN114499416A (en) * | 2021-12-16 | 2022-05-13 | 深圳芯盛微电子有限公司 | Operational amplifier circuit and chip |
| CN114915282A (en) * | 2022-07-15 | 2022-08-16 | 深圳市单源半导体有限公司 | Discharge circuit with stable power and method thereof |
Non-Patent Citations (2)
| Title |
|---|
| BENDONG SUN等: "New low-voltage fully-balanced wide-band differential CMOS current amplifier", 《THE 2002 45TH MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS》 * |
| 王松林等: "一种采用改进自调零技术的误差放大器设计", 《复旦学报(自然科学版)》 * |
Also Published As
| Publication number | Publication date |
|---|---|
| CN115173817B (en) | 2022-12-02 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP3318725B2 (en) | Analog filter circuit | |
| US20070040607A1 (en) | Switched capacitor amplifier with higher gain and improved closed-loop gain accuracy | |
| KR100299740B1 (en) | Filter circuit | |
| US4888559A (en) | Correction arrangement for an amplifier | |
| US4868482A (en) | CMOS integrated circuit having precision resistor elements | |
| CN101002382A (en) | Current mode instrumentation amplifier | |
| JP2558027B2 (en) | Hysteresis circuit | |
| US20050184805A1 (en) | Differential amplifier circuit | |
| EP0930802A2 (en) | Microphone bias current measurement circuit | |
| US20080169847A1 (en) | Driver and driver/receiver system | |
| CN113504806B (en) | Current reference circuit, chip and electronic equipment | |
| CN115173817B (en) | Differential amplification circuit, error amplification circuit and trimming method thereof | |
| JPS62250706A (en) | Variable attenuator | |
| US6538513B2 (en) | Common mode output current control circuit and method | |
| JP3535836B2 (en) | Power amplifier circuit | |
| US20220337198A1 (en) | Amplifier circuit, corresponding device and method | |
| KR100499856B1 (en) | Variable gain amplifier | |
| EP0759230B1 (en) | Cmos programmable resistor-based transconductor | |
| JP2008028446A (en) | Highly precise pull-up/pull-down circuit | |
| JP4417673B2 (en) | Electric meter signal input circuit | |
| US20040113692A1 (en) | Opamp with infinite open loop gain | |
| US7492225B2 (en) | Gain-controlled amplifier | |
| CN117439560A (en) | Transimpedance amplifier circuit with stable bandwidth | |
| KR100341586B1 (en) | Bias Circuit | |
| JP4606770B2 (en) | Amplifier and reference voltage generation circuit |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |