CN103178789A - Low-temperature drift detuning self-calibration operational amplifier circuit and design method thereof - Google Patents
Low-temperature drift detuning self-calibration operational amplifier circuit and design method thereof Download PDFInfo
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Abstract
The invention relates to a low-temperature drift detuning self-calibration operational amplifier circuit and a design method of the low-temperature drift detuning self-calibration operational amplifier circuit. The low-temperature drift detuning self-calibration operational amplifier circuit comprises two gain units, a biased module, three capacitors, a current source, six switches, four P-type metal oxide semiconductor (MOS) pipes and five N-type MOS pipes, wherein each gain unit comprises a capacitor, two resistors, a switch, ten P-type MOS pipes and four N-type MOS pipes. A folded cascade structure is adopted to be used as a gain stage of an amplifier so that high voltage gain and a high power supply rejection ratio can be obtained. Due to the fact that the MOS capacitor is adopted to store, operate and amplify detuning information caused by technology variation, and the detuning information is successively and automatically calibrated when a closed loop is used, low direct current detuning is achieved. A lower temperature coefficient is achieved by adoption of a temperature compensation technology. A high drive capability is obtained by adoption of push-pull output of an AB class.
Description
Technical field
The invention belongs to field of power supplies, particularly a kind of Low Drift Temperature imbalance self calibration operation amplifier circuit and method for designing, it is mainly used in the DC/DC transducer; the AC/DC transducer, LED driver, D power-like amplifier; the high-accuracy current-limiting switch, battery protection chip etc.
Background technology
Consumer electronics market continuous expansion in recent years, ic power field be also in expansion at full speed, is accompanied by properties of product and requires more and more highlyer, and the performance requirement of power supply class IC is also more and more harsher.Be activated the puzzlement of scarce capacity as the nucleus module reference voltage source of all power source products always, adopt driving force that operational amplifier can improve reference voltage source as driving stage but because the imbalance of amplifier itself brings DC deviation to system, greatly affected the performance of system.
Summary of the invention
Order of the present invention ground is: a kind of Low Drift Temperature imbalance self calibration operation amplifier circuit and method for designing are provided, it greatly reduces the offset voltage of operational amplifier by the dynamic memory of error information, thereby greatly reduce the DC deviation of system under the prerequisite that guarantees the drives ability, improved the performance of system.
Technical scheme of the present invention is: a kind of Low Drift Temperature imbalance self calibration operation amplifier circuit and method for designing are provided, comprise gain stage and output stage, it is characterized in that: gain stage comprises gain unit AMP_CELL1, gain unit AMP_CELL2, and 6 switches; Output stage comprises: biasing module, three electric capacity, six switches, 4 P type metal-oxide-semiconductors and 5 the N-type metal-oxide-semiconductors that current source consists of,
Described gain unit AMP_CELL1 or gain unit AMP_CELL2 comprise: the end that an electric capacity, two resistance, a switch, 10 P type metal-oxide-semiconductors and 4 N-type metal-oxide-semiconductors, an end of the grid of the source electrode of the source electrode of a P type metal-oxide-semiconductor MP1, the 4th P type metal-oxide-semiconductor MP4, the grid of the 6th P type metal-oxide-semiconductor MP6, the 7th P type metal-oxide-semiconductor MP7, the source electrode of the 5th P type metal-oxide-semiconductor MP5, capacitor C, the source electrode of the 8th P type metal-oxide-semiconductor MP8 are connected with resistance R connects; The source electrode of the source electrode of the drain electrode of the one P type metal-oxide-semiconductor MP1, the 2nd P type metal-oxide-semiconductor MP2 and the 3rd P type metal-oxide-semiconductor MP3 connects; The grid of the 2nd P type metal-oxide-semiconductor MP2 is connected with the anode Vin+ of differential signal input, and the grid of the 3rd P type metal-oxide-semiconductor MP3 is connected with the negative terminal Vin-of differential signal input; The drain electrode of the drain electrode of the 2nd P type metal-oxide-semiconductor MP2, the source electrode of the 3rd N-type metal-oxide-semiconductor N3 and the tenth P type metal-oxide-semiconductor MP10 connects; The drain electrode of the drain electrode of the 3rd P type metal-oxide-semiconductor MP3, the source electrode of the 4th N-type metal-oxide-semiconductor N4 and the 9th P type metal-oxide-semiconductor MP9 connects; The grid of the grid of the 4th P type metal-oxide-semiconductor MP4 and the 5th P type metal-oxide-semiconductor MP5 connects; The grid of the grid of the 3rd N-type metal-oxide-semiconductor N3 and the 4th N-type metal-oxide-semiconductor N4 connects; The grid of the first N-type metal-oxide-semiconductor N1 be connected the grid of N-type metal-oxide-semiconductor N2 and connect; The end that the source electrode of the source electrode of the first N-type metal-oxide-semiconductor N1, the second N-type metal-oxide-semiconductor N2 is connected with resistance R connects; One end of the grid of the 9th P type metal-oxide-semiconductor MP9, the other end of capacitor C, switch S 1 is connected with the single-ended signal output end vo; The source electrode of the source electrode of the drain electrode of the 8th P type metal-oxide-semiconductor MP8, the 9th P type metal-oxide-semiconductor MP9 and the tenth P type metal-oxide-semiconductor MP10 connects; The other end that the grid of the tenth P type metal-oxide-semiconductor MP10, the other end of resistance R 1 are connected with resistance R connects; The source electrode of the drain electrode of the 4th P type metal-oxide-semiconductor MP4 and the 6th P type metal-oxide-semiconductor MP6 connects; The source electrode of the drain electrode of the 5th P type metal-oxide-semiconductor MP5 and the 7th P type metal-oxide-semiconductor MP7 connects; The drain electrode of the drain electrode of the 6th P type metal-oxide-semiconductor MP6 and the 3rd N-type metal-oxide-semiconductor N3 connects; The other end that the drain electrode of the 7th P type metal-oxide-semiconductor MP7, the drain electrode of the 4th N-type metal-oxide-semiconductor N4 are connected with switch S connects.
Described gain unit comprises three grades:
The first order is transconductance stage, and transconductance stage comprises: a P type metal-oxide-semiconductor MP1, the 2nd P type metal-oxide-semiconductor MP2, the 3rd P type metal-oxide-semiconductor MP3; The one P type metal-oxide-semiconductor MP1 is the transconductance stage current source, and the 2nd P type metal-oxide-semiconductor MP2, the 3rd P type metal-oxide-semiconductor MP3 are P type differential pair tube, consists of the mutual conductance device of gain unit, and input voltage signal is converted into electric current;
The second level is impedance level, comprising: the 4th P type metal-oxide-semiconductor MP4, the 5th P type metal-oxide-semiconductor MP5, the 6th P type metal-oxide-semiconductor MP6, the 7th P type metal-oxide-semiconductor MP7, the first N-type metal-oxide-semiconductor MN1, the second N-type metal-oxide-semiconductor MN2, the 3rd N-type metal-oxide-semiconductor MN3, the 4th N-type metal-oxide-semiconductor MN4 form common-source common-gate current mirror; Impedance level is converted into voltage signal with current signal, and produces enough gains;
The third level is the error information storage level, comprising: the 8th P type metal-oxide-semiconductor MP8, the 9th P type metal-oxide-semiconductor MP9, the tenth P type metal-oxide-semiconductor MP10, and divider resistance R1, R2 provide the direct current biasing near VDD/2; The 8th P type metal-oxide-semiconductor MP8 is third level current source; The 9th P type metal-oxide-semiconductor MP9, the tenth P type metal-oxide-semiconductor MP10 are P type differential pair tube, be used for the offset voltage signal of storage is converted into current signal, and because offset voltage is often less, so the mutual conductance that the third level need to be less, so MP9, MP10 adopt than pipe.
The end that the inverting input Vin-of described the first gain unit AMP_CELL1, an end of switch S 2 are connected with switch S connects; One end of one end of the drain electrode of the other end of the other end of switch S 3, switch S 5, the 11 P type metal-oxide-semiconductor MP11, the drain electrode of the 11 N-type metal-oxide-semiconductor MN11, capacitor C 2, an end of capacitor C 3, capacitor C 4, output end vo connect; The end that the inverting input Vin-of gain unit AMP_CELL2, an end of switch S 4 are connected with switch S connects; The other end of the in-phase input end Vin+ of gain unit AMP_CELL1, the in-phase input end Vin+ of gain unit AMP_CELL2, switch S 2, an end of switch S 4 are connected with signal input part Vin; The end that the output of gain unit AMP_CELL1 is connected with switch S connects; The end that the output of gain unit AMP_CELL2 is connected with switch S connects; The other end of the other end connection of switch S 6, the other end connection of switch S 7, capacitor C 2, the grid of the 11 P type metal-oxide-semiconductor MP11 and the grid of the 12 P type metal-oxide-semiconductor MP12 connect; The other end of the source electrode of the source electrode of the 11 P type metal-oxide-semiconductor MP11, the source electrode of the 12 P type metal-oxide-semiconductor MP12, the 13 P type metal-oxide-semiconductor MP13, the source electrode of the 14 P type metal-oxide-semiconductor MP14, capacitor C 3 is connected inflow direction and is connected with current source IB; The other end that the source electrode of the source electrode of the source electrode of the 11 N-type metal-oxide-semiconductor MN11, the source electrode of the 12 N-type metal-oxide-semiconductor MN12, the 13 N-type metal-oxide-semiconductor MN13, the source electrode of the 14 N-type metal-oxide-semiconductor MN14, the 15 N-type metal-oxide-semiconductor MN15 is connected with capacitor C connects; The grid of the drain electrode of the 12 P type metal-oxide-semiconductor MP12, the drain electrode of the 12 N-type metal-oxide-semiconductor MN12, the 12 N-type metal-oxide-semiconductor MN12 and the grid of the 13 N-type metal-oxide-semiconductor MN13 connect; The drain electrode of the grid of the 11 N-type metal-oxide-semiconductor N11, the drain electrode of the 13 N-type metal-oxide-semiconductor MN13 and the 13 P type metal-oxide-semiconductor MP13; The grid of the 13 P type metal-oxide-semiconductor MP13, the grid of the 14 P type metal-oxide-semiconductor MP14, the drain electrode of the 14 P type metal-oxide-semiconductor MP14, the grid of the 14 N-type metal-oxide-semiconductor MN14 four, the drain electrode of the 14 N-type metal-oxide-semiconductor MN14 four and the grid of the 15 N-type metal-oxide-semiconductor MN15 four; The drain electrode of the outflow direction of current source IB and the 15 N-type metal-oxide-semiconductor MN15 connects.
The current source of described output stage consists of biasing module and comprises 3 bipolar transistors, 8 P type metal-oxide-semiconductors, and 6 N-type metal-oxide-semiconductors, 9 resistance and 1 electric capacity, wherein,
The grid of the one P type metal-oxide-semiconductor MP1 is connected with Enable Pin EN; The drain electrode of the one P type metal-oxide-semiconductor MP1 is connected with the grid of the drain electrode of the first N-type metal-oxide-semiconductor MN1, grid and the second N-type metal-oxide-semiconductor MN2; The source electrode of the first N-type metal-oxide-semiconductor MN1 is connected with the emitter-base bandgap grading of a P type bipolar transistor P1; Drain electrode, the grid of the 2nd P type metal-oxide-semiconductor MP2, the grid of the 3rd P type metal-oxide-semiconductor MP3 is connected with the drain electrode of the second N-type metal-oxide-semiconductor MN2; The drain electrode of the drain electrode of the 3rd P type metal-oxide-semiconductor MP3, the 4th P type metal-oxide-semiconductor MP4 is connected with zero temp shift current output terminal Iout; The grid of the drain electrode of the grid of the 4th P type metal-oxide-semiconductor MP4, the 5th P type metal-oxide-semiconductor MP5, the 5th P type metal-oxide-semiconductor MP5, an end of resistance R 2 are connected with an end of resistance R 3; The collector electrode of the first N-type bipolar transistor N1, resistance R 2 other ends are connected with the grid of the 3rd N-type metal-oxide-semiconductor MN3; The collector electrode of the second N-type bipolar transistor N2, resistance R 3 other ends are connected with the grid of the 4th N-type metal-oxide-semiconductor MN4; The emitter of the second N-type bipolar transistor N2 is connected with an end of resistance R 4; The base stage of the base stage of the first N-type bipolar transistor N1, the second N-type bipolar transistor N2, an end of resistance R 6 are connected with an end of resistance R 7; The grid of the drain electrode of the 6th P type metal-oxide-semiconductor MP6, the 6th P type metal-oxide-semiconductor MP6, the drain electrode of the 3rd N-type metal-oxide-semiconductor MN3 are connected with the grid of the 7th P type metal-oxide-semiconductor MP7; The source electrode of the source electrode of the 3rd N-type metal-oxide-semiconductor MN3, the 4th N-type metal-oxide-semiconductor MN4 is connected with the drain electrode of the 5th N-type metal-oxide-semiconductor MN5; The grid of the drain electrode of the 7th P type metal-oxide-semiconductor MP7, the drain electrode of the 4th N-type metal-oxide-semiconductor MN4, the 8th P type metal-oxide-semiconductor MP8 is connected with capacitor C 1 one ends; The drain electrode of the drain electrode of the grid of the 5th N-type metal-oxide-semiconductor MN5, the 6th N-type metal-oxide-semiconductor MN6, the 6th N-type metal-oxide-semiconductor MN6 is connected with an end of resistance R 6; One end of the other end of resistance R 6, resistance R 9 is connected with the drain electrode of the 8th P type metal-oxide-semiconductor MP8; The other end of resistance R 9 is connected with the other end of capacitor C 1.
The source electrode of the source electrode of the source electrode of the source electrode of a P type metal-oxide-semiconductor MP1 in described gain unit AMP_CELL1, gain unit AMP_CELL2, the source electrode of the 2nd P type metal-oxide-semiconductor MP2, the 3rd P type metal-oxide-semiconductor MP3, the source electrode of the 3rd P type metal-oxide-semiconductor MP3, the 4th P type metal-oxide-semiconductor MP4, the source electrode of the 5th P type metal-oxide-semiconductor MP5, the 6th P type metal-oxide-semiconductor MP6, the source electrode of the 7th P type metal-oxide-semiconductor MP7, the source electrode of the 8th P type metal-oxide-semiconductor MP8 are connected with power vd D with the other end of resistance R 8.
The other end of the other end of the collector electrode of the P type bipolar transistor P1 in described gain unit AMP_CELL1, gain unit AMP_CELL2, the base stage of a P type bipolar transistor P1, resistance R 1, the emitter of the first N-type bipolar transistor N1, resistance R 4, the source electrode of the 5th N-type metal-oxide-semiconductor MN5, the other end of resistance R 7, the source electrode of the 6th N-type metal-oxide-semiconductor MN6 are connected with ground GND.
Advantage of the present invention: comprise two gain units, a biasing module, three electric capacity, a current source, six switches, 4 P type metal-oxide-semiconductors and 5 N-type metal-oxide-semiconductors, wherein each gain unit comprises an electric capacity, two resistance, a switch, 10 P type metal-oxide-semiconductors and 4 N-type metal-oxide-semiconductors; It is large that this circuit has overcome conventional operation amplifier imbalance, and temperature coefficient is large, and the shortcomings such as driving force deficiency are applicable to DC maladjustment and require the harsh precision circuit field of waiting.This circuit adopts the folded common source and common grid structure as the gain stage of amplifier, has obtained high voltage gain and high PSRR; The error information that has adopted mos capacitance storage amplifier to bring because of factors such as process deviations, and when closed loop is used automatic calibration successively, realized low DC maladjustment; Adopted technique for temperature compensation to realize lower temperature coefficient; Adopt the output of recommending of AB class, obtained high driving force.
Description of drawings
The invention will be further described below in conjunction with the embodiment accompanying drawing:
Fig. 1 is that embodiment of the present invention imbalance self calibration operational amplifier comprises gain stage and output stage two-stage circuit figure;
Fig. 2 is the operational amplifier gain unit;
Fig. 3 is the biasing module circuit diagram;
Fig. 4 is operational amplifier switching sequence and mistuning calibration function figure as a result, and wherein, Fig. 4 (a) is the course of work of imbalance self calibration operational amplifier; Fig. 4 (b) reduces the offset error of operational amplifier gradually through multiply periodic iteration.
Embodiment
As shown in Figure 1, a kind of Low Drift Temperature imbalance self calibration operation amplifier circuit and method for designing comprise gain stage and output stage, and wherein, gain stage comprises 2 gain units and 6 switches; Output stage comprises: biasing module, three electric capacity, six switches, 4 P type metal-oxide-semiconductors and 5 the N-type metal-oxide-semiconductors that current source consists of, and Fig. 2 provides gain unit physical circuit figure, and gain unit comprises three grades:
The first order is transconductance stage, and transconductance stage comprises: a P type metal-oxide-semiconductor MP1, the 2nd P type metal-oxide-semiconductor MP2, the 3rd P type metal-oxide-semiconductor MP3; The one P type metal-oxide-semiconductor MP1 is the transconductance stage current source, and the 2nd P type metal-oxide-semiconductor MP2, the 3rd P type metal-oxide-semiconductor MP3 are P type differential pair tube, consists of the mutual conductance device of gain unit, and input voltage signal is converted into electric current.
The second level is impedance level, comprising: the 4th P type metal-oxide-semiconductor MP4, the 5th P type metal-oxide-semiconductor MP5, the 6th P type metal-oxide-semiconductor MP6, the 7th P type metal-oxide-semiconductor MP7, the first N-type metal-oxide-semiconductor MN1, the second N-type metal-oxide-semiconductor MN2, the 3rd N-type metal-oxide-semiconductor MN3, the 4th N-type metal-oxide-semiconductor MN4 form common-source common-gate current mirror.Impedance level is converted into voltage signal with current signal, and produces enough gains.
The third level is the error information storage level, comprising: the 8th P type metal-oxide-semiconductor MP8, the 9th P type metal-oxide-semiconductor MP9, the tenth P type metal-oxide-semiconductor MP10, and divider resistance R1, R2 provide the direct current biasing near VDD/2; The 8th P type metal-oxide-semiconductor MP8 is third level current source.The 9th P type metal-oxide-semiconductor MP9, the tenth P type metal-oxide-semiconductor MP10 are P type differential pair tube, be used for the offset voltage signal of storage is converted into current signal, and because offset voltage is often less, so the mutual conductance that the third level need to be less, so MP9, MP10 adopt than pipe.
The end that the inverting input Vin-of gain unit AMP_CELL1, an end of switch S 2 are connected with switch S connects; One end of one end of the drain electrode of the other end of the other end of switch S 3, switch S 5, the 11 P type metal-oxide-semiconductor MP11, the drain electrode of the 11 N-type metal-oxide-semiconductor MN11, capacitor C 2, an end of capacitor C 3, capacitor C 4, output end vo connect; The end that the inverting input Vin-of gain unit AMP_CELL2, an end of switch S 4 are connected with switch S connects; The other end of the in-phase input end Vin+ of gain unit AMP_CELL1, the in-phase input end Vin+ of gain unit AMP_CELL2, switch S 2, an end of switch S 4 are connected with signal input part Vin; The end that the output of gain unit AMP_CELL1 is connected with switch S connects; The end that the output of gain unit AMP_CELL2 is connected with switch S connects; The other end of the other end connection of switch S 6, the other end connection of switch S 7, capacitor C 2, the grid of the 11 P type metal-oxide-semiconductor MP11 and the grid of the 12 P type metal-oxide-semiconductor MP12 connect; The other end of the source electrode of the source electrode of the 11 P type metal-oxide-semiconductor MP11, the source electrode of the 12 P type metal-oxide-semiconductor MP12, the 13 P type metal-oxide-semiconductor MP13, the source electrode of the 14 P type metal-oxide-semiconductor MP14, capacitor C 3 is connected inflow direction and is connected with current source IB; The other end that the source electrode of the source electrode of the source electrode of the 11 N-type metal-oxide-semiconductor MN11, the source electrode of the 12 N-type metal-oxide-semiconductor MN12, the 13 N-type metal-oxide-semiconductor MN13, the source electrode of the 14 N-type metal-oxide-semiconductor MN14, the 15 N-type metal-oxide-semiconductor MN15 is connected with capacitor C connects; The grid of the drain electrode of the 12 P type metal-oxide-semiconductor MP12, the drain electrode of the 12 N-type metal-oxide-semiconductor MN12, the 12 N-type metal-oxide-semiconductor MN12 and the grid of the 13 N-type metal-oxide-semiconductor MN13 connect; The drain electrode of the grid of the 11 N-type metal-oxide-semiconductor N11, the drain electrode of the 13 N-type metal-oxide-semiconductor MN13 and the 13 P type metal-oxide-semiconductor MP13; The grid of the 13 P type metal-oxide-semiconductor MP13, the grid of the 14 P type metal-oxide-semiconductor MP14, the drain electrode of the 14 P type metal-oxide-semiconductor MP14, the grid of the 14 N-type metal-oxide-semiconductor MN14 four, the drain electrode of the 14 N-type metal-oxide-semiconductor MN14 four and the grid of the 15 N-type metal-oxide-semiconductor MN15 four; The drain electrode of the outflow direction of current source IB and the 15 N-type metal-oxide-semiconductor MN15 connects;
Gain unit wherein, comprise an electric capacity, two resistance, a switch, 10 P type metal-oxide-semiconductors and 4 N-type metal-oxide-semiconductors, the end that an end of the grid of the source electrode of the source electrode of a P type metal-oxide-semiconductor MP1, the 4th P type metal-oxide-semiconductor MP4, the grid of the 6th P type metal-oxide-semiconductor MP6, the 7th P type metal-oxide-semiconductor MP7, the source electrode of the 5th P type metal-oxide-semiconductor MP5, capacitor C, the source electrode of the 8th P type metal-oxide-semiconductor MP8 are connected with resistance R connects; The source electrode of the source electrode of the drain electrode of the one P type metal-oxide-semiconductor MP1, the 2nd P type metal-oxide-semiconductor MP2 and the 3rd P type metal-oxide-semiconductor MP3 connects; The grid of the 2nd P type metal-oxide-semiconductor MP2 is connected with the anode Vin+ of differential signal input, and the grid of the 3rd P type metal-oxide-semiconductor MP3 is connected with the negative terminal Vin-of differential signal input; The drain electrode of the drain electrode of the 2nd P type metal-oxide-semiconductor MP2, the source electrode of the 3rd N-type metal-oxide-semiconductor N3 and the tenth P type metal-oxide-semiconductor MP10 connects; The drain electrode of the drain electrode of the 3rd P type metal-oxide-semiconductor MP3, the source electrode of the 4th N-type metal-oxide-semiconductor N4 and the 9th P type metal-oxide-semiconductor MP9 connects; The grid of the grid of the 4th P type metal-oxide-semiconductor MP4 and the 5th P type metal-oxide-semiconductor MP5 connects; The grid of the grid of the 3rd N-type metal-oxide-semiconductor N3 and the 4th N-type metal-oxide-semiconductor N4 connects; The grid of the first N-type metal-oxide-semiconductor N1 be connected the grid of N-type metal-oxide-semiconductor N2 and connect; The end that the source electrode of the source electrode of the first N-type metal-oxide-semiconductor N1, the second N-type metal-oxide-semiconductor N2 is connected with resistance R connects; One end of the grid of the 9th P type metal-oxide-semiconductor MP9, the other end of capacitor C, switch S 1 is connected with the single-ended signal output end vo; The source electrode of the source electrode of the drain electrode of the 8th P type metal-oxide-semiconductor MP8, the 9th P type metal-oxide-semiconductor MP9 and the tenth P type metal-oxide-semiconductor MP10 connects; The other end that the grid of the tenth P type metal-oxide-semiconductor MP10, the other end of resistance R 1 are connected with resistance R connects; The source electrode of the drain electrode of the 4th P type metal-oxide-semiconductor MP4 and the 6th P type metal-oxide-semiconductor MP6 connects; The source electrode of the drain electrode of the 5th P type metal-oxide-semiconductor MP5 and the 7th P type metal-oxide-semiconductor MP7 connects; The drain electrode of the drain electrode of the 6th P type metal-oxide-semiconductor MP6 and the 3rd N-type metal-oxide-semiconductor N3 connects; The other end that the drain electrode of the 7th P type metal-oxide-semiconductor MP7, the drain electrode of the 4th N-type metal-oxide-semiconductor N4 are connected with switch S connects.
Wherein biasing module as shown in Figure 3, comprises 3 bipolar transistors, 8 P type metal-oxide-semiconductors, 6 N-type metal-oxide-semiconductors, 9 resistance and 1 electric capacity.It is characterized in that:
The grid of the one P type metal-oxide-semiconductor MP1 is connected with Enable Pin EN; The drain electrode of the one P type metal-oxide-semiconductor MP1 is connected with the grid of the drain electrode of the first N-type metal-oxide-semiconductor MN1, grid and the second N-type metal-oxide-semiconductor MN2; The source electrode of the first N-type metal-oxide-semiconductor MN1 is connected with the emitter-base bandgap grading of a P type bipolar transistor P1; Drain electrode, the grid of the 2nd P type metal-oxide-semiconductor MP2, the grid of the 3rd P type metal-oxide-semiconductor MP3 is connected with the drain electrode of the second N-type metal-oxide-semiconductor MN2; The drain electrode of the drain electrode of the 3rd P type metal-oxide-semiconductor MP3, the 4th P type metal-oxide-semiconductor MP4 is connected with zero temp shift current output terminal Iout; The grid of the drain electrode of the grid of the 4th P type metal-oxide-semiconductor MP4, the 5th P type metal-oxide-semiconductor MP5, the 5th P type metal-oxide-semiconductor MP5, an end of resistance R 2 are connected with an end of resistance R 3; The collector electrode of the first N-type bipolar transistor N1, resistance R 2 other ends are connected with the grid of the 3rd N-type metal-oxide-semiconductor MN3; The collector electrode of the second N-type bipolar transistor N2, resistance R 3 other ends are connected with the grid of the 4th N-type metal-oxide-semiconductor MN4; The emitter of the second N-type bipolar transistor N2 is connected with an end of resistance R 4; The base stage of the base stage of the first N-type bipolar transistor N1, the second N-type bipolar transistor N2, an end of resistance R 6 are connected with an end of resistance R 7; The grid of the drain electrode of the 6th P type metal-oxide-semiconductor MP6, the 6th P type metal-oxide-semiconductor MP6, the drain electrode of the 3rd N-type metal-oxide-semiconductor MN3 are connected with the grid of the 7th P type metal-oxide-semiconductor MP7; The source electrode of the source electrode of the 3rd N-type metal-oxide-semiconductor MN3, the 4th N-type metal-oxide-semiconductor MN4 is connected with the drain electrode of the 5th N-type metal-oxide-semiconductor MN5; The grid of the drain electrode of the 7th P type metal-oxide-semiconductor MP7, the drain electrode of the 4th N-type metal-oxide-semiconductor MN4, the 8th P type metal-oxide-semiconductor MP8 is connected with capacitor C 1 one ends; The drain electrode of the drain electrode of the grid of the 5th N-type metal-oxide-semiconductor MN5, the 6th N-type metal-oxide-semiconductor MN6, the 6th N-type metal-oxide-semiconductor MN6 is connected with an end of resistance R 6; One end of the other end of resistance R 6, resistance R 9 is connected with the drain electrode of the 8th P type metal-oxide-semiconductor MP8; The other end of resistance R 9 is connected with the other end of capacitor C 1.
The source electrode of the source electrode of the source electrode of the source electrode of the source electrode of the source electrode of the source electrode of the source electrode of the source electrode of the one P type metal-oxide-semiconductor MP1, the 2nd P type metal-oxide-semiconductor MP2, the 3rd P type metal-oxide-semiconductor MP3, the 3rd P type metal-oxide-semiconductor MP3, the 4th P type metal-oxide-semiconductor MP4, the 5th P type metal-oxide-semiconductor MP5, the 6th P type metal-oxide-semiconductor MP6, the 7th P type metal-oxide-semiconductor MP7, the 8th P type metal-oxide-semiconductor MP8 is connected with power vd D with the other end of resistance R 8.
The source electrode of the emitter of the base stage of the collector electrode of the one P type bipolar transistor P1, a P type bipolar transistor P1, the other end of resistance R 1, the first N-type bipolar transistor N1, the other end of resistance R 4, the 5th N-type metal-oxide-semiconductor MN5, the other end of resistance R 7, the source electrode of the 6th N-type metal-oxide-semiconductor MN6 are connected with ground GND.
As shown in Figure 3, in biasing module, the circuit that MP1-MP3, MN1-MN2, P1, R1 form produces negative temperature parameter current
The circuit that MP4-MP5, MN1-MN2, N1, N2, R2-R5 form produces the PTAT electric current
And MP6-MP8, MN3-MN6, R6-R8 form two-stage calculation amplifier, guarantee that the collector electrode of N1 equates with the collector voltage of N2, and wherein C1 and R1 produce and offset Left half-plane one limit a zero point.Final output current is the stack of negative temperature parameter current and PTAT electric current
The course of work of imbalance self calibration operational amplifier is as shown in the switching sequence of Fig. 4 (a), and wherein the low level representation switch is closed, and the high level representation switch disconnects.In the T1 period, the first switch S 1 closure in the first gain unit AMP_CELL1, in the second gain unit AMP_CELL2, the first switch S 1 disconnects, second switch S2 is closed, and the 3rd switch S 3 disconnects, and the 4th switch S 4 disconnects, the 5th switch S 5 closures, the 6th switch S 6 disconnects, and minion is closed the S7 closure.The in-phase input end Vin+ of the first gain unit AMP_CELL1 and inverting input Vin-short circuit in this period, and be connected with incoming level, output disconnects with push-pull output stage.The first loop L1 of the first gain unit AMP_CELL1 namely gain loop disconnects, and the second loop L2 namely alignment loop is closed.The input imbalance that alignment loop L2 causes the problems such as technique mismatch is calibrated, and error information is stored in the first gain unit AMP_CELL1 in the first capacitor C 1.In-phase input end Vin+ and the input signal of the second gain unit AMP_CELL2 join in this period, and inverting input Vin-and push-pull output stage output are joined, component unit gain negative-feedback circuit.The first loop L1 of the second gain unit AMP_CELL2 namely gain loop is closed, and the second loop L2 namely alignment loop disconnects.Alignment loop L2 will export amplifier according to the error information of the first capacitor C 1 storage in the second gain unit AMP_CELL2 and calibrate; In the T2 period, in the first gain unit AMP_CELL1, the first switch S 1 disconnects, the first switch S 1 closure in the second gain unit AMP_CELL2, second switch S2 disconnects, the 3rd switch S 3 closures, the 4th switch S 4 closures, the 5th switch S 5 disconnects, and the 6th switch S 6 closures, minion are closed S7 and disconnected.In-phase input end Vin+ and the input signal of the first gain unit AMP_CELL1 join in this period, and inverting input Vin-and push-pull output stage output are joined, component unit gain negative-feedback circuit.The first loop L1 of the first gain unit AMP_CELL1 namely gain loop is closed, and the second loop L2 namely alignment loop disconnects.Alignment loop L2 will export amplifier according to the error information of the first capacitor C 1 storage in the first gain unit AMP_CELL1 and calibrate.The in-phase input end Vin+ of the second gain unit AMP_CELL2 and inverting input Vin-short circuit in this period, and be connected with incoming level, output disconnects with push-pull output stage.The first loop L1 of the second gain unit AMP_CELL2 namely gain loop disconnects, and the second loop L2 namely alignment loop is closed.The input imbalance that alignment loop L2 causes the problems such as technique mismatch is calibrated, and error information is stored in the second gain unit AMP_CELL2 in the first capacitor C 1.T3 period circuit working is identical with the T1 period, and T4 period circuit working is identical with the T2 period, reduces gradually the offset error of operational amplifier through multiply periodic iteration, as shown in Fig. 4 (b).
Claims (6)
1. Low Drift Temperature imbalance self calibration operation amplifier circuit and method for designing, comprise gain stage and output stage, and it is characterized in that: gain stage comprises gain unit AMP_CELL1, gain unit AMP_CELL2, and 6 switches; Output stage comprises: biasing module, three electric capacity, six switches, 4 P type metal-oxide-semiconductors and 5 the N-type metal-oxide-semiconductors that current source consists of,
Described gain unit AMP_CELL1 or gain unit AMP_CELL2 comprise: the end that an electric capacity, two resistance, a switch, 10 P type metal-oxide-semiconductors and 4 N-type metal-oxide-semiconductors, an end of the grid of the source electrode of the source electrode of a P type metal-oxide-semiconductor MP1, the 4th P type metal-oxide-semiconductor MP4, the grid of the 6th P type metal-oxide-semiconductor MP6, the 7th P type metal-oxide-semiconductor MP7, the source electrode of the 5th P type metal-oxide-semiconductor MP5, capacitor C, the source electrode of the 8th P type metal-oxide-semiconductor MP8 are connected with resistance R connects; The source electrode of the source electrode of the drain electrode of the one P type metal-oxide-semiconductor MP1, the 2nd P type metal-oxide-semiconductor MP2 and the 3rd P type metal-oxide-semiconductor MP3 connects; The grid of the 2nd P type metal-oxide-semiconductor MP2 is connected with the anode Vin+ of differential signal input, and the grid of the 3rd P type metal-oxide-semiconductor MP3 is connected with the negative terminal Vin-of differential signal input; The drain electrode of the drain electrode of the 2nd P type metal-oxide-semiconductor MP2, the source electrode of the 3rd N-type metal-oxide-semiconductor N3 and the tenth P type metal-oxide-semiconductor MP10 connects; The drain electrode of the drain electrode of the 3rd P type metal-oxide-semiconductor MP3, the source electrode of the 4th N-type metal-oxide-semiconductor N4 and the 9th P type metal-oxide-semiconductor MP9 connects; The grid of the grid of the 4th P type metal-oxide-semiconductor MP4 and the 5th P type metal-oxide-semiconductor MP5 connects; The grid of the grid of the 3rd N-type metal-oxide-semiconductor N3 and the 4th N-type metal-oxide-semiconductor N4 connects; The grid of the first N-type metal-oxide-semiconductor N1 be connected the grid of N-type metal-oxide-semiconductor N2 and connect; The end that the source electrode of the source electrode of the first N-type metal-oxide-semiconductor N1, the second N-type metal-oxide-semiconductor N2 is connected with resistance R connects; One end of the grid of the 9th P type metal-oxide-semiconductor MP9, the other end of capacitor C, switch S 1 is connected with the single-ended signal output end vo; The source electrode of the source electrode of the drain electrode of the 8th P type metal-oxide-semiconductor MP8, the 9th P type metal-oxide-semiconductor MP9 and the tenth P type metal-oxide-semiconductor MP10 connects; The other end that the grid of the tenth P type metal-oxide-semiconductor MP10, the other end of resistance R 1 are connected with resistance R connects; The source electrode of the drain electrode of the 4th P type metal-oxide-semiconductor MP4 and the 6th P type metal-oxide-semiconductor MP6 connects; The source electrode of the drain electrode of the 5th P type metal-oxide-semiconductor MP5 and the 7th P type metal-oxide-semiconductor MP7 connects; The drain electrode of the drain electrode of the 6th P type metal-oxide-semiconductor MP6 and the 3rd N-type metal-oxide-semiconductor N3 connects; The other end that the drain electrode of the 7th P type metal-oxide-semiconductor MP7, the drain electrode of the 4th N-type metal-oxide-semiconductor N4 are connected with switch S connects.
2. a kind of Low Drift Temperature imbalance self calibration operation amplifier circuit according to claim 1 and method for designing, it is characterized in that: described gain unit comprises three grades:
The first order is transconductance stage, and transconductance stage comprises: a P type metal-oxide-semiconductor MP1, the 2nd P type metal-oxide-semiconductor MP2, the 3rd P type metal-oxide-semiconductor MP3; The one P type metal-oxide-semiconductor MP1 is the transconductance stage current source, and the 2nd P type metal-oxide-semiconductor MP2, the 3rd P type metal-oxide-semiconductor MP3 are P type differential pair tube, consists of the mutual conductance device of gain unit, and input voltage signal is converted into electric current;
The second level is impedance level, comprising: the 4th P type metal-oxide-semiconductor MP4, the 5th P type metal-oxide-semiconductor MP5, the 6th P type metal-oxide-semiconductor MP6, the 7th P type metal-oxide-semiconductor MP7, the first N-type metal-oxide-semiconductor MN1, the second N-type metal-oxide-semiconductor MN2, the 3rd N-type metal-oxide-semiconductor MN3, the 4th N-type metal-oxide-semiconductor MN4 form common-source common-gate current mirror; Impedance level is converted into voltage signal with current signal, and produces enough gains;
The third level is the error information storage level, comprising: the 8th P type metal-oxide-semiconductor MP8, the 9th P type metal-oxide-semiconductor MP9, the tenth P type metal-oxide-semiconductor MP10, and divider resistance R1, R2 provide the direct current biasing near VDD/2; The 8th P type metal-oxide-semiconductor MP8 is third level current source; The 9th P type metal-oxide-semiconductor MP9, the tenth P type metal-oxide-semiconductor MP10 are P type differential pair tube, be used for the offset voltage signal of storage is converted into current signal, and because offset voltage is often less, so the mutual conductance that the third level need to be less, so MP9, MP10 adopt than pipe.
3. a kind of Low Drift Temperature imbalance self calibration operation amplifier circuit according to claim 1 and method for designing, is characterized in that: the end connection that the inverting input Vin-of described the first gain unit AMP_CELL1, an end of switch S 2 are connected with switch S; One end of one end of the drain electrode of the other end of the other end of switch S 3, switch S 5, the 11 P type metal-oxide-semiconductor MP11, the drain electrode of the 11 N-type metal-oxide-semiconductor MN11, capacitor C 2, an end of capacitor C 3, capacitor C 4, output end vo connect; The end that the inverting input Vin-of gain unit AMP_CELL2, an end of switch S 4 are connected with switch S connects; The other end of the in-phase input end Vin+ of gain unit AMP_CELL1, the in-phase input end Vin+ of gain unit AMP_CELL2, switch S 2, an end of switch S 4 are connected with signal input part Vin; The end that the output of gain unit AMP_CELL1 is connected with switch S connects; The end that the output of gain unit AMP_CELL2 is connected with switch S connects; The other end of the other end connection of switch S 6, the other end connection of switch S 7, capacitor C 2, the grid of the 11 P type metal-oxide-semiconductor MP11 and the grid of the 12 P type metal-oxide-semiconductor MP12 connect; The other end of the source electrode of the source electrode of the 11 P type metal-oxide-semiconductor MP11, the source electrode of the 12 P type metal-oxide-semiconductor MP12, the 13 P type metal-oxide-semiconductor MP13, the source electrode of the 14 P type metal-oxide-semiconductor MP14, capacitor C 3 is connected inflow direction and is connected with current source IB; The other end that the source electrode of the source electrode of the source electrode of the 11 N-type metal-oxide-semiconductor MN11, the source electrode of the 12 N-type metal-oxide-semiconductor MN12, the 13 N-type metal-oxide-semiconductor MN13, the source electrode of the 14 N-type metal-oxide-semiconductor MN14, the 15 N-type metal-oxide-semiconductor MN15 is connected with capacitor C connects; The grid of the drain electrode of the 12 P type metal-oxide-semiconductor MP12, the drain electrode of the 12 N-type metal-oxide-semiconductor MN12, the 12 N-type metal-oxide-semiconductor MN12 and the grid of the 13 N-type metal-oxide-semiconductor MN13 connect; The drain electrode of the grid of the 11 N-type metal-oxide-semiconductor N11, the drain electrode of the 13 N-type metal-oxide-semiconductor MN13 and the 13 P type metal-oxide-semiconductor MP13; The grid of the 13 P type metal-oxide-semiconductor MP13, the grid of the 14 P type metal-oxide-semiconductor MP14, the drain electrode of the 14 P type metal-oxide-semiconductor MP14, the grid of the 14 N-type metal-oxide-semiconductor MN14 four, the drain electrode of the 14 N-type metal-oxide-semiconductor MN14 four and the grid of the 15 N-type metal-oxide-semiconductor MN15 four; The drain electrode of the outflow direction of current source IB and the 15 N-type metal-oxide-semiconductor MN15 connects.
4. a kind of Low Drift Temperature imbalance self calibration operation amplifier circuit according to claim 1 and method for designing, it is characterized in that: the current source of described output stage consists of biasing module and comprises 3 bipolar transistors, 8 P type metal-oxide-semiconductors, 6 N-type metal-oxide-semiconductors, 9 resistance and 1 electric capacity, wherein
The grid of the one P type metal-oxide-semiconductor MP1 is connected with Enable Pin EN; The drain electrode of the one P type metal-oxide-semiconductor MP1 is connected with the grid of the drain electrode of the first N-type metal-oxide-semiconductor MN1, grid and the second N-type metal-oxide-semiconductor MN2; The source electrode of the first N-type metal-oxide-semiconductor MN1 is connected with the emitter-base bandgap grading of a P type bipolar transistor P1; Drain electrode, the grid of the 2nd P type metal-oxide-semiconductor MP2, the grid of the 3rd P type metal-oxide-semiconductor MP3 is connected with the drain electrode of the second N-type metal-oxide-semiconductor MN2; The drain electrode of the drain electrode of the 3rd P type metal-oxide-semiconductor MP3, the 4th P type metal-oxide-semiconductor MP4 is connected with zero temp shift current output terminal Iout; The grid of the drain electrode of the grid of the 4th P type metal-oxide-semiconductor MP4, the 5th P type metal-oxide-semiconductor MP5, the 5th P type metal-oxide-semiconductor MP5, an end of resistance R 2 are connected with an end of resistance R 3; The collector electrode of the first N-type bipolar transistor N1, resistance R 2 other ends are connected with the grid of the 3rd N-type metal-oxide-semiconductor MN3; The collector electrode of the second N-type bipolar transistor N2, resistance R 3 other ends are connected with the grid of the 4th N-type metal-oxide-semiconductor MN4; The emitter of the second N-type bipolar transistor N2 is connected with an end of resistance R 4; The base stage of the base stage of the first N-type bipolar transistor N1, the second N-type bipolar transistor N2, an end of resistance R 6 are connected with an end of resistance R 7; The grid of the drain electrode of the 6th P type metal-oxide-semiconductor MP6, the 6th P type metal-oxide-semiconductor MP6, the drain electrode of the 3rd N-type metal-oxide-semiconductor MN3 are connected with the grid of the 7th P type metal-oxide-semiconductor MP7; The source electrode of the source electrode of the 3rd N-type metal-oxide-semiconductor MN3, the 4th N-type metal-oxide-semiconductor MN4 is connected with the drain electrode of the 5th N-type metal-oxide-semiconductor MN5; The grid of the drain electrode of the 7th P type metal-oxide-semiconductor MP7, the drain electrode of the 4th N-type metal-oxide-semiconductor MN4, the 8th P type metal-oxide-semiconductor MP8 is connected with capacitor C 1 one ends; The drain electrode of the drain electrode of the grid of the 5th N-type metal-oxide-semiconductor MN5, the 6th N-type metal-oxide-semiconductor MN6, the 6th N-type metal-oxide-semiconductor MN6 is connected with an end of resistance R 6; One end of the other end of resistance R 6, resistance R 9 is connected with the drain electrode of the 8th P type metal-oxide-semiconductor MP8; The other end of resistance R 9 is connected with the other end of capacitor C 1.
5. a kind of Low Drift Temperature imbalance self calibration operation amplifier circuit according to claim 1 and method for designing, it is characterized in that: described gain unit AMP_CELL1, the source electrode of a P type metal-oxide-semiconductor MP1 in gain unit AMP_CELL2, the source electrode of the 2nd P type metal-oxide-semiconductor MP2, the source electrode of the 3rd P type metal-oxide-semiconductor MP3, the source electrode of the 3rd P type metal-oxide-semiconductor MP3, the source electrode of the 4th P type metal-oxide-semiconductor MP4, the source electrode of the 5th P type metal-oxide-semiconductor MP5, the source electrode of the 6th P type metal-oxide-semiconductor MP6, the source electrode of the 7th P type metal-oxide-semiconductor MP7, the source electrode of the 8th P type metal-oxide-semiconductor MP8 is connected with power vd D with the other end of resistance R 8.
6. a kind of Low Drift Temperature imbalance self calibration operation amplifier circuit according to claim 1 and method for designing, it is characterized in that: the other end of the other end of the collector electrode of the P type bipolar transistor P1 in described gain unit AMP_CELL1, gain unit AMP_CELL2, the base stage of a P type bipolar transistor P1, resistance R 1, the emitter of the first N-type bipolar transistor N1, resistance R 4, the source electrode of the 5th N-type metal-oxide-semiconductor MN5, the other end of resistance R 7, the source electrode of the 6th N-type metal-oxide-semiconductor MN6 are connected with ground GND.
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