CN105322899A - Gain-boosted operational amplifier applicable to sigma-delta modulator - Google Patents
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Abstract
The invention relates to large-scale integrated circuits, and aims to improve direct current gain of an amplifier, simultaneously increase gain bandwidth product of the amplifier and finally realize increase of direct current gain and bandwidth of the amplifier under the condition of same chip area. Therefore, the technical scheme of the invention is a gain-boosted operational amplifier applicable to a sigma-delta modulator. The gain-boosted operational amplifier applicable to the sigma-delta modulator is composed of a Recycling folded cascade amplification stage, an output resistance boosting loop, a transconductance boosting loop and a common-mode feedback stage; differential mode signals Vin- and Vin+ are input through the Recycling folded cascade amplification stage, then, the signals are subjected to the cross positive feedback effect of the output resistance boosting loop stage and the transconductance boosting loop stage and further subjected to current multiplication of a cascade current mirror, and finally, the signals are output to output ends Vout- and Vout+. The gain-boosted operational amplifier applicable to the sigma-delta modulator is mainly applied to design and manufacturing of the large-scale integrated circuits.
Description
Technical field
The present invention relates to large scale integrated circuit, low-voltage and low-power dissipation, sigma_delta modulator, operational amplifier, specifically, relate to the gain suppression type operational amplifier being applicable to sigma delta modulator.
Background technology
Low-voltage and low-power dissipation high gain operational amplifier is the very active research field of low-power consumption analog circuit all the time.Many high gain operational amplifiers (such as multi-stage operational amplifier) rely on laterally increases the gain that gain stage number improves amplifier, although improve low-frequency gain like this, but be reduction of the stability of amplifier, also need to increase extra electric capacity to improve stability, so this adds increased the area of chip, so these are unfavorable for the high integration future development of low dissipation amplifier.More bulky capacitor can cause the long-pending reduction of the unity gain bandwidth of amplifier simultaneously, this reduces the speed of amplifier, is more unfavorable for the high speed future development of amplifier.So single stage operational amplifier is just widely used in high speed processing field (such as: in the equipment such as sigma_delta modulator, integrator, radio communication).
Summary of the invention
The invention is intended to make up the deficiencies in the prior art, improve the DC current gain of amplifier.Increase the gain bandwidth product of amplifier simultaneously.Final realization, under the condition of equal chip area, improves DC current gain and the bandwidth of amplifier.For this reason, the technical scheme that the present invention takes is, is applicable to the gain suppression type operational amplifier of sigma delta modulator, is made up of Recyclingfoldedcascode amplifying stage, output resistance reinforcing feedback, mutual conductance reinforcing feedback and common-mode feedback level; Input difference mode signal Vin-and Vin+ is after Recyclingfoldedcascode amplifying stage, again after the intersection positive feedback effect of output resistance reinforcing feedback level and mutual conductance reinforcing feedback level, the current multiplication then through cascode current mirror is applied to output end vo ut-and Vout+; Simultaneously through the stability of the negative feedback maintenance amplifier of common mode feedback voltage Vcmfb.
Recyclingfoldedcascode amplifying stage comprises input mutual conductance booster stage gm1 and cascode current mirror; Output resistance reinforcing feedback comprises transistor Ma1-Ma8; Mutual conductance reinforcing feedback comprises transistor Mb1-Mb8; Common-mode feedback level comprises transistor M5-M6.
Recyclingfoldedcascode amplifying stage is made up of PMOS transistor M1a, M1b, M2a, M2b, M5, M6, M7, M8, M9, M10 and nmos pass transistor M11, M12, M3a, M3b, M4a, M4b.Input mutual conductance booster stage gm1 is made up of PMOS transistor M1a, M1b, M2a, M2b, Ma1, Ma3, Ma5, Ma7, Mb1, Mb3, Mb5, Mb7 and nmos pass transistor Ma2, Ma4, Ma6, Ma8, Mb2, Mb4, Mb6, Mb8.Cascode current mirror is made up of nmos pass transistor M11, M12, M3a, M3b, M4a, M4b.
Concrete implementing circuit is: described amplifier by the first to the 21 PMOS transistor M0a, M0b, M0c, M1a, M1b, M2a, M2b, Ma1, Ma3, Ma5, Ma7, Mb1, Mb3, Mb5, Mb7, M5, M6, M7, M8, M9, M10 and first to the 14 nmos pass transistor Ma2, Ma4, Ma6, Ma8, Mb2, Mb4, Mb6, Mb8, M11, M12, M3a, M3b, M4a, M4b totally 35 MOS transistor form; Wherein:
First to the 3rd, the 16, the 17 PMOS transistor M0a, M0b, M0c, M5, M6 source electrode jointly meet power supply VDD; The substrate termination power supply VDD of all PMOS transistor M0a, M0b, M0c, M1a, M1b, M2a, M2b, Ma1, Ma3, Ma5, Ma7, Mb1, Mb3, Mb5, Mb7, M5, M6, M7, M8, M9, M10; Except the 9th to the tenth nmos pass transistor M11, M12, the source electrode common ground GND of all nmos pass transistor Ma2, Ma4, Ma6, Ma8, Mb2, Mb4, Mb6, Mb8, M3a, M3b, M4a, M4b; The substrate common ground GND of all nmos pass transistor Ma2, Ma4, Ma6, Ma8, Mb2, Mb4, Mb6, Mb8, M11, M12, M3a, M3b, M4a, M4b;
The grid of the first to the 3rd PMOS transistor M0a, M0b, M0c meets the first bias voltage Vb1; The drain electrode of the first PMOS transistor M0a connects the source electrode of the 4th to the 7th PMOS transistor M1a, M1b, M2a, M2b;
The grid of the 4th to the 5th PMOS transistor M1a, M1b meets input Vp; The grid of the 6th to the 7th PMOS transistor M2a, M2b meets input Vn;
Four, the drain electrode of the 20 PMOS transistor M1a, M9 connects the drain electrode of the 11 nmos pass transistor M3a jointly; Six, the drain electrode of the 21 PMOS transistor M2a, M10 connects the drain electrode of the 13 nmos pass transistor M4a jointly; The grid of the 7th PMOS transistor M2b, the 11 to the tenth bi-NMOS transistor M3a, M3b connects the drain electrode of the 9th nmos pass transistor M11 jointly; The grid of the 5th PMOS transistor M1b, the 13 to the 14 nmos pass transistor M4a, M4b connects the drain electrode of the tenth nmos pass transistor M12 jointly; The source electrode of the 9th nmos pass transistor M11 connects the drain electrode of the tenth bi-NMOS transistor M3b; The drain electrode of the tenth nmos pass transistor M12 connects the drain electrode of the 14 nmos pass transistor M4b; Nine, the grid of the tenth nmos pass transistor M11, M12 and the 20, the 21 PMOS transistor M9, M10 meets the 3rd bias voltage Vb3 jointly;
The source electrode of the 20 PMOS transistor M9 and the drain electrode of the 18 PMOS transistor M7 meet output end vo ut-jointly; The source electrode of the 21 PMOS transistor M10 and the drain electrode of the 19 PMOS transistor M8 meet output end vo ut+ jointly; 18, the grid of the 19 PMOS transistor M7, M8 meets the second bias voltage Vb2 jointly; The source electrode of the 18 PMOS transistor M7 connects the drain electrode of the 16 PMOS transistor M5; The source electrode of the 19 PMOS transistor M8 connects the drain electrode of the 17 PMOS transistor M6; 16, the grid of the 17 PMOS transistor M5, M6 meets the first common mode feedback voltage Vcmfb jointly;
The source electrode of the 8th to the 11 PMOS transistor Ma1, Ma3, Ma5, Ma7 connects the drain electrode of the second PMOS transistor M0b jointly; The grid of the 8th PMOS transistor Ma1 and drain electrode, the grid of the first nmos pass transistor Ma2 and drain electrode connect the source electrode of the 4th PMOS transistor M1a jointly; The grid of the 11 PMOS transistor Ma7 and drain electrode, the grid of the 4th nmos pass transistor Ma8 and drain electrode connect the source electrode of the 6th PMOS transistor M2a jointly; The grid of the 9th PMOS transistor Ma3 and the second nmos pass transistor Ma4, the drain electrode of the tenth PMOS transistor Ma5 and the 3rd nmos pass transistor Ma6 connects the grid of the 11 PMOS transistor Ma7 jointly; The drain electrode of the 9th PMOS transistor Ma3 and the second nmos pass transistor Ma4, the grid of the tenth PMOS transistor Ma5 and the 3rd nmos pass transistor Ma6 connects the grid of the 8th PMOS transistor Ma1 jointly; The source electrode common ground GND of first to fourth nmos pass transistor Ma2, Ma4, Ma6, Ma8;
The source electrode of the 12 to the 15 PMOS transistor Mb1, Mb3, Mb5, Mb7 connects the drain electrode of the 3rd PMOS transistor M0c jointly; The grid of the 12 PMOS transistor Mb1 and drain electrode, the grid of the 5th nmos pass transistor Mb2 and drain electrode connect the drain electrode of the 9th nmos pass transistor M11 jointly; The grid of the 15 PMOS transistor Mb7 and drain electrode, the grid of the 8th nmos pass transistor Mb8 and drain electrode connect the drain electrode of the tenth nmos pass transistor M12 jointly; The grid of the 13 PMOS transistor Mb3 and the 6th nmos pass transistor Mb4, the drain electrode of the 14 PMOS transistor Mb5 and the 7th nmos pass transistor Mb6 connects the grid of the 15 PMOS transistor Mb7 jointly; The drain electrode of the 13 PMOS transistor Mb3 and the 6th nmos pass transistor Mb4, the grid of the 14 PMOS transistor Mb5 and the 7th nmos pass transistor Mb6 connects the grid of the 12 PMOS transistor Mb1 jointly; The source electrode common ground GND of the 5th to the 8th nmos pass transistor Mb2, Mb4, Mb6, Mb8;
The drain electrode of the 5th PMOS transistor M1b connects the drain electrode of the tenth nmos pass transistor M12; The drain electrode of the 6th PMOS transistor M2b connects the drain electrode of the 9th nmos pass transistor M11.
Technical characterstic of the present invention and effect:
Adopt the loop of positive feedback to improve input mutual conductance and the output resistance of amplifier respectively, and then improve the DC current gain of amplifier.Increase the gain bandwidth product of amplifier simultaneously.Final realization, under the condition of equal chip area, improves DC current gain and the bandwidth of amplifier, and has lower power consumption.
Accompanying drawing explanation
The above-mentioned advantage of the present invention will become obvious and easy understand from the following description of the accompanying drawings of embodiments, wherein:
The circuit diagram of Fig. 1 operational amplifier.
Embodiment
In order to overcome above-mentioned the deficiencies in the prior art part, the present invention proposes the low-power consumption operational transconductance amplifier of a kind of mutual conductance enhancing for sigma_delta modulator and output resistance enhancing, based on original RecyclingFoldedcascode amplifier, adopt the loop of positive feedback to improve input mutual conductance and the output resistance of amplifier respectively herein, and then improve the DC current gain of amplifier.Increase the gain bandwidth product of amplifier simultaneously.Final realization, under the condition of equal chip area, improves DC current gain and the bandwidth of amplifier.
The present invention proposes a kind of low-power consumption gain suppression type operational amplifier being applicable to sigma_delta modulator, described amplifier is made up of Recyclingfoldedcascode amplifying stage, output resistance reinforcing feedback, mutual conductance reinforcing feedback and common-mode feedback level.Recyclingfoldedcascode amplifying stage comprises input mutual conductance booster stage gm1 and cascode current mirror.Output resistance reinforcing feedback comprises transistor Ma1-Ma8; Mutual conductance reinforcing feedback comprises transistor Mb1-Mb8; Common-mode feedback level comprises transistor M5-M6.
Recyclingfoldedcascode amplifying stage is made up of PMOS transistor M1a, M1b, M2a, M2b, M5, M6, M7, M8, M9, M10 and nmos pass transistor M11, M12, M3a, M3b, M4a, M4b.Input mutual conductance booster stage gm1 is made up of PMOS transistor M1a, M1b, M2a, M2b, Ma1, Ma3, Ma5, Ma7, Mb1, Mb3, Mb5, Mb7 and nmos pass transistor Ma2, Ma4, Ma6, Ma8, Mb2, Mb4, Mb6, Mb8.Cascode current mirror is made up of nmos pass transistor M11, M12, M3a, M3b, M4a, M4b.
Concrete implementing circuit principle is as accompanying drawing: as described in amplifier by the first to the 21 PMOS transistor M0a, M0b, M0c, M1a, M1b, M2a, M2b, Ma1, Ma3, Ma5, Ma7, Mb1, Mb3, Mb5, Mb7, M5, M6, M7, M8, M9, M10 and first to the 14 nmos pass transistor Ma2, Ma4, Ma6, Ma8, Mb2, Mb4, Mb6, Mb8, M11, M12, M3a, M3b, M4a, M4b totally 35 MOS transistor form; Wherein:
First to the 3rd, the 16, the 17 PMOS transistor M0a, M0b, M0c, M5, M6 source electrode jointly meet power supply VDD; The substrate termination power supply VDD of all PMOS transistor M0a, M0b, M0c, M1a, M1b, M2a, M2b, Ma1, Ma3, Ma5, Ma7, Mb1, Mb3, Mb5, Mb7, M5, M6, M7, M8, M9, M10; Except the 9th to the tenth nmos pass transistor M11, M12, the source electrode common ground GND of all nmos pass transistor Ma2, Ma4, Ma6, Ma8, Mb2, Mb4, Mb6, Mb8, M3a, M3b, M4a, M4b; The substrate common ground GND of all nmos pass transistor Ma2, Ma4, Ma6, Ma8, Mb2, Mb4, Mb6, Mb8, M11, M12, M3a, M3b, M4a, M4b;
The grid of the first to the 3rd PMOS transistor M0a, M0b, M0c meets the first bias voltage Vb1; The drain electrode of the first PMOS transistor M0a connects the source electrode of the 4th to the 7th PMOS transistor M1a, M1b, M2a, M2b;
The grid of the 4th to the 5th PMOS transistor M1a, M1b meets input Vp; The grid of the 6th to the 7th PMOS transistor M2a, M2b meets input Vn;
Four, the drain electrode of the 20 PMOS transistor M1a, M9 connects the drain electrode of the 11 nmos pass transistor M3a jointly; Six, the drain electrode of the 21 PMOS transistor M2a, M10 connects the drain electrode of the 13 nmos pass transistor M4a jointly; The grid of the 7th PMOS transistor M2b, the 11 to the tenth bi-NMOS transistor M3a, M3b connects the drain electrode of the 9th nmos pass transistor M11 jointly; The grid of the 5th PMOS transistor M1b, the 13 to the 14 nmos pass transistor M4a, M4b connects the drain electrode of the tenth nmos pass transistor M12 jointly; The source electrode of the 9th nmos pass transistor M11 connects the drain electrode of the tenth bi-NMOS transistor M3b; The drain electrode of the tenth nmos pass transistor M12 connects the drain electrode of the 14 nmos pass transistor M4b; Nine, the grid of the tenth nmos pass transistor M11, M12 and the 20, the 21 PMOS transistor M9, M10 meets the 3rd bias voltage Vb3 jointly;
The source electrode of the 20 PMOS transistor M9 and the drain electrode of the 18 PMOS transistor M7 meet output end vo ut-jointly; The source electrode of the 21 PMOS transistor M10 and the drain electrode of the 19 PMOS transistor M8 meet output end vo ut+ jointly; 18, the grid of the 19 PMOS transistor M7, M8 meets the second bias voltage Vb2 jointly; The source electrode of the 18 PMOS transistor M7 connects the drain electrode of the 16 PMOS transistor M5; The source electrode of the 19 PMOS transistor M8 connects the drain electrode of the 17 PMOS transistor M6; 16, the grid of the 17 PMOS transistor M5, M6 meets the first common mode feedback voltage Vcmfb jointly;
The source electrode of the 8th to the 11 PMOS transistor Ma1, Ma3, Ma5, Ma7 connects the drain electrode of the second PMOS transistor M0b jointly; The grid of the 8th PMOS transistor Ma1 and drain electrode, the grid of the first nmos pass transistor Ma2 and drain electrode connect the source electrode of the 4th PMOS transistor M1a jointly; The grid of the 11 PMOS transistor Ma7 and drain electrode, the grid of the 4th nmos pass transistor Ma8 and drain electrode connect the source electrode of the 6th PMOS transistor M2a jointly; The grid of the 9th PMOS transistor Ma3 and the second nmos pass transistor Ma4, the drain electrode of the tenth PMOS transistor Ma5 and the 3rd nmos pass transistor Ma6 connects the grid of the 11 PMOS transistor Ma7 jointly; The drain electrode of the 9th PMOS transistor Ma3 and the second nmos pass transistor Ma4, the grid of the tenth PMOS transistor Ma5 and the 3rd nmos pass transistor Ma6 connects the grid of the 8th PMOS transistor Ma1 jointly; The source electrode common ground GND of first to fourth nmos pass transistor Ma2, Ma4, Ma6, Ma8;
The source electrode of the 12 to the 15 PMOS transistor Mb1, Mb3, Mb5, Mb7 connects the drain electrode of the 3rd PMOS transistor M0c jointly; The grid of the 12 PMOS transistor Mb1 and drain electrode, the grid of the 5th nmos pass transistor Mb2 and drain electrode connect the drain electrode of the 9th nmos pass transistor M11 jointly; The grid of the 15 PMOS transistor Mb7 and drain electrode, the grid of the 8th nmos pass transistor Mb8 and drain electrode connect the drain electrode of the tenth nmos pass transistor M12 jointly; The grid of the 13 PMOS transistor Mb3 and the 6th nmos pass transistor Mb4, the drain electrode of the 14 PMOS transistor Mb5 and the 7th nmos pass transistor Mb6 connects the grid of the 15 PMOS transistor Mb7 jointly; The drain electrode of the 13 PMOS transistor Mb3 and the 6th nmos pass transistor Mb4, the grid of the 14 PMOS transistor Mb5 and the 7th nmos pass transistor Mb6 connects the grid of the 12 PMOS transistor Mb1 jointly; The source electrode common ground GND of the 5th to the 8th nmos pass transistor Mb2, Mb4, Mb6, Mb8;
The drain electrode of the 5th PMOS transistor M1b connects the drain electrode of the tenth nmos pass transistor M12; The drain electrode of the 6th PMOS transistor M2b connects the drain electrode of the 9th nmos pass transistor M11.
Choose the 4th to the 5th PMOS transistor M1a, the gate input Vp and the 6th to the gate input Vn of the 7th PMOS transistor M2a, M2b of M1b inputs difference mode signal Vin-and Vin+ respectively, after the intersection positive feedback effect of output resistance reinforcing feedback level and mutual conductance reinforcing feedback level, the current multiplication then through cascode current mirror is applied to output end vo ut-and Vout+.Simultaneously through the stability of the negative feedback maintenance amplifier of common mode feedback voltage Vcmfb.The final object realizing improving DC current gain and expand gain bandwidth product.
Claims (4)
1. be applicable to a gain suppression type operational amplifier for sigma delta modulator, it is characterized in that, be made up of Recyclingfoldedcascode amplifying stage, output resistance reinforcing feedback, mutual conductance reinforcing feedback and common-mode feedback level; Input difference mode signal Vin-and Vin+ is after Recyclingfoldedcascode amplifying stage, again after the intersection positive feedback effect of output resistance reinforcing feedback level and mutual conductance reinforcing feedback level, the current multiplication then through cascode current mirror is applied to output end vo ut-and Vout+; Simultaneously through the stability of the negative feedback maintenance amplifier of common mode feedback voltage Vcmfb.
2. be applicable to the gain suppression type operational amplifier of sigma delta modulator as claimed in claim 1, it is characterized in that: Recyclingfoldedcascode amplifying stage comprises input mutual conductance booster stage gm1 and cascode current mirror; Output resistance reinforcing feedback comprises transistor Ma1-Ma8; Mutual conductance reinforcing feedback comprises transistor Mb1-Mb8; Common-mode feedback level comprises transistor M5-M6.
3. be applicable to the gain suppression type operational amplifier of sigma delta modulator as claimed in claim 1, it is characterized in that: Recyclingfoldedcascode amplifying stage is made up of PMOS transistor M1a, M1b, M2a, M2b, M5, M6, M7, M8, M9, M10 and nmos pass transistor M11, M12, M3a, M3b, M4a, M4b.Input mutual conductance booster stage gm1 is made up of PMOS transistor M1a, M1b, M2a, M2b, Ma1, Ma3, Ma5, Ma7, Mb1, Mb3, Mb5, Mb7 and nmos pass transistor Ma2, Ma4, Ma6, Ma8, Mb2, Mb4, Mb6, Mb8.Cascode current mirror is made up of nmos pass transistor M11, M12, M3a, M3b, M4a, M4b.
4. be applicable to the gain suppression type operational amplifier of sigma delta modulator as claimed in claim 1, it is characterized in that, concrete implementing circuit is: described amplifier by the first to the 21 PMOS transistor M0a, M0b, M0c, M1a, M1b, M2a, M2b, Ma1, Ma3, Ma5, Ma7, Mb1, Mb3, Mb5, Mb7, M5, M6, M7, M8, M9, M10 and first to the 14 nmos pass transistor Ma2, Ma4, Ma6, Ma8, Mb2, Mb4, Mb6, Mb8, M11, M12, M3a, M3b, M4a, M4b totally 35 MOS transistor form; Wherein:
First to the 3rd, the 16, the 17 PMOS transistor M0a, M0b, M0c, M5, M6 source electrode jointly meet power supply VDD; The substrate termination power supply VDD of all PMOS transistor M0a, M0b, M0c, M1a, M1b, M2a, M2b, Ma1, Ma3, Ma5, Ma7, Mb1, Mb3, Mb5, Mb7, M5, M6, M7, M8, M9, M10; Except the 9th to the tenth nmos pass transistor M11, M12, the source electrode common ground GND of all nmos pass transistor Ma2, Ma4, Ma6, Ma8, Mb2, Mb4, Mb6, Mb8, M3a, M3b, M4a, M4b; The substrate common ground GND of all nmos pass transistor Ma2, Ma4, Ma6, Ma8, Mb2, Mb4, Mb6, Mb8, M11, M12, M3a, M3b, M4a, M4b;
The grid of the first to the 3rd PMOS transistor M0a, M0b, M0c meets the first bias voltage Vb1; The drain electrode of the first PMOS transistor M0a connects the source electrode of the 4th to the 7th PMOS transistor M1a, M1b, M2a, M2b;
The grid of the 4th to the 5th PMOS transistor M1a, M1b meets input Vp; The grid of the 6th to the 7th PMOS transistor M2a, M2b meets input Vn;
Four, the drain electrode of the 20 PMOS transistor M1a, M9 connects the drain electrode of the 11 nmos pass transistor M3a jointly; Six, the drain electrode of the 21 PMOS transistor M2a, M10 connects the drain electrode of the 13 nmos pass transistor M4a jointly; The grid of the 7th PMOS transistor M2b, the 11 to the tenth bi-NMOS transistor M3a, M3b connects the drain electrode of the 9th nmos pass transistor M11 jointly; The grid of the 5th PMOS transistor M1b, the 13 to the 14 nmos pass transistor M4a, M4b connects the drain electrode of the tenth nmos pass transistor M12 jointly; The source electrode of the 9th nmos pass transistor M11 connects the drain electrode of the tenth bi-NMOS transistor M3b; The drain electrode of the tenth nmos pass transistor M12 connects the drain electrode of the 14 nmos pass transistor M4b; Nine, the grid of the tenth nmos pass transistor M11, M12 and the 20, the 21 PMOS transistor M9, M10 meets the 3rd bias voltage Vb3 jointly;
The source electrode of the 20 PMOS transistor M9 and the drain electrode of the 18 PMOS transistor M7 meet output end vo ut-jointly; The source electrode of the 21 PMOS transistor M10 and the drain electrode of the 19 PMOS transistor M8 meet output end vo ut+ jointly; 18, the grid of the 19 PMOS transistor M7, M8 meets the second bias voltage Vb2 jointly; The source electrode of the 18 PMOS transistor M7 connects the drain electrode of the 16 PMOS transistor M5; The source electrode of the 19 PMOS transistor M8 connects the drain electrode of the 17 PMOS transistor M6; 16, the grid of the 17 PMOS transistor M5, M6 meets the first common mode feedback voltage Vcmfb jointly;
The source electrode of the 8th to the 11 PMOS transistor Ma1, Ma3, Ma5, Ma7 connects the drain electrode of the second PMOS transistor M0b jointly; The grid of the 8th PMOS transistor Ma1 and drain electrode, the grid of the first nmos pass transistor Ma2 and drain electrode connect the source electrode of the 4th PMOS transistor M1a jointly; The grid of the 11 PMOS transistor Ma7 and drain electrode, the grid of the 4th nmos pass transistor Ma8 and drain electrode connect the source electrode of the 6th PMOS transistor M2a jointly; The grid of the 9th PMOS transistor Ma3 and the second nmos pass transistor Ma4, the drain electrode of the tenth PMOS transistor Ma5 and the 3rd nmos pass transistor Ma6 connects the grid of the 11 PMOS transistor Ma7 jointly; The drain electrode of the 9th PMOS transistor Ma3 and the second nmos pass transistor Ma4, the grid of the tenth PMOS transistor Ma5 and the 3rd nmos pass transistor Ma6 connects the grid of the 8th PMOS transistor Ma1 jointly; The source electrode common ground GND of first to fourth nmos pass transistor Ma2, Ma4, Ma6, Ma8;
The source electrode of the 12 to the 15 PMOS transistor Mb1, Mb3, Mb5, Mb7 connects the drain electrode of the 3rd PMOS transistor M0c jointly; The grid of the 12 PMOS transistor Mb1 and drain electrode, the grid of the 5th nmos pass transistor Mb2 and drain electrode connect the drain electrode of the 9th nmos pass transistor M11 jointly; The grid of the 15 PMOS transistor Mb7 and drain electrode, the grid of the 8th nmos pass transistor Mb8 and drain electrode connect the drain electrode of the tenth nmos pass transistor M12 jointly; The grid of the 13 PMOS transistor Mb3 and the 6th nmos pass transistor Mb4, the drain electrode of the 14 PMOS transistor Mb5 and the 7th nmos pass transistor Mb6 connects the grid of the 15 PMOS transistor Mb7 jointly; The drain electrode of the 13 PMOS transistor Mb3 and the 6th nmos pass transistor Mb4, the grid of the 14 PMOS transistor Mb5 and the 7th nmos pass transistor Mb6 connects the grid of the 12 PMOS transistor Mb1 jointly; The source electrode common ground GND of the 5th to the 8th nmos pass transistor Mb2, Mb4, Mb6, Mb8;
The drain electrode of the 5th PMOS transistor M1b connects the drain electrode of the tenth nmos pass transistor M12; The drain electrode of the 6th PMOS transistor M2b connects the drain electrode of the 9th nmos pass transistor M11.
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| CN109921756A (en) * | 2019-01-26 | 2019-06-21 | 桂林电子科技大学 | A kind of fully differential operational transconductance amplifier |
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| Y.L. LI等: ""Transconductance enhancement method for operational transconductance amplifiers"", 《ELECTRONICS LETTERS》 * |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109921756A (en) * | 2019-01-26 | 2019-06-21 | 桂林电子科技大学 | A kind of fully differential operational transconductance amplifier |
| CN109921756B (en) * | 2019-01-26 | 2023-03-14 | 桂林电子科技大学 | Fully-differential transconductance operational amplifier |
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| CN105322899B (en) | 2018-10-16 |
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