CN105573396A - Low dropout linear regulator circuit - Google Patents
Low dropout linear regulator circuit Download PDFInfo
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- CN105573396A CN105573396A CN201610067306.8A CN201610067306A CN105573396A CN 105573396 A CN105573396 A CN 105573396A CN 201610067306 A CN201610067306 A CN 201610067306A CN 105573396 A CN105573396 A CN 105573396A
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
- G05F1/10—Regulating voltage or current
- G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
- G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
Abstract
The invention discloses a low dropout linear regulator circuit which comprises an error amplifier, a regulating tube, a frequency compensation circuit and a feedback circuit. The frequency compensation circuit comprises two compensation capacitors. The input end of the frequency compensation circuit is connected with the output end of the error amplifier. The output end of the frequency compensation circuit is connected with the output end of the low dropout linear regulator circuit. It can be seen that double-capacitance compensation is adopted for frequency compensation of the low dropout linear regulator circuit, the output pole of the error amplifier is amplified by the two compensation capacitors, becomes the main pole of the whole circuit and is located at a high-frequency position, and therefore the influences of load changes on the position of the output pole can be ignored, and therefore the stability of LDO circuits without off-chip capacitors is improved.
Description
Technical field
The present invention relates to switching voltage converter technical field, in particular, relate to a kind of low differential voltage linear voltage stabilizer circuit.
Background technology
Low pressure difference linear voltage regulator (LowDropoutRegulator, LDO) is a kind of linear Voltagre regulator, and its basic function ensures stable output voltage in certain change range of input voltage He in load variation range.LDO is as the important component part of power management chip, it has wide input voltage range, output voltage ripple-free and the advantages such as noise is little, structure is simple, low-power consumption and low production cost, is widely used in the various occasions such as portable product, computing machine, household electrical appliances, automobile electronics.
Tradition LDO circuit all belongs to the structure having the outer electric capacity of sheet, the outer electric capacity of sheet not only can reduce because of change in voltage caused during load current transient changing, it and the system loop of equivalent series resistance to place can also be utilized to compensate, maintain the stability of system.But along with improving constantly of electronic product integrated level, particularly sum power consumption in opposite has the portable electric appts of strict demand, the range of application of the LDO of the outer electric capacity of sheet is had to be subject to increasing restriction.Therefore, the study hotspot of LDO is become without the LDO of capacitance structure outside sheet.
The output capacitance of tradition LDO circuit is the microfarad order of magnitude, so dominant pole is generally positioned at the output terminal of LDO circuit, and is only the pico farad order of magnitude, so its dominant pole is usually located at the output terminal of error amplifier without the output capacitance of the outer electric capacity LDO circuit of sheet.Therefore, the position without the output limit of the outer electric capacity LDO circuit of sheet is determined by load, because load variation range is very large, therefore brings very large impact to the stability without the outer electric capacity LDO circuit of sheet.
To sum up, how to provide a kind of stability high be those skilled in the art's technical matterss urgently to be resolved hurrily without the outer electric capacity LDO circuit of sheet.
Summary of the invention
In view of this, the invention provides a kind of low differential voltage linear voltage stabilizer circuit, to realize the raising without the outer electric capacity LDO circuit stability of sheet.
A kind of low differential voltage linear voltage stabilizer circuit, comprising: error amplifier, Correctional tube, frequency compensated circuit and feedback circuit, wherein, described frequency compensated circuit comprises two compensation condensers;
The inverting input of described error amplifier is connected with reference voltage source, and the output terminal of described error amplifier is connected with the control end of described Correctional tube, and the output terminal of described Correctional tube connects the normal phase input end of described error amplifier by described feedback circuit;
The input end of described Correctional tube connects power supply, the common port of described Correctional tube and described feedback circuit is connected with the output terminal of described frequency compensated circuit as the output terminal of low differential voltage linear voltage stabilizer circuit, and the input end of described frequency compensated circuit connects the output terminal of described error amplifier;
The feedback voltage that described feedback circuit exports by described error amplifier and reference voltage compare generation error signal, by amplifying described error signal, described Correctional tube is regulated, and by described frequency compensated circuit, frequency compensation is carried out to whole circuit.
Preferably, described error amplifier comprises: the first switching tube, second switch pipe, the 3rd switching tube, the 4th switching tube, the 5th switching tube, the 6th switching tube, the 7th switching tube, the 8th switching tube, the 9th switching tube, the tenth switching tube and the 11 switching tube;
The input end of described 11 switching tube connects described power supply, the control end of described 11 switching tube connects the first bias voltage, and the output terminal of described 11 switching tube connects the input end of described first switching tube and the input end of described second switch pipe respectively;
The control end of described first switching tube connects described feedback circuit as the normal phase input end of error amplifier, and the control end of described second switch pipe connects described reference voltage source as the inverting input of described error amplifier;
The input end of described 9th switching tube is all connected described power supply with the input end of described tenth switching tube, and the control end of described 9th switching tube is connected with the control end of described tenth switching tube;
The input end of described 7th switching tube connects the output terminal of described 9th switching tube, the output terminal of described 7th switching tube connects the control end of described 9th switching tube, the control end of described 7th switching tube connects with the described control end of the 8th switching tube and the common port of two control ends is connected the second bias voltage, and the input end of described 8th switching tube connects the output terminal of described tenth switching tube;
The input end of described 5th switching tube connects the output terminal of described 7th switching tube, the control end of described 5th switching tube connects the control end of described 6th switching tube and the common port of two control ends connects the 3rd bias voltage, the input end of described 6th switching tube connects the output terminal of described 8th switching tube, wherein, the common port of described 6th switching tube and described 8th switching tube is as the output terminal of described error amplifier;
The input end of described 3rd switching tube connects the output terminal of described 5th switching tube, and the input end of described 3rd switching tube connects the output terminal of described first switching tube, the output terminal of described 3rd switching tube connects earth terminal, the control end of described 3rd switching tube connects the control end of described 4th switching tube and the common port of two control ends connects the 4th bias voltage, the input end of described 4th switching tube connects the output terminal of described 6th switching tube, and the input end of described 4th switching tube connects the output terminal of described second switch pipe, the output terminal of described 4th switching tube connects earth terminal.
Preferably,
Described first switching tube, described second switch pipe, described 7th switching tube, described 8th switching tube, described 9th switching tube, described tenth switching tube and described 11 switching tube are PMOS;
Described 3rd switching tube, described 4th switching tube, described 5th switching tube and described 6th switching tube are NMOS tube.
Preferably, two described compensation condensers are respectively the first compensation condenser and the second compensation condenser;
The positive plate of described first compensation condenser connects the common port of described 6th switching tube and described 8th switching tube, and the negative plate of described first compensation condenser connects the common port of described Correctional tube and described feedback circuit;
The positive plate of described second compensation condenser connects the common port of described 6th switching tube and described 4th switching tube, and the negative plate of described second compensation condenser connects the negative plate of described first compensation condenser.
Preferably, also comprise: impact damper;
The input end of described impact damper connects the output terminal of described error amplifier, and the output terminal of described impact damper connects the control end of described Correctional tube, and described impact damper is used for when quiescent current is lower than preset value, improves the Slew Rate of the control end of described Correctional tube.
Preferably, described impact damper comprises: twelvemo closes pipe, the 13 switching tube, the 14 switching tube, the 15 switching tube, sixteenmo close pipe and the 17 switching tube;
The input end that described twelvemo closes pipe is all connected described power supply with the input end of described 13 switching tube, the described twelvemo control end that closes pipe connects the output terminal of described error amplifier as the input end of impact damper, the output terminal that described twelvemo closes pipe is connected with the output terminal of described 13 switching tube, and all connecting earth terminal, the control end of described 13 switching tube connects the output terminal of described 13 switching tube;
The input end of described 14 switching tube connects described power supply, and the control end of described 14 switching tube connects the output terminal of described error amplifier,
The input end of described 15 switching tube connects described power supply, and the control end of described 15 switching tube connects the output terminal of described 13 switching tube, and the output terminal of described 15 switching tube connects the control end of described Correctional tube;
Described sixteenmo closes the output terminal of described 14 switching tube of input end connection of pipe, the output terminal that described sixteenmo closes pipe connects earth terminal, described sixteenmo close pipe control end closes the input end of pipe with described sixteenmo respectively, the control end of described 17 switching tube is connected;
The input end of described 17 switching tube connects the output terminal of described 15 switching tube, and the output terminal of described 17 switching tube connects earth terminal.
Preferably,
Described twelvemo closes pipe, described 13 switching tube, described 14 switching tube and described 15 switching tube are PMOS;
Described sixteenmo closes pipe and described 17 switching tube is NMOS tube.
Preferably, described feedback circuit comprises: the first resistance and the second resistance;
One end of described first resistance connects the output terminal of described Correctional tube, the other end of described first resistance connects earth terminal by described second resistance, and the common port of described first resistance and described second resistance is connected the normal phase input end of described error amplifier as the output terminal of feedback resistance.
Preferably, also comprise: filtering circuit;
The input end of described filtering circuit is connected with the output terminal of described low differential voltage linear voltage stabilizer circuit, and the output terminal of described filtering circuit connects earth terminal.
Preferably, described filtering circuit comprises: filter resistance and filter capacitor;
One end of described filter resistance connects the output terminal of described low differential voltage linear voltage stabilizer circuit, and the other end of described filter resistance connects earth terminal;
The positive plate of described filter capacitor connects the output terminal of described low differential voltage linear voltage stabilizer circuit, and the negative plate of described filter capacitor connects earth terminal.
As can be seen from above-mentioned technical scheme, the invention provides a kind of low differential voltage linear voltage stabilizer circuit, comprise error amplifier, Correctional tube, frequency compensated circuit and feedback circuit, frequency compensated circuit comprises two compensation condensers, the input end of frequency compensated circuit connects the output terminal of error amplifier, and the output terminal of frequency compensated circuit connects the output terminal of low differential voltage linear voltage stabilizer circuit.Can find out, the frequency compensation of low differential voltage linear voltage stabilizer circuit adopts two capacitance compensation, the output limit of error amplifier is amplified by two compensation condensers, output node becomes the dominant pole of whole circuit, and be in upper frequency place, thus load change can be ignored the impact exporting pole location, and then improve the stability without the outer electric capacity LDO circuit of sheet.
Accompanying drawing explanation
In order to be illustrated more clearly in the embodiment of the present invention or technical scheme of the prior art, be briefly described to the accompanying drawing used required in embodiment or description of the prior art below, apparently, accompanying drawing in the following describes is only embodiments of the invention, for those of ordinary skill in the art, under the prerequisite not paying creative work, other accompanying drawing can also be obtained according to the accompanying drawing provided.
The circuit diagram of Fig. 1 a kind of low differential voltage linear voltage stabilizer circuit disclosed in the embodiment of the present invention;
The circuit diagram of Fig. 2 another kind of low differential voltage linear voltage stabilizer circuit disclosed in the embodiment of the present invention;
The circuit diagram of Fig. 3 another kind of low differential voltage linear voltage stabilizer circuit disclosed in the embodiment of the present invention;
The circuit diagram of Fig. 4 a kind of small-signal model of low differential voltage linear voltage stabilizer circuit disclosed in the embodiment of the present invention.
Embodiment
Below in conjunction with the accompanying drawing in the embodiment of the present invention, be clearly and completely described the technical scheme in the embodiment of the present invention, obviously, described embodiment is only the present invention's part embodiment, instead of whole embodiments.Based on the embodiment in the present invention, those of ordinary skill in the art, not making the every other embodiment obtained under creative work prerequisite, belong to the scope of protection of the invention.
The embodiment of the invention discloses a kind of low differential voltage linear voltage stabilizer circuit, to realize the raising without the outer electric capacity LDO circuit stability of sheet.
See Fig. 1, the circuit diagram of a kind of low differential voltage linear voltage stabilizer circuit that the embodiment of the present invention provides, comprising: error amplifier EA, Correctional tube M
p, frequency compensated circuit 11 and feedback circuit 12, wherein, frequency compensated circuit 11 comprises two compensation condensers;
Wherein:
The inverting input of error amplifier EA is connected with reference voltage source, the output terminal of error amplifier EA and Correctional tube M
pcontrol end connect, Correctional tube M
poutput terminal connected the normal phase input end of error amplifier EA by feedback circuit 12;
Correctional tube M
pinput end connect power supply VDD, Correctional tube M
pwith the common port of the feedback circuit 12 output terminal V as low pressure difference linear voltage regulator (LowDropoutRegulator, LDO) circuit
outbe connected with the output terminal of frequency compensated circuit 11, the input end of frequency compensated circuit 11 connects the output terminal of error amplifier EA.
It will be appreciated by persons skilled in the art that two compensation condensers in frequency compensated circuit 11 can the output limit of fault in enlargement amplifier EA.
The principle of work of low differential voltage linear voltage stabilizer circuit is as follows:
After supply voltage powers on, reference voltage source produces a reference voltage V close to zero-temperature coefficient system
refand act on the inverting input of error amplifier EA, by error amplifier EA, Correctional tube M
pand feedback circuit 12 forms stable feedback loop, the feedback voltage that feedback circuit 12 exports by error amplifier EA and a reference voltage V
refcompare generation error signal, by amplifying Correctional tube M described error signal
pregulate, and by frequency compensated circuit 11, frequency compensation is carried out to whole circuit, thus make integrated circuit have a stable output voltage.
In summary it can be seen, the frequency compensation of low differential voltage linear voltage stabilizer circuit provided by the invention adopts two capacitance compensation, the output limit of error amplifier EA is amplified by two compensation condensers, output node becomes the dominant pole of whole circuit, and be in upper frequency place, thus load change can be ignored the impact exporting pole location, and then improve the stability without the outer electric capacity LDO circuit of sheet.
For optimizing above-described embodiment further, see Fig. 2, a kind of circuit diagram of low differential voltage linear voltage stabilizer circuit disclosed in another embodiment of the present invention, on basis embodiment illustrated in fig. 1, also comprises: impact damper 13;
The input end of impact damper 13 connects the output terminal of error amplifier EA, and the output terminal of impact damper 13 connects Correctional tube M
pcontrol end, impact damper 13, for when quiescent current is lower than preset value, improves Correctional tube M
pthe Slew Rate of control end.
For optimizing above-described embodiment further, also comprise: filtering circuit 14;
The output terminal V of filtering circuit 14 input end and low differential voltage linear voltage stabilizer circuit
outconnect, the output terminal of filtering circuit 14 connects earth terminal, and filtering circuit 14 carries out filtering for the voltage exported low differential voltage linear voltage stabilizer circuit.
Wherein, filtering circuit 14 comprises filter resistance R
lwith filter capacitor C
l;
Filter resistance R
lone end connect the output terminal V of LDO circuit
out, filter resistance R
lthe other end connect earth terminal;
Filter capacitor C
lpositive plate connect the output terminal V of LDO circuit
out, filter capacitor C
lnegative plate connect earth terminal.
Effect due to error amplifier EA is by feedback voltage and reference voltage V
refcompare generation error signal, by amplifying Correctional tube M described error signal
pregulate, finally make the output voltage stabilization of whole circuit, therefore, the performance quality of error amplifier EA directly has influence on the various performance parameters of whole circuit, as load regulation, line regulation etc.For reaching very low load and line regulation, usually require that error amplifier EA has higher gain, therefore, error amplifier EA generally adopts Folded-cascode amplifier or two stage amplifer structure.Because two stage amplifer can produce two limits, need other design compensation circuit to produce and offset a limit zero point, this adds the design difficulty of whole circuit compensation network undoubtedly.Meanwhile, can reduce the impact of pole and zero on loop because Folded-cascode amplifier has single-stage amplifier, thus reduce the advantage compensating difficulty, Folded-cascode amplifier also can provide larger gain and larger loop bandwidth.Therefore, the present invention adopts Folded-cascode amplifier as error amplifier EA.
See Fig. 3, the circuit diagram of the low differential voltage linear voltage stabilizer circuit that the embodiment of the present invention provides, error amplifier EA comprises: the first switching tube M
1, second switch pipe M
2, the 3rd switching tube M
3, the 4th switching tube M
4, the 5th switching tube M
5, the 6th switching tube M
6, the 7th switching tube M
7, the 8th switching tube M
8, the 9th switching tube M
9, the tenth switching tube M
10with the 11 switching tube M
11;
Wherein:
Described 11 switching tube M
11input end connect power supply VDD, described 11 switching tube M
11control end connect the first bias voltage V
b0, described 11 switching tube M
11output terminal connect described first switching tube M respectively
1input end and described second switch pipe M
2input end;
Described first switching tube M
1control end connect described feedback circuit 12 as the normal phase input end of error amplifier EA (feedback voltage be V
fb), described second switch pipe M
2control end connect described reference voltage source as the inverting input of described error amplifier EA (reference voltage be V
rEF);
Described 9th switching tube M
9input end and described tenth switching tube M
10input end all connect described power supply VDD, described 9th switching tube M
9control end and described tenth switching tube M
10control end connect;
Described 7th switching tube M
7input end connect described 9th switching tube M
9output terminal, described 7th switching tube M
7output terminal connect described 9th switching tube M
9control end, described 7th switching tube M
7control end connect and described 8th switching tube M
8control end and the common port of two control ends connects the second bias voltage V
b1, described 8th switching tube M
8input end connect described tenth switching tube M
10output terminal;
Described 5th switching tube M
5input end connect described 7th switching tube M
7output terminal, described 5th switching tube M
5control end connect described 6th switching tube M
6control end and the common port of two control ends connect the 3rd bias voltage V
b3, described 6th switching tube M
6input end connect described 8th switching tube M
8output terminal, wherein, described 6th switching tube M
6with described 8th switching tube M
8common port as the output terminal of described error amplifier EA;
Described 3rd switching tube M
3input end connect described 5th switching tube M
5output terminal, and described 3rd switching tube M
3input end connect described first switching tube M
1output terminal, described 3rd switching tube M
3output terminal connect earth terminal GND, described 3rd switching tube M
3control end connect described 4th switching tube M
4control end and the common port of two control ends connect the 4th bias voltage V
b2, described 4th switching tube M
4input end connect described 6th switching tube M
6output terminal, and described 4th switching tube M
4input end connect described second switch pipe M
2output terminal, described 4th switching tube M
4output terminal connect earth terminal GND.
It should be noted that, in error amplifier EA, described first switching tube M
1, described second switch pipe M
2, described 7th switching tube M
7, described 8th switching tube M
8, described 9th switching tube M
9, described tenth switching tube M
10with described 11 switching tube M
11for PMOS;
Described 3rd switching tube M
3, described 4th switching tube M
4, described 5th switching tube M
5with described 6th switching tube M
6for NMOS tube.
As can be seen from the figure, the input of error amplifier EA is PMOS to pipe, thus error amplifier EA can be made still normally to work when inputting low voltage, VDD is soft starting control electric pressure, has three bias voltages to provide direct current biasing point for amplifier in tube-in-tube structure.
For error amplifier EA, its DC characteristic of Water demand and AC characteristic.
(1) DC characteristic: comprise input voltage range, input common mode electrical level, output voltage swing, quiescent current etc.The input voltage range of the error amplifier EA of the present invention's design is 0 ~ (VDD-|V
dS11|-| V
gS1|), this error amplifier EA normally can work when input voltage is low to moderate 0V, wherein, and V
dS11be the 11 switching tube M
11drain-source voltage, V
gS1be the first switching tube M
1gate source voltage.
The scope of the output voltage of error amplifier EA is (V
dS5+ V
dS3) ~ (VDD-|V
gS9|), wherein, V
dS5be the 5th switching tube M
5drain-source voltage, V
dS3be the 3rd switching tube M
3drain-source voltage, V
gS9be the 9th switching tube M
9gate source voltage.Therefore, error amplifier EA provided by the invention has wider output voltage swing.
(2) AC characteristic: comprise open-loop gain, phase margin, unity gain bandwidth, Power Supply Rejection Ratio etc.
Suppose, two compensation condensers in frequency compensated circuit 11 are respectively the first compensation condenser C
3with the second compensation condenser C
4;
See Fig. 3, the first compensation condenser C
3positive plate connect described 6th switching tube M
6with described 8th switching tube M
8common port, the first compensation condenser C
3negative plate connect Correctional tube M
pwith the common port of feedback circuit 12;
Second compensation condenser C
4positive plate connect described 6th switching tube M
6with described 4th switching tube M
4common port, the second compensation condenser C
4negative plate connect the first compensation condenser C
3negative plate.
It should be noted that, buffering 13 output stage in the present invention adopts push-pull cascade structure, to make under extremely low quiescent current, can significantly improve Correctional tube M
pthe Slew Rate of control end, and then improve transient response.
See Fig. 3, impact damper 13 comprises: twelvemo closes pipe M
12, the 13 switching tube M
13, the 14 switching tube M
14, the 15 switching tube M
15, sixteenmo closes pipe M
16with the 17 switching tube M
17;
Wherein:
Described twelvemo closes pipe M
12input end and described 13 switching tube M
13input end all connect described power supply VDD, described twelvemo closes pipe M
12control end connect output terminal (the i.e. described 6th switching tube M of error amplifier EA as the input end of impact damper 13
6with described 8th switching tube M
8common port), described twelvemo closes pipe M
12output terminal and described 13 switching tube M
13output terminal connect, and all connect earth terminal GND, described 13 switching tube M
13control end connect described 13 switching tube M
13output terminal;
Described 14 switching tube M
14input end connect described power supply VDD, described 14 switching tube M
14control end connect the output terminal of described error amplifier EA,
Described 15 switching tube M
15input end connect described power supply VDD, described 15 switching tube M
15control end connect described 13 switching tube M
13output terminal, described 15 switching tube M
15output terminal connect described Correctional tube M
pcontrol end;
Described sixteenmo closes pipe M
16input end connect described 14 switching tube M
14output terminal, described sixteenmo closes pipe M
16output terminal connect earth terminal GND, described sixteenmo closes pipe M
16control end close pipe M with described sixteenmo respectively
16input end, described 17 switching tube M
17control end connect;
Described 17 switching tube M
17input end connect described 15 switching tube M
15output terminal, described 17 switching tube M
17output terminal connect earth terminal GND.
It should be noted that, in impact damper 13, described twelvemo closes pipe M
12, described 13 switching tube M
13, described 14 switching tube M
14with described 15 switching tube M
15for PMOS;
Described sixteenmo closes pipe M
16with described 17 switching tube M
17for NMOS tube.
It should be noted that, feedback circuit 12 comprises: the first resistance R
f1with the second resistance R
f2(see Fig. 3);
First resistance R
f1one end connect Correctional tube M
poutput terminal, the first resistance R
f1the other end by the second resistance R
f2connect earth terminal GND, the first resistance R
f1with the second resistance R
f2common port connect the normal phase input end of error amplifier EA as the output terminal of feedback circuit 12.
The impact that load can be made to change exporting pole location for further illustrating low differential voltage linear voltage stabilizer circuit provided by the invention can be ignored, and the present invention is illustrated from system transter angle again.
See Fig. 4, the circuit diagram of the small-signal model of a kind of low differential voltage linear voltage stabilizer circuit that the embodiment of the present invention provides, by carrying out analysis and calculation to this model, can try to achieve its transport function.
Wherein, g
m1represent the input mutual conductance of error amplifier, R
1represent the equivalent output impedance of error amplifier, C
1represent the equivalent output capacitance of error amplifier, g
m2represent the input mutual conductance of impact damper, R
2represent the equivalent output impedance of impact damper, C
2represent the equivalent output capacitance of impact damper, g
m3represent the input mutual conductance of Correctional tube, R
eqrepresent LDO integrated circuit output terminal V
outequiva lent impedance, C
lrepresent LDO integrated circuit output terminal V
outequivalent output capacitance, g
m6represent the 6th switching tube M
6input mutual conductance, V
iNrepresent the voltage of error amplifier, g
m1v
iNrepresent the equivalent current of error amplifier, V
irepresent the voltage of impact damper, g
m2v
irepresent the equivalent current of impact damper, V
2represent the voltage of impact damper, g
m3v
2represent the equivalent current of Correctional tube, C
3represent the first compensation condenser, C
4represent the second compensation condenser; (1)
System transter H (s) is:
A in formula (1)
1, a
2, a
3and a
4be respectively:
a
1＝g
m2g
m3R
1R
2R
eq(C
3+C
4)(2)；
a
3≈R
1R
2R
eqC
2C
3C
L(4)；
Limit P can be obtained by formula (4)
1~ P
4with Z at zero point
1~ Z
3be respectively:
Four limit P are had in LDO
1~ P
4with three zero point Z
1~ Z
3.Because the electric capacity of error amplifier EA output terminal has been exaggerated g
m2g
m3r
1r
2r
eq(C
3+ C
4) doubly, therefore error amplifier EA output terminal limit P
1become the dominant pole of whole circuit.Due to the 6th switching tube M
6input mutual conductance g
m6very little, the 6th switching tube M
6output terminal produce limit P
2be a high frequency poles, too much influence is not had to the stability of LDO.
The limit P that buffer output end produces
3because of with become zero pole point Z zero point
2to and cancel out each other, thus the impact of the stability of LDO can be ignored.LDO output terminal limit P
4numerical value be exaggerated g
m2r
2doubly, so LDO output terminal limit P
4also at higher frequency place, and zero point Z
3also at very high frequency place, therefore all pole and zeros can be ignored the impact of the stability of LDO.
In summary it can be seen, the frequency compensation of low differential voltage linear voltage stabilizer circuit provided by the invention adopts two capacitance compensation, the output limit of error amplifier EA is amplified by two compensation condensers, output node becomes the dominant pole of whole circuit, and be in upper frequency place, thus load change can be ignored the impact exporting pole location, and then improve the stability without the outer electric capacity LDO circuit of sheet.
Meanwhile, the output stage of impact damper 13 adopts push-pull cascade structure, to make under extremely low quiescent current, can significantly improve Correctional tube M
pthe Slew Rate of control end, and then improve transient response.
Finally, low differential voltage linear voltage stabilizer circuit provided by the invention is wireless plug-in capacitor, thus improve the integrated level of power management chip.
Finally, also it should be noted that, in this article, the such as relational terms of first and second grades and so on is only used for an entity or operation to separate with another entity or operational zone, and not necessarily requires or imply the relation that there is any this reality between these entities or operation or sequentially.And, term " comprises ", " comprising " or its any other variant are intended to contain comprising of nonexcludability, thus make to comprise the process of a series of key element, method, article or equipment and not only comprise those key elements, but also comprise other key elements clearly do not listed, or also comprise by the intrinsic key element of this process, method, article or equipment.When not more restrictions, the key element limited by statement " comprising ... ", and be not precluded within process, method, article or the equipment comprising described key element and also there is other identical element.
In this instructions, each embodiment adopts the mode of going forward one by one to describe, and what each embodiment stressed is the difference with other embodiments, between each embodiment identical similar portion mutually see.
To the above-mentioned explanation of the disclosed embodiments, professional and technical personnel in the field are realized or uses the present invention.To be apparent for those skilled in the art to the multiple amendment of these embodiments, General Principle as defined herein can without departing from the spirit or scope of the present invention, realize in other embodiments.Therefore, the present invention can not be restricted to these embodiments shown in this article, but will meet the widest scope consistent with principle disclosed herein and features of novelty.
Claims (10)
1. a low differential voltage linear voltage stabilizer circuit, is characterized in that, comprising: error amplifier, Correctional tube, frequency compensated circuit and feedback circuit, and wherein, described frequency compensated circuit comprises two compensation condensers;
The inverting input of described error amplifier is connected with reference voltage source, and the output terminal of described error amplifier is connected with the control end of described Correctional tube, and the output terminal of described Correctional tube connects the normal phase input end of described error amplifier by described feedback circuit;
The input end of described Correctional tube connects power supply, the common port of described Correctional tube and described feedback circuit is connected with the output terminal of described frequency compensated circuit as the output terminal of low differential voltage linear voltage stabilizer circuit, and the input end of described frequency compensated circuit connects the output terminal of described error amplifier;
The feedback voltage that described feedback circuit exports by described error amplifier and reference voltage compare generation error signal, by amplifying described error signal, described Correctional tube is regulated, and by described frequency compensated circuit, frequency compensation is carried out to whole circuit.
2. low differential voltage linear voltage stabilizer circuit according to claim 1, it is characterized in that, described error amplifier comprises: the first switching tube, second switch pipe, the 3rd switching tube, the 4th switching tube, the 5th switching tube, the 6th switching tube, the 7th switching tube, the 8th switching tube, the 9th switching tube, the tenth switching tube and the 11 switching tube;
The input end of described 11 switching tube connects described power supply, the control end of described 11 switching tube connects the first bias voltage, and the output terminal of described 11 switching tube connects the input end of described first switching tube and the input end of described second switch pipe respectively;
The control end of described first switching tube connects described feedback circuit as the normal phase input end of error amplifier, and the control end of described second switch pipe connects described reference voltage source as the inverting input of described error amplifier;
The input end of described 9th switching tube is all connected described power supply with the input end of described tenth switching tube, and the control end of described 9th switching tube is connected with the control end of described tenth switching tube;
The input end of described 7th switching tube connects the output terminal of described 9th switching tube, the output terminal of described 7th switching tube connects the control end of described 9th switching tube, the control end of described 7th switching tube connects with the described control end of the 8th switching tube and the common port of two control ends is connected the second bias voltage, and the input end of described 8th switching tube connects the output terminal of described tenth switching tube;
The input end of described 5th switching tube connects the output terminal of described 7th switching tube, the control end of described 5th switching tube connects the control end of described 6th switching tube and the common port of two control ends connects the 3rd bias voltage, the input end of described 6th switching tube connects the output terminal of described 8th switching tube, wherein, the common port of described 6th switching tube and described 8th switching tube is as the output terminal of described error amplifier;
The input end of described 3rd switching tube connects the output terminal of described 5th switching tube, and the input end of described 3rd switching tube connects the output terminal of described first switching tube, the output terminal of described 3rd switching tube connects earth terminal, the control end of described 3rd switching tube connects the control end of described 4th switching tube and the common port of two control ends connects the 4th bias voltage, the input end of described 4th switching tube connects the output terminal of described 6th switching tube, and the input end of described 4th switching tube connects the output terminal of described second switch pipe, the output terminal of described 4th switching tube connects earth terminal.
3. low differential voltage linear voltage stabilizer circuit according to claim 2, is characterized in that,
Described first switching tube, described second switch pipe, described 7th switching tube, described 8th switching tube, described 9th switching tube, described tenth switching tube and described 11 switching tube are PMOS;
Described 3rd switching tube, described 4th switching tube, described 5th switching tube and described 6th switching tube are NMOS tube.
4. low differential voltage linear voltage stabilizer circuit according to claim 2, is characterized in that, two described compensation condensers are respectively the first compensation condenser and the second compensation condenser;
The positive plate of described first compensation condenser connects the common port of described 6th switching tube and described 8th switching tube, and the negative plate of described first compensation condenser connects the common port of described Correctional tube and described feedback circuit;
The positive plate of described second compensation condenser connects the common port of described 6th switching tube and described 4th switching tube, and the negative plate of described second compensation condenser connects the negative plate of described first compensation condenser.
5. low differential voltage linear voltage stabilizer circuit according to claim 1, is characterized in that, also comprises: impact damper;
The input end of described impact damper connects the output terminal of described error amplifier, and the output terminal of described impact damper connects the control end of described Correctional tube, and described impact damper is used for when quiescent current is lower than preset value, improves the Slew Rate of the control end of described Correctional tube.
6. low differential voltage linear voltage stabilizer circuit according to claim 5, is characterized in that, described impact damper comprises: twelvemo closes pipe, the 13 switching tube, the 14 switching tube, the 15 switching tube, sixteenmo close pipe and the 17 switching tube;
The input end that described twelvemo closes pipe is all connected described power supply with the input end of described 13 switching tube, the described twelvemo control end that closes pipe connects the output terminal of described error amplifier as the input end of impact damper, the output terminal that described twelvemo closes pipe is connected with the output terminal of described 13 switching tube, and all connecting earth terminal, the control end of described 13 switching tube connects the output terminal of described 13 switching tube;
The input end of described 14 switching tube connects described power supply, and the control end of described 14 switching tube connects the output terminal of described error amplifier,
The input end of described 15 switching tube connects described power supply, and the control end of described 15 switching tube connects the output terminal of described 13 switching tube, and the output terminal of described 15 switching tube connects the control end of described Correctional tube;
Described sixteenmo closes the output terminal of described 14 switching tube of input end connection of pipe, the output terminal that described sixteenmo closes pipe connects earth terminal, described sixteenmo close pipe control end closes the input end of pipe with described sixteenmo respectively, the control end of described 17 switching tube is connected;
The input end of described 17 switching tube connects the output terminal of described 15 switching tube, and the output terminal of described 17 switching tube connects earth terminal.
7. low differential voltage linear voltage stabilizer circuit according to claim 6, is characterized in that,
Described twelvemo closes pipe, described 13 switching tube, described 14 switching tube and described 15 switching tube are PMOS;
Described sixteenmo closes pipe and described 17 switching tube is NMOS tube.
8. low differential voltage linear voltage stabilizer circuit according to claim 1, is characterized in that, described feedback circuit comprises: the first resistance and the second resistance;
One end of described first resistance connects the output terminal of described Correctional tube, the other end of described first resistance connects earth terminal by described second resistance, and the common port of described first resistance and described second resistance is connected the normal phase input end of described error amplifier as the output terminal of feedback resistance.
9. low differential voltage linear voltage stabilizer circuit according to claim 1, is characterized in that, also comprises: filtering circuit;
The input end of described filtering circuit is connected with the output terminal of described low differential voltage linear voltage stabilizer circuit, and the output terminal of described filtering circuit connects earth terminal.
10. low differential voltage linear voltage stabilizer circuit according to claim 9, is characterized in that, described filtering circuit comprises: filter resistance and filter capacitor;
One end of described filter resistance connects the output terminal of described low differential voltage linear voltage stabilizer circuit, and the other end of described filter resistance connects earth terminal;
The positive plate of described filter capacitor connects the output terminal of described low differential voltage linear voltage stabilizer circuit, and the negative plate of described filter capacitor connects earth terminal.
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Cited By (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108964454A (en) * | 2017-05-17 | 2018-12-07 | 中芯国际集成电路制造(上海)有限公司 | DC-DC conversion circuitry and forming method thereof |
| CN109450234A (en) * | 2018-12-14 | 2019-03-08 | 杭州士兰微电子股份有限公司 | Ideal diode and its control circuit |
| CN109976429A (en) * | 2019-04-19 | 2019-07-05 | 宁波大学 | Regulated power supply in a kind of current feedback zero-temperature coefficient piece |
| CN110032232A (en) * | 2018-01-12 | 2019-07-19 | 中芯国际集成电路制造(北京)有限公司 | A kind of electric power controller and power supply device |
| WO2020119774A1 (en) * | 2018-12-14 | 2020-06-18 | 华润矽威科技（上海）有限公司 | Integrating circuit and integrating method thereof |
| CN111367340A (en) * | 2018-12-26 | 2020-07-03 | 北京兆易创新科技股份有限公司 | Low dropout linear voltage stabilizing circuit |
| CN111555610A (en) * | 2020-05-13 | 2020-08-18 | 成都明夷电子科技有限公司 | Power supply quick response voltage-stabilized power supply circuit based on 5G communication system |
| CN112394768A (en) * | 2020-12-03 | 2021-02-23 | 南京英锐创电子科技有限公司 | Voltage stabilizer |
| CN112650345A (en) * | 2020-12-23 | 2021-04-13 | 杭州晶华微电子股份有限公司 | Semiconductor device with a plurality of semiconductor chips |
| CN113342106A (en) * | 2021-06-04 | 2021-09-03 | 广东希荻微电子股份有限公司 | Low dropout regulator and control system |
| WO2022134042A1 (en) * | 2020-12-25 | 2022-06-30 | 中国科学院微电子研究所 | Signal driving system with constant slew rate |
| CN114879794A (en) * | 2022-05-25 | 2022-08-09 | 西安微电子技术研究所 | On-chip capacitor implementation circuit for LDO frequency compensation and LDO circuit |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2000039923A (en) * | 1998-07-23 | 2000-02-08 | Nec Corp | Voltage regulator |
| US20060192538A1 (en) * | 2005-02-25 | 2006-08-31 | O2Micro, Inc. | Low drop-out voltage regulator with enhanced frequency compensation |
| CN101364119A (en) * | 2008-07-07 | 2009-02-11 | 武汉大学 | Wide dynamic range and low voltage difference linear constant voltage regulator |
| CN101419479A (en) * | 2008-12-10 | 2009-04-29 | 武汉大学 | Low-voltage difference linear constant voltage regulator with novel structure |
| CN103092241A (en) * | 2011-10-27 | 2013-05-08 | 厦门立昂电子科技有限公司 | Mixed compensating type high-stability LDO (low-dropout regulator) chip circuit |
-
2016
- 2016-01-29 CN CN201610067306.8A patent/CN105573396B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2000039923A (en) * | 1998-07-23 | 2000-02-08 | Nec Corp | Voltage regulator |
| US20060192538A1 (en) * | 2005-02-25 | 2006-08-31 | O2Micro, Inc. | Low drop-out voltage regulator with enhanced frequency compensation |
| CN101364119A (en) * | 2008-07-07 | 2009-02-11 | 武汉大学 | Wide dynamic range and low voltage difference linear constant voltage regulator |
| CN101419479A (en) * | 2008-12-10 | 2009-04-29 | 武汉大学 | Low-voltage difference linear constant voltage regulator with novel structure |
| CN103092241A (en) * | 2011-10-27 | 2013-05-08 | 厦门立昂电子科技有限公司 | Mixed compensating type high-stability LDO (low-dropout regulator) chip circuit |
Non-Patent Citations (1)
| Title |
|---|
| 王义凯，王忆，巩文超，何乐年: "大电流、高稳定性的LDO线形稳压器", 《半导体学报》 * |
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|---|---|---|---|---|
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| CN108964454B (en) * | 2017-05-17 | 2020-07-28 | 中芯国际集成电路制造(上海)有限公司 | DC-DC conversion circuit system and forming method thereof |
| CN110032232A (en) * | 2018-01-12 | 2019-07-19 | 中芯国际集成电路制造(北京)有限公司 | A kind of electric power controller and power supply device |
| CN109450234A (en) * | 2018-12-14 | 2019-03-08 | 杭州士兰微电子股份有限公司 | Ideal diode and its control circuit |
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| CN111367340A (en) * | 2018-12-26 | 2020-07-03 | 北京兆易创新科技股份有限公司 | Low dropout linear voltage stabilizing circuit |
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| CN112394768A (en) * | 2020-12-03 | 2021-02-23 | 南京英锐创电子科技有限公司 | Voltage stabilizer |
| CN112394768B (en) * | 2020-12-03 | 2022-04-29 | 南京英锐创电子科技有限公司 | Voltage stabilizer |
| CN112650345A (en) * | 2020-12-23 | 2021-04-13 | 杭州晶华微电子股份有限公司 | Semiconductor device with a plurality of semiconductor chips |
| CN112650345B (en) * | 2020-12-23 | 2022-05-17 | 杭州晶华微电子股份有限公司 | Semiconductor device with a plurality of semiconductor chips |
| WO2022134042A1 (en) * | 2020-12-25 | 2022-06-30 | 中国科学院微电子研究所 | Signal driving system with constant slew rate |
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| US11474551B1 (en) | 2021-06-04 | 2022-10-18 | Halo Microelectronics Co., Ltd. | Low-dropout linear regulator and control system |
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