CN101339443B - Broad output current scope low pressure difference linear manostat - Google Patents

Broad output current scope low pressure difference linear manostat Download PDF

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CN101339443B
CN101339443B CN200810048738XA CN200810048738A CN101339443B CN 101339443 B CN101339443 B CN 101339443B CN 200810048738X A CN200810048738X A CN 200810048738XA CN 200810048738 A CN200810048738 A CN 200810048738A CN 101339443 B CN101339443 B CN 101339443B
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China
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pmos transistor
circuit
input
grid
output
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CN200810048738XA
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CN101339443A (en
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江金光
张提升
刘经南
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武汉大学
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Abstract

A low dropout linear voltage regulator with wide output current range and low pressure difference, comprises an error amplifier in the folding common source and common gate structure, a buffer circuit, a driving element, a feedback circuit, a load capacitance equivalent series resistance compensating circuit and a multistage Miller compensation circuit, wherein the buffer circuit changes the low frequency pole into a medium frequency pole and a high frequency pole; the large load capacitance of the load capacitance equivalent series resistance compensating circuit pushes the main pole to the low frequency, causing the gain crossover point to push inwards, and generating a medium frequency zero point for counteracting the medium frequency pole connected serially with the equivalent series resistance; the stride multilevel Miller compensation circuit generates a medium high frequency pole and a medium high frequency zero point slightly smaller than the medium high frequency pole for advancing the phase margin, thereby not only adding the unity gain bandwidth, but also saving considerable chip area. When the output current has a large change range, the structure provided by the invention generates wider unity gain bandwidth, provides the phase margin of greater than 85 degrees, ensures the stability of the system and advances the low pressure difference linear voltage stabilization performance.

Description

Broad output current scope low pressure difference linear manostat
Technical field
The present invention relates to a kind of low pressure difference linear voltage regulator, particularly a kind of low pressure difference linear voltage regulator with broad output current scope.
Background technology
Current demand to the high-performance feed circuit makes the sustainable development of voltage stabilizer equipment.Many low voltage products, the equipment such as employing mobile batteries such as notebook computer, mobile phone, mobile DVD, MP3, cameras all need use low pressure reduction (LDO) voltage stabilizer.These portable electric appts need low pressure drop and little quiescent current to increase the effect and the life-span of battery usually.
Usually, the LDO voltage stabilizer provides specific direct-flow steady voltage, and the voltage difference between the input of this voltage and output is less.The LDO voltage stabilizer is usually used in providing required power supply to circuit.Typical low-dropout regulator structural representation as shown in Figure 1, LDO voltage stabilizer normally error amplifier, two element connected in series of driving element connects.Error amplifier is connected to an input end of LDO voltage stabilizer, and driving element is connected to an output terminal of LDO voltage stabilizer, thereby driving element can drive external loading.Usually also provide feedback circuit to the LDO voltage stabilizer, the output voltage of dividing potential drop is fed back to error amplifier by voltage divider.
Nowadays low pressure difference linear voltage regulator is used for various electronic equipments more and more widely, and along with the widespread use of low pressure difference linear voltage regulator, no matter be in design, still in commercial production, we are more and more higher to the requirement of low pressure difference linear voltage regulator.Indexs such as the loading range of voltage stabilizer, response speed, stability all require us to reach.Wherein the stability problem of low pressure difference linear voltage regulator is most important.
In typical low pressure difference linear voltage regulator, dominant pole f0 is positioned at output end of voltage stabilizer, and the first non-dominant pole f1 is positioned at the grid of driving element.The first non-dominant pole is by the output impedance of error amplifier and the grid stray capacitance decision of driving element, when the output impedance of error amplifier and driving element size design are unreasonable, it is very near that the dominant pole of low pressure difference linear voltage regulator and the first non-dominant pole will lean on, in this case, low pressure difference linear voltage regulator is unsettled.Because of low pressure difference linear voltage regulator self unreasonable causing the low pressure difference linear voltage regulator instability of design, the size variation of output current also can make the instability of low pressure difference linear voltage regulator change except above-mentioned.
Typical low pressure difference linear voltage regulator flows through most of current direction load of driving element, that is: I as a voltage source L≈ I DSo, dominant pole frequency:
f 0 = λ I D 2 π C L ≈ λ I L 2 π C L
As seen, the dominant pole frequency f0 of low pressure difference linear voltage regulator is with load current I LVariation and change, load current is big more, dominant pole frequency is more away from true origin; Load current is more little, and dominant pole frequency is the closer to left side initial point.Usually low pressure difference linear voltage regulator is under unloaded and fully loaded two kinds of maximal work situations, the variation range of load current is very big, the result has caused the dominant pole frequency position of low pressure difference linear voltage regulator also wide variation taking place, thereby can cause the low pressure difference linear voltage regulator job insecurity.
The variation that typical low pressure difference linear voltage regulator is an inherence, external all unsettled system, especially load current is difficult to prediction especially to the influence of low pressure difference linear voltage regulator stability.Fig. 1 has provided the structural representation of existing a kind of typical low pressure difference linear voltage regulator.This circuit is made up of error amplifier 101, driving element 103, feedback circuit 104, load capacitance 105 and pull-up resistor 106.The output voltage of low pressure difference linear voltage regulator produces feedback voltage INN after feedback circuit 104 samplings.Reference voltage INP and feedback voltage INN are connected to the in-phase input end and the inverting input of error amplifier 101 respectively, its voltage difference produces a control signal after error amplifier 101 amplifies, this control signal is used for regulating the duty of driving element 103, thereby the output voltage of guaranteeing low pressure difference linear voltage regulator still is nominal value when supply voltage, working temperature, loading condition variation.
In the system shown in Figure 1, there are two low-frequency pole, an output terminal that is positioned at low pressure difference linear voltage regulator, another is positioned at driving element 103 grid places.Dominant pole is formed by load capacitance 105 and pull-up resistor 106, and the first non-dominant pole is formed by the gate capacitance of driving element 103 and the output impedance of error amplifier 101.Because low pressure difference linear voltage regulator need drive bigger load current, so the size of driving element 103 is bigger, its gate capacitance is also bigger, makes the non-dominant pole of winning be positioned at low frequency./ 10th place's phase places about pole frequency just begin to change greatly, and amplitude then is just to descend near pole frequency, and limit is big to the influence of the influence comparison amplitude of phase place.Because dominant pole frequency changes with output current, and have two low-frequency pole to exist, phase crossover occurs in before the gain cross-over probably, and this system is a potential time-dependent system.
Fig. 2 has provided existing a kind of traditional structural representation with frequency compensated low pressure difference linear voltage regulator.The difference of this circuit and circuit shown in Figure 1 is: this circuit has increased buffer circuit 102, and the input end of buffer circuit 102 is connected to the output terminal of error amplifier 101, and the output terminal of buffer circuit 102 is connected to the input end of driving element 103; Employed in addition load capacitance 105 has very little equivalent series resistance, the load capacitance equivalent series resistance compensating circuit 105 that is promptly proposed among the present invention, and remainder is identical with Fig. 1.Among the figure, it is OPA that error amplifier 101 indicates element according to custom, and 102 of buffer current are denoted as BUF.
In the system shown in Figure 2, have a low-frequency pole, this dominant pole is positioned at the output terminal of low pressure difference linear voltage regulator, and this limit is formed by load capacitance and pull-up resistor.Have an intermediate frequency limit, as the intermediate frequency limit of the first non-dominant pole between error amplifier 101 and buffering circuit 102.Because buffer circuit has the feature that input impedance is big, output impedance is little, and the input capacitance of buffer circuit 102 is little a lot of than the grid capacitance of driving element 103, so the low frequency first non-dominant pole originally is after adding buffer circuit 102, substituted by an intermediate frequency first non-dominant pole and a high frequency poles, high frequency poles is between buffer circuit 102 and driving element 103, and other stray capacitance also can produce high frequency poles.Because dominant pole frequency changes with load current, cause the dominant pole distance first non-dominant pole possibility nearer, add the existence of second, third non-dominant pole, system is a potential time-dependent system.
For guaranteeing the steady operation of low pressure difference linear voltage regulator, a kind of load capacitance equivalent series resistance compensating circuit 105 that circuit shown in Figure 2 uses, be to utilize load capacitance and its intermediate frequency of equivalent series resistance generation zero point, be used for offsetting the first non-dominant pole this zero point, and all the other limits except that dominant pole are outside unity gain bandwidth, thereby the phase margin of the system of assurance is greater than 45 degree.
In the circuit shown in Figure 2, owing to be subject to the position of the second non-dominant pole and the 3rd non-dominant pole, the unity gain bandwidth of low pressure difference linear voltage regulator is narrower.Narrower unity gain bandwidth not only causes the response speed of system slack-off, and has limited the DC current gain of system, if the DC current gain of low pressure difference linear voltage regulator is low, and the also corresponding reduction of its output voltage precision.Owing to be subjected to the restriction of condition of work, manufacturing process variations and model order of accuarcy etc., can't the accurate Calculation second non-dominant pole when circuit design and the position of the 3rd non-dominant pole, this has just increased frequency compensated difficulty.For guaranteeing that designed circuit can steady operation, further other performances of sacrificing of needs usually.
As seen, can stablize, work reliably, when low pressure difference linear voltage regulator designs, must carry out the stabiloity compensation design it in order to make low pressure difference linear voltage regulator.Low pressure difference linear voltage regulator stability is not enough, no matter in design, still in commercial production, all requires its improvement.
Summary of the invention
Technical matters to be solved by this invention is: overcome the deficiencies in the prior art, a kind of improved low pressure difference linear voltage regulator is provided, expanded the unity gain bandwidth of low pressure difference linear voltage regulator, improve the phase margin of system, greatly improved the stability of low pressure difference linear voltage regulator system when the output current variation range is big.
Technical solution of the present invention is: be made up of error amplifier, buffer circuit, driving element, feedback circuit and compensating circuit, error amplifier is provided with preset voltage input end and feedback voltage input end, the output terminal of error amplifier connects the input end of buffer circuit, the output terminal of buffer circuit connects the input end of driving element, the drive output of driving element connects feedback circuit, feedback circuit dividing potential drop gained feedback voltage is delivered to the feedback voltage input end of error amplifier, it is characterized in that: described error amplifier adopts the folded common source and common grid structure; Described compensating circuit is by striding multistage Miller's compensating circuit and load capacitance equivalent series resistance compensating circuit is formed, one end of striding multistage Miller's compensating circuit is connected with error amplifier, the other end strides across the drive output that is connected driving element after two-stage or the above amplification, one end of load capacitance equivalent series resistance compensating circuit is connected the drive output of driving element, and the other end is connected with ground voltage.
And described error amplifier adopts folded common source and common grid operation transconductance amplifier structure, promptly form by difference input circuit, common grid amplifying circuit and single-ended output circuit,
Described difference input circuit comprises PMOS differential amplifier circuit and current source, and current source is couple to supply voltage VDDA, and output current is to the PMOS differential amplifier circuit; Described PMOS differential amplifier circuit comprises first difference input PMOS transistor MP1A and second difference input PMOS transistor MP1B,, first difference input PMOS transistor MP1A links to each other with the source electrode of second difference input PMOS transistor MP1B; Feedback voltage inserts the grid of first difference input PMOS transistor MP1A, and preset voltage inserts the grid of second difference input PMOS transistor MP1B; The drain current of first difference input PMOS transistor MP1A outputs to the first difference output end IN1, and the drain current of second difference input PMOS transistor MP1B outputs to the second difference output end IN2;
Described grid amplifying circuit altogether comprises that the first current mirror nmos pass transistor MN3A, the second current mirror nmos pass transistor MN3B, first are total to grid and amplify nmos pass transistor MN2A and second grid amplification nmos pass transistor MN2B altogether; The source electrode of the first current mirror nmos pass transistor MN3A is connected ground voltage GNDA, and drain electrode is connected to the first difference output end IN1, and grid is input as the 5th bias voltage Vbias5; The source electrode of the second current mirror nmos pass transistor MN3B is connected ground voltage GNDA, and drain electrode is connected to the second difference output end IN2, and grid is input as the 5th bias voltage Vbias5; First source electrode that is total to grid amplification nmos pass transistor MN2A is connected to the first difference output end IN1, and drain electrode is connected to first node N1, and grid is input as the 4th bias voltage Vbias4; Second source electrode that is total to grid amplification nmos pass transistor MN2B is connected to the second difference output end IN2, and drain electrode is connected to the output terminal of error amplifier, and grid is input as the 4th bias voltage Vbias4.
Described single-ended output circuit comprises the first current mirror PMOS transistor MP2A, the second current mirror PMOS transistor MP2B, the 3rd current mirror PMOS transistor MP3A and the 4th current mirror PMOS transistor MP3B; The source electrode of the first current mirror PMOS transistor MP2A is connected supply voltage VDDA, and drain electrode is connected to the source electrode of the 3rd current mirror PMOS transistor MP3A, and grid is connected to first node N1; The source electrode of the second current mirror PMOS transistor MP2B is connected supply voltage VDDA, and drain electrode is connected to the source electrode of the 4th current mirror PMOS transistor MP3B, and grid is connected to first node N1; The 3rd current mirror PMOS transistor MP3A source electrode is connected to the drain electrode of the first current mirror PMOS transistor MP2A, and drain electrode is connected to first node N1, and grid is input as the 3rd bias voltage Vbias3; The source electrode of the 4th current mirror PMOS transistor MP3B is connected to the drain electrode of the second current mirror PMOS transistor MP2B, and drain electrode is connected to the output terminal of error amplifier, and grid is input as the 3rd bias voltage Vbias3;
And described driving element includes first and drives PMOS transistor MPOUT, and first grid that drives PMOS transistor MPOUT is connected to the output terminal of buffer circuit, and source electrode is connected supply voltage VDDA, and drain electrode provides drive output.
And described buffer circuit is made of source follower circuit and current-sensing circuit, and the input end of current-sensing circuit is connected to driving element, and the output terminal of current-sensing circuit is connected to the output terminal of source follower circuit; Described source follower circuit adopts PMOS transistor MPSF and direct current biasing transistor MPB1; The grid of PMOS transistor MPSF is connected to the output terminal of error amplifier, and source electrode is connected to driving element, and drain electrode is connected to ground voltage GNDA; The drain electrode of direct current biasing transistor MPB1 connects the source electrode of PMOS transistor MPSF.
And the breadth length ratio of PMOS transistor MPSF and direct current biasing transistor MPB1 is less than first breadth length ratio that drives PMOS transistor MPOUT, and greater than other transistorized breadth length ratio in the low pressure difference linear voltage regulator.
And, describedly stride multistage Miller's compensating circuit and adopt the first compensation condenser C1, the first compensation condenser C1 stride three grades of amplifications be connected in first drain electrode and second that drives PMOS transistor MPOUT altogether grid amplify between the source electrode of nmos pass transistor MN2B;
Described load capacitance equivalent series resistance compensating circuit comprises the first load capacitance CL and the first equivalent series resistance RO, the first equivalent series resistance RO is the equivalent series resistance of the first load capacitance CL, the first load capacitance CL, one end is connected in the drain electrode of the first driving PMOS transistor MPOUT, and the other end is connected with the first equivalent series resistance R0; The first equivalent series resistance RO, one end is connected with the first load capacitance CL, and the other end is connected ground voltage GNDA.
And the load capacitance equivalent series resistance compensating circuit in the described compensating circuit adopts external structure.
The invention provides low pressure difference linear voltage regulator with big output current scope, adopt the folded common source and common grid structure as error amplifier, carry out the frequency compensated while making full use of the load capacitance equivalent series resistance, adopted and striden multistage miller compensation structure.This structure has increased the distance of the dominant pole and the first non-dominant pole greatly, and has a zero point between the dominant pole and the first non-dominant pole, and other parasitic poles has been pulled to beyond the unity gain bandwidth.And the source follower that adds reasonable size can further improve system stability as buffer circuit.The present invention has widened the unity gain bandwidth of low pressure difference linear voltage regulator, improved the phase margin of low pressure difference linear voltage regulator, greatly improve the stability of low pressure difference linear voltage regulator system when the output current variation range is big, thereby improved the performance of low pressure difference linear voltage regulator.
Description of drawings
Figure 1 shows that the structural representation of a kind of typical low pressure difference linear voltage regulator in the prior art;
Figure 2 shows that a kind of traditional structural representation in the prior art with frequency compensated low pressure difference linear voltage regulator;
Figure 3 shows that the structural representation of the embodiment of the invention;
The agent structure that Figure 4 shows that the embodiment of the invention realizes circuit;
Figure 5 shows that the frequency response chart of the embodiment of the invention under the output current normal condition;
Figure 6 shows that the frequency response chart of the embodiment of the invention under the big situation of output current;
Figure 7 shows that the frequency response chart of the embodiment of the invention under the less situation of output current.
Embodiment
The present invention is directed to the deficiency that the typical low pressure difference linear voltage regulator of tradition exists at aspects such as stability, proposed a kind ofly when the output current variation range is big, still have the above phase margin of 85 degree, the circuit structure that system can steady operation.Fig. 3 has provided the structural representation of the embodiment of the invention, and a kind of low pressure difference linear voltage regulator with big output current scope is provided, for the ease of clear performance technical scheme of the present invention, and the unified symbol of the respective element of Fig. 1, Fig. 2, Fig. 3.This circuit is by error amplifier 101, buffer circuit 102, driving element 103, feedback circuit 104, load capacitance equivalent series resistance compensating circuit 105, pull-up resistor 106 and stride multistage Miller's compensating circuit 107 and form.Error amplifier 101 is folded common source and common grid structures, form by difference input circuit, common grid amplifying circuit and single-ended output circuit, in-phase input end of error amplifier 101 (being the preset voltage input end) and inverting input (being the feedback voltage output terminal) are connected respectively to the feedback voltage INN of reference voltage INP and output voltage generation after feedback circuit 104 samplings, and the output terminal of error amplifier is connected to the input end of buffer circuit 102; Produce a control signal by buffer circuit, this control signal is used for regulating the duty of driving element 103; Output signal is sent by the drive output OUT of driving element 103; Load capacitance equivalent series resistance compensating circuit 105 1 ends are connected to the drive output OUT of driving element 103, and an end is connected to ground voltage GNDA; Stride multistage Miller's compensating circuit 107 1 ends and be connected to the output terminal of the homophase difference input pipe of error amplifier 101, the common grid of striding error amplifier 101 amplify, 103 3 grades of buffer circuit 102 and driving elements, and the other end is connected to the drive output OUT of driving element 103.Striding multistage meaning is two-stage or more than the two-stage, as long as in general the connected mode science, strides to such an extent that progression is many more, required electric capacity is more little, saves chip area.The embodiment of the invention to stride multistage Miller's compensating circuit 107 be three grades, also can select secondary, level Four etc. when specifically implementing according to circuit formation situation.For example on the circuit structure basis of the embodiment of the invention, change the employing secondary, only need to stride multistage Miller's compensating circuit 107 1 ends and be connected to drive output OUT, the other end is connected between error amplifier 101 and the buffer circuit 102, so just the building-out capacitor that needs is bigger, and effect slightly is worse than the situation of striding three grades.
In the circuit shown in Figure 3, have a low-frequency pole, be positioned at the output terminal of low pressure difference linear voltage regulator, because of load capacitance is bigger, the low-frequency pole that is produced by load capacitance and output impedance is a dominant pole; There is an intermediate frequency limit, between error amplifier 101 and buffering circuit 102, because of the error amplifier output impedance of folded common source and common grid structure is bigger, be the first non-dominant pole with the intermediate frequency limit that the input capacitance that cushions circuit produces by error amplifier output impedance; Have intermediate frequency zero point, be positioned at the output terminal of low pressure difference linear voltage regulator, because of output load capacitance is very big, produce intermediate frequency zero point by output load capacitance and its equivalent series resistance, this intermediate frequency is used for offsetting the first non-dominant pole zero point; There is a medium-high frequency limit, be positioned at the output terminal of error amplifier 101 homophase difference input pipes, bigger because of striding multistage miller compensation electric capacity in the equivalent capacity of this point, produce a medium-high frequency limit, the i.e. second non-dominant pole by the output impedance of striding multistage miller compensation electric capacity and homophase difference input pipe; There is medium-high frequency zero point, between error amplifier 101 and buffering circuit 102, by striding the equivalent capacity and the drain-source equiva lent impedance generation medium-high frequency zero point that be total to grid amplifier tube of multistage miller compensation electric capacity, be slightly larger than the second non-dominant pole this zero point at homophase difference input pipe output terminal; Other high frequency utmost points are positioned at outside the unity gain bandwidth zero point.
By Fig. 3 circuit zero pole distribution as can be known, the first non-dominant pole is output the intermediate frequency counteracting at zero point that end produces; The cause second non-dominant pole is far away and stationkeeping apart from dominant pole, and dominant pole frequency does not change and can bring influence to system stability with output current; Have exist a zero point that is slightly less than the second non-dominant pole, can improve phase margin, improve system stability; Other non-dominant poles are positioned at front end, can enough not become to threaten to system stability.So the phase margin of native system is bigger, low pressure difference linear voltage regulator stability when the output current variation range is big is better.
The agent structure that Fig. 4 has provided the embodiment of the invention realizes circuit.This circuit is the specific implementation circuit structure of Fig. 3 structural representation, and this circuit is by error amplifier 101, buffer circuit 102, driving element 103, feedback circuit 104, load capacitance equivalent series resistance compensating circuit 105, pull-up resistor 106 and stride multistage Miller's compensating circuit 107 and form.Annexation between each unit has been set forth clear when Fig. 3 is described, will specify the stability problem of the structure function and the system of each unit below.
Error amplifier 101 adopts folded common source and common grid operation transconductance amplifier structures, promptly is made up of difference input circuit, common grid amplifying circuit and single-ended output circuit.The difference input circuit only amplifies differential signal, and common-mode signal is suppressed, and has very strong antijamming capability, and has temperature and float advantages such as being easy to direct coupling between little, level and the level.In order to improve the gain of error amplifier, adopt cascode structure, the CMOS cascode structure has sleeve and folding two kinds of versions.Tube-in-tube structure has characteristics such as frequency characteristic is good, low in energy consumption, yet under low supply voltage, its output voltage swing and common-mode input range are difficult to reach the expection requirement.From application point, error amplifier of the present invention will require fast as far as possible speed at operation at low power supply voltage, and therefore bigger output voltage swing and input common-mode range adopt the folded common source and common grid structure.In addition, adopt PMOS as input stage, can accomplish that common mode input is minimum can meet the low pressure difference linear voltage regulator design philosophy to ground voltage GNDA, and can make error amplifier have lower noise.PMOS transistor MP1A, MP1B are that difference is imported pipe, and nmos pass transistor MN2A, MN2B are for being total to the grid amplifier tube, and transistor MP1A, MP1B and MN2A, MN2B form and import the folded common source and common grid structure.PMOS transistor MP2A, MP2B, MP3A, MP3B constitute common-source common-gate current mirror, not only be used for both-end output is converted into single-ended output, but also can increase substantially the output impedance of error amplifier 101, thereby the gain that helps improving error amplifier 101.First to the 5th bias voltage Vbias1 ~ 5 that is marked on the embodiment circuit that Fig. 4 provides, current source circuit is used for stablizing rational grid voltage for the bias current sources in the main circuit provides.These bias voltages can provide correct grid voltage for corresponding MOS device, thereby the current source that corresponding MOS device is constituted has stable and accurate electric current to offer main operating circuit.
Buffer circuit 102 is made of source follower and current-sensing circuit.Source follower is connected between error amplifier 101 and the driving element 103, plays the buffering buffer action.The output impedance of error amplifier 101 is very high, and driving element 103 is bigger because of driving bigger current loading size, cause gate capacitance bigger, if error amplifier 101 directly is connected with driving element 103, will produce a low-frequency pole, and low-dropout regulator also will produce a low-frequency pole at output terminal because of the existence of the big electric capacity of load, and the existence of two low-frequency pole causes system's instability easily.Play buffer action so between error amplifier 101 and driving element 103, increase a source follower.Source follower utilizes the grid received signal, utilizes the source drive load, makes source potential can follow grid voltage.Source follower shows higher input impedance and lower output impedance.Its output impedance is inversely proportional to its mutual conductance, and its mutual conductance and transistorized breadth length ratio are directly proportional, the breadth length ratio that suitably increases source follower not only can reduce the output impedance of source follower itself, also can strengthen simultaneously the regulating action of its output control signal to driving element 103, help driving element 103 operate as normal, be unlikely to enter too early cut-off region.Under the buffering buffer action of source follower, suitably select the size of source follower, the low-frequency pole that produces between original error amplifier 101 and the driving element 103 can be converted into an intermediate frequency limit and a high frequency poles, because of error amplifier 101 output impedance higher, the source follower gate capacitance is less relatively, source follower output impedance is very little, thus the intermediate frequency limit between error amplifier 101 and source follower, high frequency poles is between source follower and driving element.The source follower circuit of the embodiment of the invention adopts PMOS transistor MPSF and direct current biasing transistor MPB1, current-sensing circuit also is provided, current-sensing circuit is made of PMOS transistor MPDEC0, MPDEC1, MPDEC2 and nmos pass transistor MNDEC1, MNDEC2, and current-sensing circuit is used for improving the transient response characteristic of low pressure difference linear voltage regulator.Because of the current-sensing circuit specific implementation has multiple choices, and buffer circuit 102 places that specifically are connected among Fig. 4 of the part of the current-sensing circuit in the embodiment of the invention have embodiment, do not repeat them here.In general, the breadth length ratio that described PMOS transistor MPSF and direct current biasing transistor MPB1 adopt is less than first breadth length ratio that drives PMOS transistor MPOUT, and greater than other transistorized breadth length ratio in the low pressure difference linear voltage regulator.During concrete enforcement, the breadth length ratio that can select PMOS transistor MPSF and direct current biasing transistor MPB1 is first to drive the breadth length ratio about 1/10 of PMOS transistor MPOUT, is about 10 times of other transistorized breadth length ratios in the low pressure difference linear voltage regulator.For example, choosing the first breadth length ratio numerical value that drives PMOS transistor MPOUT is W=20L=2Num=400, and the breadth length ratio numerical value of PMOS transistor MPSF is W=15L=4Num=56.
The specific implementation of driving element 103 is very simple, can adopt first to drive PMOS transistor MPOUT, first grid that drives PMOS transistor MPOUT connects the output terminal of buffer circuit 102, and source electrode is connected to supply voltage VDDA, and drain electrode provides drive output OUT.Driving element is because will drive bigger load current, so size is bigger, gate capacitance is also bigger.The load current of low pressure difference linear voltage regulator can change in a big way, thereby causes the output impedance of driving element that bigger variation is also arranged, and dominant pole frequency can change with the variation of load current as a result.
The present invention also provides the specific design of feedback circuit 140: feedback circuit 104 includes the first feedback resistance R1 and the second feedback resistance R2, the first feedback resistance R1 is connected to described first and drives between the feedback voltage input end of the drain electrode of PMOS transistor MPOUT and described error amplifier 101, and the second feedback resistance R2 is connected between the feedback voltage input end of ground voltage GNDA and described error amplifier 101.
Load capacitance equivalent series resistance compensating circuit 105 is connected in series by the big electric capacity of load and its equivalent series resistance and forms.Big electric capacity one end of load is connected to the output terminal of low pressure difference linear voltage regulator, and the other end is connected with equivalent series resistance; Equivalent series resistance one end is connected with load capacitance, and the other end is connected to ground voltage GNDA.The load capacitance value is 10uF, and bigger load capacitance value can advance dominant pole to low frequency, makes dominant pole as much as possible away from the second non-dominant pole, thereby gain cross-over is advanced inwards, increases phase margin, improves system stability.The series connection of equivalent series resistance and load capacitance produces intermediate frequency zero point, can offset the first non-dominant pole, thereby reduce the limit number, and phase crossover is outwards advanced, and increases phase margin, improves system stability.
The present invention has also proposed to stride multistage Miller's compensating circuit 107 emphatically.Miller compensation capacitor C c one end is connected to the drain electrode of error amplifier 101 1 difference input transistors MP1B, other end source follower PMOS transistor MPSF and driving element 103PMOS transistor MPOUT totally three grades of amplifications in the common grid amplifier transistor MN2B of error amplifier 101, buffer circuit 102 are connected to the output terminal of low pressure difference linear voltage regulator.Stride multistage miller compensation and can reduce the value of building-out capacitor significantly, save considerable chip area, with much bigger bandwidth is provided, improve phase margin, in specific implementation circuit of the present invention, can also produce simultaneously medium-high frequency zero point, play crucial effects in the system stability of the low pressure difference linear voltage regulator of inventing with big output current scope, effect is very obvious.
Fig. 4 realizes circuit as the agent structure of the embodiment of the invention, and utmost point The Distribution of Zeros has determined the stability of system in the system.
In low pressure difference linear voltage regulator, output terminal produces a low-frequency pole, i.e. dominant pole P0, to circuit analysis as can be known:
P 0 ≈ 1 2 π ( R L | | r 0 ) C L
R wherein 0Be the drain electrode output impedance of driving element 103, C LBe load capacitance, R LIt is pull-up resistor; The output impedance of error amplifier 101 is bigger, the input capacitance of buffer circuit 103 is bigger and relatively large because of the size of source follower MPSF, between error amplifier 101 and buffering circuit 102, produce an intermediate frequency limit, the i.e. first non-dominant pole P1, if error amplifier output impedance is R1, the input gate capacitance of buffer circuit is C1, then has:
P 1 ≈ 1 2 π R 1 C 1 ;
Produce an intermediate frequency Z1 at zero point by load capacitance CL and its equivalent series resistance R0:
Z 1 ≈ 1 2 π R 0 C L ,
If the gain of grid amplifier transistor MN2B is A1 altogether, the gain of source follower transistor MPSF is A2, the gain of driving element transistor MPOUT is-A3 that then striding multistage miller compensation capacitor C c is that (A3) Cc establishes it and is Ca 1-A1A2 in the drain electrode equivalence direct earth capacitance of difference input transistors MP1B.When carrying out small-signal analysis, the earth impedance of the drain electrode of difference input transistors MP1B is the drain resistance r of MP1B 01BDrain resistance r with current source MN3B 03BParallel connection, the drain-source resistance of grid amplifier stage transistor MN2B is r altogether 02B, a medium-high frequency limit produces in drain electrode place of difference input transistors MP1B, i.e. the second non-dominant pole P2:
P 2 ≈ 1 2 π ( r 01 B | | r 03 B ) Ca
When carrying out small-signal analysis, r between error amplifier 101 and buffering circuit 102 02BThe ground connection of connecting with Ca produces a medium-high frequency Z2 at zero point:
Z 2 ≈ 1 2 π r 02 B Ca
Be slightly less than the second non-dominant pole P2 this zero point; The utmost point that other stray capacitance produces all is positioned at front end zero point, to the not influence of stability of system.
Because the CL value is bigger,, gain cross-over is advanced inwards so dominant pole P0 advances to low frequency end; Rationally adjust transistor parameter, the intermediate frequency Z1 and the first non-dominant pole P1 offset; Because of P2 at front end, and the P2 value fixes, so P2 distance P 0 is far away, so not only reduced the limit number in the unity gain bandwidth, increased unity gain bandwidth simultaneously; Another one Z2 at zero point is arranged between dominant pole and P2, and it relatively near P2, can improve phase margin.So not only the dominant pole P0 distance second non-dominant pole P2 far away and before non-dominant pole arrives, have one zero point Z2, realized total phase shift is reduced to minimum, phase crossover is outwards advanced, the while gain cross-over advances inwards.So in big electric current variation range, under the bigger prerequisite of unity gain bandwidth, phase margin has all reached more than 85 degree, system is highly stable.
In order to further specify the stablizing effect of the present invention system under the bigger situation of output current variation range, the embodiment of the invention is normal at output current respectively, output current has carried out emulation with Hspice software to the frequency response of circuit shown in Figure 4 greatly and under the less three kinds of situations of output current.
When output current is 25mA, be output current just often, it is the voltage source of 1V for the 2.5V alternating voltage that the preset voltage input end adopts a direct current voltage, the feedback voltage input end connects a big capacity earth, connect the drive output OUT of a big inductance to driving element 103, output load is that 100 Europe resistance and 10uF electric capacity are connected in parallel, and the equivalent series resistance of load capacitance is 1 Europe.Fig. 5 has the low differential voltage linear voltage stabilizer circuit of big output current scope at output current frequency response chart just often for the present invention.Wherein, left scale is represented phase place, unit degree of being; Right scale is represented amplitude, and unit is a decibel; Following scale is represented frequency, and unit is a hertz.Among Fig. 5, dotted line is a phase frequency curve, and cross wires is an amplitude frequency curve.Analyze this figure as can be known: at first, can see clearly that from the curve map of this frequency response there is not the limit of RHP in this system, the unity gain bandwidth broad, low-frequency gain is higher; Secondly, be to the maximum about 90 degree in the phase deviation of the above system of 0dB, respective phase nargin reaches nearly 90 degree, greater than 45 degree that require; Once more, in unity gain bandwidth, a Z2 at zero point who is not cancelled is arranged, cause the non-dominant pole that comprises P2 all to be advanced to beyond the unity gain bandwidth, clearly, such system is very stable.
When output current is 310mA, be that output current is when big, it is the voltage source of 1V for the 2.5V alternating voltage that the preset voltage input end adopts a direct current voltage, the feedback voltage input end connects a big capacity earth, connect the drive output OUT of a big inductance to driving element 103, output load is that 8 Europe resistance and 10uF electric capacity are connected in parallel, and the equivalent series resistance of load capacitance is 1 Europe.Fig. 6 has the frequency response chart of low differential voltage linear voltage stabilizer circuit when output current is big of big output current scope for the present invention.Wherein, left scale is represented phase place, unit degree of being; Right scale is represented amplitude, and unit is a decibel; Following scale is represented frequency, and unit is a hertz.Among Fig. 6, dotted line is a phase frequency curve, and cross wires is an amplitude frequency curve.Analyze this figure as can be known: at first, can see clearly that from the curve map of this frequency response there is not the limit of RHP in this system, the unity gain bandwidth broad, low-frequency gain is higher; Secondly, be to the maximum about 90 degree in the phase deviation of the above system of 0dB, respective phase nargin reaches nearly 90 degree, greater than 45 degree that require; Once more, in unity gain bandwidth, a Z2 at zero point who is not cancelled is arranged, cause the non-dominant pole that comprises P2 all to be advanced to beyond the unity gain bandwidth; At last, though it is a lot of that dominant pole outwards advances because output current is big, dominant pole P0 distance second non-dominant pole P2 and medium-high frequency Z2 at zero point are far away, so dominant pole outwards advances phase margin is not had, clearly, such system is very stable.
When output current is 0.05mA, be output current hour, it is the voltage source of 1V for the 2.5V alternating voltage that the preset voltage input end adopts a direct current voltage, the feedback voltage input end connects a big capacity earth, connect the drive output OUT of a big inductance to driving element 103, output load is that 50K Europe resistance and 10uF electric capacity are connected in parallel, and the equivalent series resistance of load capacitance is 1 Europe.Fig. 7 has the low differential voltage linear voltage stabilizer circuit of big output current scope at output current frequency response chart just often for the present invention.Wherein, left scale is represented phase place, unit degree of being; Right scale is represented amplitude, and unit is a decibel; Following scale is represented frequency, and unit is a hertz.Among Fig. 7, dotted line is a phase frequency curve, and cross wires is an amplitude frequency curve.Analyze this figure as can be known: at first, can see clearly that from the curve map of this frequency response there is not the limit of RHP in this system, low-frequency gain is higher; Secondly, be to the maximum about 90 degree in the phase deviation of the above system of 0dB, respective phase nargin reaches nearly 90 degree, greater than 45 degree that require; Once more, in unity gain bandwidth, a Z2 at zero point who is not cancelled is arranged, cause the non-dominant pole that comprises P2 all to be advanced to beyond the unity gain bandwidth; At last, cause the dominant pole low frequency to advance because output current is less, thereby gain cross-over advances inwards, unity gain bandwidth decreases, and clearly, such system is very stable.
What particularly point out is, circuit of the present invention is constituted the situation of doing to be equal to replacement, all should fall in the present invention's technical scheme scope required for protection.

Claims (5)

1. broad output current scope low pressure difference linear manostat, by error amplifier, buffer circuit, driving element, feedback circuit and compensating circuit are formed, error amplifier is provided with preset voltage input end and feedback voltage input end, the output terminal of error amplifier connects the input end of buffer circuit, the output terminal of buffer circuit connects the input end of driving element, the drive output of driving element connects feedback circuit, feedback circuit dividing potential drop gained feedback voltage is delivered to the feedback voltage input end of error amplifier, it is characterized in that: described error amplifier adopts the folded common source and common grid structure; Described compensating circuit is by striding multistage Miller's compensating circuit and load capacitance equivalent series resistance compensating circuit is formed, one end of striding multistage Miller's compensating circuit is connected with error amplifier, the other end strides across the drive output that is connected driving element after two-stage or the above amplification, one end of load capacitance equivalent series resistance compensating circuit is connected the drive output of driving element, and the other end is connected with ground voltage;
Described error amplifier adopts folded common source and common grid operation transconductance amplifier structure, promptly forms by difference input circuit, common grid amplifying circuit and single-ended output circuit,
Described difference input circuit comprises PMOS differential amplifier circuit and current source, and current source is couple to supply voltage VDDA, and output current is to the PMOS differential amplifier circuit; Described PMOS differential amplifier circuit comprises difference input PMOS transistor MP1A and difference input PMOS transistor MP1B, and the source electrode of difference input PMOS transistor MP1A links to each other with the source electrode of difference input PMOS transistor MP1B; The grid of feedback voltage access differential input PMOS transistor MP1A, the grid of preset voltage access differential input PMOS transistor MP1B; The drain current of difference input PMOS transistor MP1A outputs to the first difference output end IN1, and the drain current of difference input PMOS transistor MP1B outputs to the second difference output end IN2;
Described grid amplifying circuit altogether comprises current mirror nmos pass transistor MN3A, current mirror nmos pass transistor MN3B, grid amplify nmos pass transistor MN2A and are total to grid amplification nmos pass transistor MN2B altogether; The source electrode of current mirror nmos pass transistor MN3A is connected ground voltage GNDA, and drain electrode is connected to the first difference output end IN1, and grid is input as bias voltage Vbias5; The source electrode of current mirror nmos pass transistor MN3B is connected ground voltage GNDA, and drain electrode is connected to the second difference output end IN2, and grid is input as bias voltage Vbias5; The source electrode of grid amplification nmos pass transistor MN2A is connected to the first difference output end IN1 altogether, and drain electrode is connected to first node N1, and grid is input as bias voltage Vbias4; The source electrode of grid amplification nmos pass transistor MN2B is connected to the second difference output end IN2 altogether, and drain electrode is connected to the output terminal of error amplifier, and grid is input as bias voltage Vbias4;
Described single-ended output circuit comprises current mirror PMOS transistor MP2A, current mirror PMOS transistor MP2B, current mirror PMOS transistor MP3A and current mirror PMOS transistor MP3B; The source electrode of current mirror PMOS transistor MP2A is connected supply voltage VDDA, and the drain electrode of current mirror PMOS transistor MP2A is connected to the source electrode of current mirror PMOS transistor MP3A, and the grid of current mirror PMOS transistor MP2A is connected to first node N1; The source electrode of current mirror PMOS transistor MP2B is connected supply voltage VDDA, and the drain electrode of current mirror PMOS transistor MP2B is connected to the source electrode of current mirror PMOS transistor MP3B, and the grid of current mirror PMOS transistor MP2B is connected to first node N1; The source electrode of current mirror PMOS transistor MP3A is connected to the drain electrode of current mirror PMOS transistor MP2A, and the drain electrode of current mirror PMOS transistor MP3A is connected to first node N1, and the grid of current mirror PMOS transistor MP3A is input as bias voltage Vbias3; The source electrode of current mirror PMOS transistor MP3B is connected to the drain electrode of current mirror PMOS transistor MP2B, and the drain electrode of current mirror PMOS transistor MP3B is connected to the output terminal of error amplifier, and the grid of current mirror PMOS transistor MP3B is input as bias voltage Vbias3;
Described driving element includes and drives PMOS transistor MPOUT, and the grid that drives PMOS transistor MPOUT is connected to the output terminal of buffer circuit, and source electrode is connected supply voltage VDDA, and drain electrode provides drive output;
Describedly stride multistage Miller's compensating circuit and adopt the first compensation condenser C1, the first compensation condenser C1 stride three grades of amplifications be connected in the drain electrode that drives PMOS transistor MPOUT and altogether grid amplify between the source electrode of nmos pass transistor MN2B;
Described load capacitance equivalent series resistance compensating circuit comprises the first load capacitance CL and the first equivalent series resistance RO, the first equivalent series resistance RO is the equivalent series resistance of the first load capacitance CL, the first load capacitance CL, one end is connected in the drain electrode that drives PMOS transistor MPOUT, and the other end is connected with the first equivalent series resistance RO; The first equivalent series resistance RO, one end is connected with the first load capacitance CL, and the other end is connected ground voltage GNDA.
2. broad output current scope low pressure difference linear manostat according to claim 1, it is characterized in that: described buffer circuit is made of source follower circuit and current-sensing circuit, the input end of current-sensing circuit is connected to driving element, and the output terminal of current-sensing circuit is connected to the output terminal of source follower circuit; Described source follower circuit adopts PMOS transistor MPSF and direct current biasing transistor MPB1; The grid of PMOS transistor MPSF is connected to the output terminal of error amplifier, and source electrode is connected to driving element, and drain electrode is connected to ground voltage GNDA; The drain electrode of direct current biasing transistor MPB1 connects the source electrode of PMOS transistor MPSF.
3. broad output current scope low pressure difference linear manostat according to claim 2, it is characterized in that: the breadth length ratio of described PMOS transistor MPSF and direct current biasing transistor MPB1 is less than the breadth length ratio that drives PMOS transistor MPOUT, and greater than other transistorized breadth length ratio in the low pressure difference linear voltage regulator.
4. broad output current scope low pressure difference linear manostat according to claim 1, it is characterized in that: described feedback circuit includes the first feedback resistance R1 and the second feedback resistance R2, the first feedback resistance R1 is connected between the feedback voltage input end of the drain electrode of described driving PMOS transistor MPOUT and described error amplifier, and the second feedback resistance R2 is connected between the feedback voltage input end and ground voltage GNDA of described error amplifier.
5. according to claim 1 or 2 or 3 or 4 described broad output current scope low pressure difference linear manostats, it is characterized in that: the load capacitance equivalent series resistance compensating circuit in the described compensating circuit adopts external structure.
CN200810048738XA 2008-08-08 2008-08-08 Broad output current scope low pressure difference linear manostat CN101339443B (en)

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