CN105429601A - High-slew rate PSRR enhanced single-stage amplifier suitable for power management - Google Patents
High-slew rate PSRR enhanced single-stage amplifier suitable for power management Download PDFInfo
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- CN105429601A CN105429601A CN201510851992.3A CN201510851992A CN105429601A CN 105429601 A CN105429601 A CN 105429601A CN 201510851992 A CN201510851992 A CN 201510851992A CN 105429601 A CN105429601 A CN 105429601A
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Abstract
The invention discloses a high-slew rate PSRR enhanced single-stage amplifier suitable for power management. The amplifier is composed of twenty seven MOS transistors, including the first to the fifteenth PMOS transistors M0, M1a, M1b, M2a, M2b, M13a, M13b, M14a, M14b, M5, M6, M7, M8, M9 and M10, and the first to the twelfth NMOS transistors M11a, M11b, M11c, M12a, M12b, M12c, M3a, M3b, M3c, M4a, M4b and M4c; the second to the fifth PMOS transistors M1a, M1b, M2a and M2b are selected as signal input ends, differential mode signals Vin+ and Vin- are respectively input, and the differential mode signals Vin+ and Vin- orderly pass through a first tearing differential input stage, a slew rate enhancement current mirror and a PSRR enhanced stage, and are output to a Vout. According to the invention, under the condition of low-voltage, low-power consumption, same area and same power consumption, slew rate SR of the amplifier is increased and PSRR is enhanced, and the amplifier has relatively high direct current gain and bandwidth expansion characteristics.
Description
Technical field
The present invention relates to Design of Amplifiers field, particularly relate to a kind of high Slew Rate PSRR enhancement mode one-stage amplifier.
Background technology
The compensation technique of modern low-voltage and low-power dissipation single stage operational amplifier can be widely used in portable electric appts, such as: in battery of mobile phone and the equipment such as Notebook Battery, LDO, LCD.And power supply management device needs the amplifier of high Slew Rate and voltage immunity to external world, the namely amplifier of high Slew Rate height power supply ripple rejection ability.General folded common source and common grid one-stage amplifier can meet above requirement, has a lot of report to adopt the mutual conductance of tearing input stage recently, then carrys out by cascode current mirror the technology that multiplication current strengthens DC current gain and mutual conductance.Suitably insert at the output offset end of cascode current mirror the Slew Rate that shunt bias transistor can improve amplifier.Adopt in output stage in addition and intersect positive feedback technique and can heighten the parameters such as the common-mode rejection ratio (CMRR) of output and Power Supply Rejection Ratio (PSRR).
The present invention is based on above technology, adopt Recyclingfoldedcascade technology and PSRR to strengthen technology and realize under same power consumption and chip area condition, amplifier has the performance that high Slew Rate SR and PSRR strengthens.Amplifier can also have higher DC current gain simultaneously.
Summary of the invention
In order to overcome the problem of the DC system fault isolation difficulty that above-mentioned prior art exists, the present invention proposes a kind of high Slew Rate PSRR enhancement mode one-stage amplifier being applicable to power management, this operation amplifier circuit can improve the Slew Rate SR of amplifier and strengthen PSRR under equal chip area condition, and has higher DC current gain.
The present invention proposes a kind of high Slew Rate PSRR enhancement mode one-stage amplifier being applicable to power management, described amplifier by the first to the 15 PMOS transistor M0, M1a, M1b, M2a, M2b, M13a, M13b, M14a, M14b, M5, M6, M7, M8, M9, M10 and first to the tenth bi-NMOS transistor M11a, M11b, M11c, M12a, M12b, M12c, M3a, M3b, M3c, M4a, M4b, M4c totally two ten seven MOS transistor form; Wherein:
The first, the source electrode of the 8th to the 11 PMOS transistor M0, M14a, M14b, M5, M6 meets power supply VDD jointly; The substrate termination power supply VDD of all PMOS transistor M0, M1a, M1b, M2a, M2b, M13a, M13b, M14a, M14b, M5, M6, M7, M8, M9, M10; The Substrate ground GND of first to the tenth bi-NMOS transistor M11a, M11b, M11c, M11d, M12a, M12b, M12c, M12d, M3a, M3b, M3c, M4a, M4b, M4c; The source electrode common ground GND of the 7th to the tenth bi-NMOS transistor M3a, M3b, M3c, M4a, M4b, M4c;
The first, the grid of the 8th, the 9th PMOS transistor M0, M14a, M14b meets the first bias voltage Vb1; The drain electrode of the first PMOS transistor M0 connects the source electrode of the second to the 5th PMOS transistor M1a, M1b, M2a, M2b; The grid of the second to the 3rd PMOS transistor M1a, M1b meets input Vp; The grid of the 4th to the 5th PMOS transistor M2a, M2b meets input Vn;
The drain electrode of the second PMOS transistor M1a, the source electrode of the 6th nmos pass transistor M12c connect the drain electrode of the tenth nmos pass transistor M4a jointly; The drain electrode of the 4th PMOS transistor M2a, the source electrode of the 3rd nmos pass transistor M11c connect the drain electrode of the 7th nmos pass transistor M3a jointly;
The drain electrode of the 3rd PMOS transistor M1b, the grid of the 7th to the 9th nmos pass transistor M3a, M3b, M3c connect the drain electrode of the second nmos pass transistor M11b jointly; The drain electrode of the 5th PMOS transistor M2b, the grid of the tenth to the tenth bi-NMOS transistor M4a, M4b, M4c connect the drain electrode of the 5th nmos pass transistor M12b jointly; The grid of first to the 6th nmos pass transistor M11a, M11b, M11c, M12a, M12b, M12c meets the second bias voltage Vb3 jointly; The source electrode of the second nmos pass transistor M11b connects the drain electrode of the 9th nmos pass transistor M3c; The source electrode of the first nmos pass transistor M11a connects the drain electrode of the 8th nmos pass transistor M3b; The source electrode of the 5th nmos pass transistor M12b connects the drain electrode of the tenth bi-NMOS transistor M4c; The source electrode of the 4th nmos pass transistor M12a connects the drain electrode of the 11 nmos pass transistor M4b;
The drain electrode of the 3rd nmos pass transistor M11c, the drain electrode of the 6th PMOS transistor M13a, the drain electrode of the 14 PMOS transistor M9 connect the grid of the 13 PMOS transistor M8 jointly; The drain electrode of the 6th nmos pass transistor M12c, the drain electrode of the 7th PMOS transistor M13b, the drain electrode of the 15 PMOS transistor M10 connect the grid of the 12 PMOS transistor M7 jointly; The drain electrode of the 8th PMOS transistor M14a, the source electrode of the 6th PMOS transistor M13a connect the drain electrode of the first nmos pass transistor M11a jointly; The drain electrode of the 9th PMOS transistor M14b, the source electrode of the 7th PMOS transistor M13b connect the drain electrode of the 4th nmos pass transistor M12a jointly; Six, the 7th, the 14, the grid common ground two bias voltage Vb2 of the 15 PMOS transistor M13a, M13b, M9, M10; Ten, the grid of the 11 PMOS transistor M5, M6 connects the drain electrode of the 12 PMOS transistor M7 and the source electrode of the 14 PMOS transistor M9 jointly; The drain electrode of the tenth PMOS transistor M5 connects the source electrode of the 12 PMOS transistor M7; The drain electrode of the 11 PMOS transistor M6 connects the source electrode of the 13 PMOS transistor M8; The drain electrode of the 13 PMOS transistor M8, the source electrode of the 15 PMOS transistor M10 meet output end vo ut jointly;
Choose the second to the 5th PMOS transistor M1a, M1b, M2a and M2b as signal input part, input difference mode signal Vin+ and Vin-respectively, through first tearing differential input stage, Slew Rate strengthens current mirror, eventually pass PSRR booster stage outputs to Vout.
The present invention with under homalographic and consumption conditions at low-voltage and low-power dissipation, improves the Slew Rate SR of amplifier and strengthens PSRR, and having higher DC current gain and bandwidth expansion characteristic.
Accompanying drawing explanation
Fig. 1 is the circuit diagram of operational amplifier.
Embodiment
Described amplifier strengthens current mirror by Recyclingfoldedcascode amplifying stage, Slew Rate, PSRR enhanced portion is grouped into.Recyclingfoldedcascode (loop collapsing cascade) amplifying stage comprises first to the 5th, the tenth to the 15 PMOS transistor M0, M1a, M1b, M2a, M2b, M5, M6, M7, M8, M9, M10 and second, third, the five to seven, the 9th, the tenth, the tenth bi-NMOS transistor M11b, M11c, M12b, M12c, M3a, M3c, M4a, M4c composition.Slew Rate strengthens current mirror and comprises: nmos pass transistor M3a ~ M3c, M4a ~ M4c, M11a ~ M11c and M12a ~ M12c.PSRR reinforcing feedback comprises: PMOS transistor M7 ~ M10.
The course of work of the present invention is described below by embodiment:
Choose the second to the 5th PMOS transistor M1a, M1b, M2a and M2b as signal input part, input difference mode signal Vin+ and Vin-respectively, through first tearing differential input stage, Slew Rate strengthens current mirror, eventually pass PSRR booster stage outputs to Vout; So far signal completes the amplification from input to output.The output of amplifier load heavy load electric capacity can test amplifier small-signal AC response and the step response of large-signal, small-signal parameter and the transient parameter of device can be amplified.In addition after SRE, the Slew Rate of signal is enhanced.Result shows that this money operational amplifier reduces building-out capacitor, increases PSRR and Slew Rate, and in the circuit application of low-voltage and low-power dissipation, this is very favourable for this.
Claims (2)
1. one kind is applicable to the high Slew Rate PSRR enhancement mode one-stage amplifier of power management, it is characterized in that, described amplifier by the first to the 15 PMOS transistor M0, M1a, M1b, M2a, M2b, M13a, M13b, M14a, M14b, M5, M6, M7, M8, M9, M10 and first to the tenth bi-NMOS transistor M11a, M11b, M11c, M12a, M12b, M12c, M3a, M3b, M3c, M4a, M4b, M4c totally two ten seven MOS transistor form; Wherein:
The first, the source electrode of the 8th to the 11 PMOS transistor M0, M14a, M14b, M5, M6 meets power supply VDD jointly; The substrate termination power supply VDD of all PMOS transistor M0, M1a, M1b, M2a, M2b, M13a, M13b, M14a, M14b, M5, M6, M7, M8, M9, M10; The Substrate ground GND of first to the tenth bi-NMOS transistor M11a, M11b, M11c, M11d, M12a, M12b, M12c, M12d, M3a, M3b, M3c, M4a, M4b, M4c; The source electrode common ground GND of the 7th to the tenth bi-NMOS transistor M3a, M3b, M3c, M4a, M4b, M4c;
The first, the grid of the 8th, the 9th PMOS transistor M0, M14a, M14b meets the first bias voltage Vb1; The drain electrode of the first PMOS transistor M0 connects the source electrode of the second to the 5th PMOS transistor M1a, M1b, M2a, M2b; The grid of the second to the 3rd PMOS transistor M1a, M1b meets input Vp; The grid of the 4th to the 5th PMOS transistor M2a, M2b meets input Vn;
The drain electrode of the second PMOS transistor M1a, the source electrode of the 6th nmos pass transistor M12c connect the drain electrode of the tenth nmos pass transistor M4a jointly; The drain electrode of the 4th PMOS transistor M2a, the source electrode of the 3rd nmos pass transistor M11c connect the drain electrode of the 7th nmos pass transistor M3a jointly;
The drain electrode of the 3rd PMOS transistor M1b, the grid of the 7th to the 9th nmos pass transistor M3a, M3b, M3c connect the drain electrode of the second nmos pass transistor M11b jointly; The drain electrode of the 5th PMOS transistor M2b, the grid of the tenth to the tenth bi-NMOS transistor M4a, M4b, M4c connect the drain electrode of the 5th nmos pass transistor M12b jointly; The grid of first to the 6th nmos pass transistor M11a, M11b, M11c, M12a, M12b, M12c meets the second bias voltage Vb3 jointly; The source electrode of the second nmos pass transistor M11b connects the drain electrode of the 9th nmos pass transistor M3c; The source electrode of the first nmos pass transistor M11a connects the drain electrode of the 8th nmos pass transistor M3b; The source electrode of the 5th nmos pass transistor M12b connects the drain electrode of the tenth bi-NMOS transistor M4c; The source electrode of the 4th nmos pass transistor M12a connects the drain electrode of the 11 nmos pass transistor M4b;
The drain electrode of the 3rd nmos pass transistor M11c, the drain electrode of the 6th PMOS transistor M13a, the drain electrode of the 14 PMOS transistor M9 connect the grid of the 13 PMOS transistor M8 jointly; The drain electrode of the 6th nmos pass transistor M12c, the drain electrode of the 7th PMOS transistor M13b, the drain electrode of the 15 PMOS transistor M10 connect the grid of the 12 PMOS transistor M7 jointly; The drain electrode of the 8th PMOS transistor M14a, the source electrode of the 6th PMOS transistor M13a connect the drain electrode of the first nmos pass transistor M11a jointly; The drain electrode of the 9th PMOS transistor M14b, the source electrode of the 7th PMOS transistor M13b connect the drain electrode of the 4th nmos pass transistor M12a jointly; Six, the 7th, the 14, the grid common ground two bias voltage Vb2 of the 15 PMOS transistor M13a, M13b, M9, M10; Ten, the grid of the 11 PMOS transistor M5, M6 connects the drain electrode of the 12 PMOS transistor M7 and the source electrode of the 14 PMOS transistor M9 jointly; The drain electrode of the tenth PMOS transistor M5 connects the source electrode of the 12 PMOS transistor M7; The drain electrode of the 11 PMOS transistor M6 connects the source electrode of the 13 PMOS transistor M8; The drain electrode of the 13 PMOS transistor M8, the source electrode of the 15 PMOS transistor M10 meet output end vo ut jointly;
Choose the second to the 5th PMOS transistor M1a, M1b, M2a and M2b is as signal input part, input difference mode signal Vin+ and Vin-respectively, through comprising the second to the 5th PMOS transistor pipe M1a, M1b, M2a, first of M2b tears differential input stage and comprises the second to the 5th PMOS M1a, M1b, M2a, M2b and first is to the tenth bi-NMOS transistor M11a, M11b, M11c, M12a, M12b, M12c, M3a, M3b, M3c, M4a, M4b, the loop collapsing cascade amplifying stage of M4c, by nmos pass transistor M3a ~ M3c, M4a ~ M4c, the Slew Rate that M11a ~ M11c and M12a ~ M12c is formed strengthens current mirror, eventually pass the PSRR reinforcing feedback be made up of PMOS transistor M7 ~ M10 and output to output end vo ut.
2. a kind of high Slew Rate PSRR enhancement mode one-stage amplifier being applicable to power management as claimed in claim 1, is characterized in that, described output loads heavy load electric capacity.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN106774614A (en) * | 2016-12-05 | 2017-05-31 | 电子科技大学 | A kind of low pressure difference linear voltage regulator with super transconductance structure |
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Patent Citations (3)
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| CN1671040A (en) * | 2004-03-16 | 2005-09-21 | 沃福森微电子股份有限公司 | Low noise operational amplifier |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106774614A (en) * | 2016-12-05 | 2017-05-31 | 电子科技大学 | A kind of low pressure difference linear voltage regulator with super transconductance structure |
| CN106774614B (en) * | 2016-12-05 | 2017-11-14 | 电子科技大学 | A kind of low pressure difference linear voltage regulator with super transconductance structure |
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