CN105356856B - The high-gain two-stage calculation amplifier insensitive suitable for technique under nano-scale - Google Patents
The high-gain two-stage calculation amplifier insensitive suitable for technique under nano-scale Download PDFInfo
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- CN105356856B CN105356856B CN201510736725.1A CN201510736725A CN105356856B CN 105356856 B CN105356856 B CN 105356856B CN 201510736725 A CN201510736725 A CN 201510736725A CN 105356856 B CN105356856 B CN 105356856B
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Abstract
The present invention relates to large scale integrated circuits, to provide a kind of high-gain two-stage calculation amplifier insensitive applied to technique under nano-scale.The operation amplifier circuit can be insensitive to technique in amplifier, and has higher gain and stability, lower power consumption.For this reason, the technical scheme adopted by the present invention is that the high-gain two-stage calculation amplifier insensitive suitable for technique under nano-scale, is made of three gain stages, two active feedback loops and a biasing circuit；Two gain stages include transadmittance gain pole gm1, high-gain stage gm2 and the output stage gmL being sequentially connected in series；Two active feedback loops：One includes capacitance Cm1, transadmittance gain grade gma1 and resistance 1/gma1；Another includes capacitance Cm2, resistance Rm, transadmittance gain grade gma2.Present invention is mainly applied to the design and manufacture of high-gain two-stage calculation amplifier.
Description
Technical field
The present invention relates to large scale integrated circuit, low voltage and low power circuits technical field, including nanometer technology, operation amplifier
Device, the technologies application such as high-gain.In particular to it is suitable for the insensitive high-gain two-stage calculation amplification of technique under nano-scale
Device.
Technical background
With the reduction of modern CMOS processes size, the development of low-power consumption mixed signal circuit encounters the bottleneck of size, special
It is not the design of analog module.This is unfavorable for the raising of integrated chip performance, is less useful for the development of low-power consumption trend.Due to two
The miller-compensated amplifier of grade has been widely used in analog module, but in nanometer Digital CMOS circuit, with technique
The arithmetic speed of the reduction of size, transistor improves, and the high amplitude of oscillation and gain improve assertive evidence gain and be but extremely limited.Generally
For using technique insensitive design when, resistance is realized using the transistor for being biased in linear zone, but this is in low-pressure designs
In can be restricted (3 × Vov+2 of supply voltage VDD ＜ × Vth).According to document (Mohammad Taherzadeh-Sani,
Journal of Solid-State Circuits, 2011,46 (3)：660-668) the pseudo cascode- reported
Compensation technologies：The technology had not only increased two stage amplifer gain using body bias technology, but also did not influenced the defeated of amplifier
Go out voltage swing, also do not need additional biasing circuit, to save power consumption.Since the technology has the bias current of circuit
There is very strong robustness, it has already been proven that can be applied in analog-to-digital conversion or the D/A converting circuit of nanometer technology size.
Invention content
In order to overcome the deficiencies of the prior art, a kind of high-gain two-stage fortune insensitive applied to technique under nano-scale is provided
Calculate amplifier.The operation amplifier circuit can be insensitive to technique in amplifier, and has higher gain and stability, more
Low power consumption.For this reason, the technical scheme adopted by the present invention is that the high-gain two-stage fortune insensitive suitable for technique under nano-scale
Amplifier is calculated, is made of three gain stages, two active feedback loops and a biasing circuit；Two gain stages include going here and there successively
Transadmittance gain pole gm1, high-gain stage gm2 and the output stage gmL connect；Two active feedback loops：One include capacitance Cm1, across
Gain stage gma1 and resistance 1/gma1 are led, resistance 1/gma1 and mutual conductance gma1 are realized by PMOS transistor M6a, M6b respectively；Separately
One includes capacitance Cm2, resistance Rm, transadmittance gain grade gma2, and mutual conductance gma2 is realized by PMOS transistor M7a, M7b；Two
Active feedback loop is connected across between gain pole gm1 outputs, output stage gmL outputs.
First gain stage include PMOS transistor M0a, M0b, M1a, M1b, M2a, M2b, M7a, M7b, M8a, M8b and
NMOS transistor M3a, M3b, M4a, M4b, M5a, M5b, M6a, M6b etc.；Transadmittance gain grade gm1 by PMOS transistor M1a, M1b,
M2a, M2b are realized；Second gain stage includes PMOS transistor M9a, M9b and NMOS transistor M10a, M10b etc.；Transadmittance gain
GmL is by PMOS transistor M9a, M9b for grade；Biasing circuit include PMOS transistor M11a, M11b and NMOS transistor M12a,
M12b、M13a、M13b；Two active feedback loops be connected across gain stage gm1 output end and output stage gmL output end it
Between；Two of which gain stage provides DC current gain respectively；Two active feedback loops are respectively provided with source Left half-plane zero, with
The stability of amplifier is improved, and expands its range for driving load capacity；Biasing circuit is pseudo cascode PMOS brilliant
Body pipe M0a, M0b, M1a, M1b, M2a, M2b, M7a, M7b, M8a, M8b, M9a, M9b, M11a, M11b and NMOS transistor
M3a, M3b, M4a, M4b, M5a, M5b, M6a, M6b, M10a, M10b, M12a, M12b, M13a, M13b etc. provide body bias electricity
Pressure.
The amplifier by first to the 14th PMOS transistor M0a, M0b, M1a, M1b, M2a, M2b, M7a, M7b,
M8a, M8b, M9a, M9b, M11a, M11b and first to the 14th NMOS transistor M3a, M3b, M4a, M4b, M5a, M5b,
M6a, M6b, M10a, M10b, M12a, M12b, M13a, M13b totally 28 MOS transistors, four capacitances, that is, compensating electric capacity Cm1,
Cm2, floating gate capacitance Cf and load capacitance CL, a resistance Rm composition；Wherein：
The drain electrode of first PMOS transistor M0a connects the source electrode of the second PMOS transistor M0b；
The drain electrode of third PMOS transistor M1a connects the source electrode of the 4th PMOS transistor M1b；
The drain electrode of 5th PMOS transistor M2a connects the source electrode of the 6th PMOS transistor M2b；
The drain electrode of 7th PMOS transistor M7a connects the source electrode of the 8th PMOS transistor M7b；
The drain electrode of 9th PMOS transistor M8a connects the source electrode of the tenth PMOS transistor M8b；
The drain electrode of 11st PMOS transistor M9a connects the source electrode of the 12nd PMOS transistor M9b；
The drain electrode of 13rd PMOS transistor M11a connects the source electrode of the 14th PMOS transistor M11b；
The source electrode of first NMOS transistor M3a connects the drain electrode of the second NMOS transistor M3b；
The source electrode of third NMOS transistor M4a connects the drain electrode of the 4th NMOS transistor M4b；
The source electrode of 5th NMOS transistor M5a connects the drain electrode of the 6th NMOS transistor M5b；
The source electrode of 7th NMOS transistor M6a connects the drain electrode of the 8th NMOS transistor M6b；
The source electrode of 9th NMOS transistor M10a connects the drain electrode of the tenth NMOS transistor M10b；
The source electrode of 11st NMOS transistor M12a connects the drain electrode of the tenth bi-NMOS transistor M12b；
The source electrode of 13rd NMOS transistor M13a connects the drain electrode of the 14th NMOS transistor M13b；
The first, third, the five, the seven, the nine, the 11st, the 13rd PMOS transistor M0a, M1a, M2a, M7a, M8a,
The substrate of M9a, M11a, the upper end of bias current sources Ibias meet power vd D jointly；The second, the eight, the ten, the 12nd, the tenth
The substrate of four PMOS transistor M0b, M7b, M8b, M9b, M11b meets bias voltage Vbp jointly；
The first, the seven, the nine, the 11st, the source electrode of the 13rd PMOS transistor M0a, M7a, M8a, M9a, M11a is common
Meet power vd D；The second, the source electrode of the 4th, the tenth, the 12nd, the 14th NMOS transistor M3b, M4b, M10b, M12b, M13b
Common ground connection GND；
The first, third, the five, the seven, the nine, the 11st, the 13rd NMOS transistor M3a, M4a, M5a, M6a, M10a,
The substrate of M12a, M13a and the substrate of the four, the 6th PMOS transistors M1b, M2b meet bias voltage Vbn jointly；The second, the 4th,
Six, the eight, the ten, the 12nd, the substrate of the 14th NMOS transistor M3b, M4b, M5b, M6b, M10b, M12b, M13b and
The lower end of 4th capacitance CL is grounded GND jointly；
The first, second, the ten three, the grid of the 14th PMOS transistor M0a, M0b, M11a, M11b connects the 14th jointly
The drain electrode of PMOS transistor M11b and the drain electrode of the 13rd NMOS transistor M13a；The drain electrode of second PMOS transistor M0b connects
Three, the source electrode of the 5th PMOS transistor M1a, M2a；Third, the 4th PMOS transistor M1a, M1b grid connect input terminal jointly
Vn；The grid of five, the 6th PMOS transistors M2a, M2b meets input terminal Vp jointly；
The drain electrode of 4th PMOS transistor M1b, the drain electrode of the first NMOS transistor M3a connect the 6th NMOS transistor jointly
The source electrode of M5b；The drain electrode of 6th PMOS transistor M2b, the drain electrode of third NMOS transistor M4a connect the 8th NMOS transistor jointly
The source electrode of M6b；
First to fourth, the 11st to the 14th NMOS transistor M3a, M3b, M4a, M4b, M12a, M12b, M13a,
The grid of M13b, the left end of second resistance Rm2 meet drain electrode and the current source Ibias of the 11st NMOS transistor M12a jointly
Lower end；The grid of 5th to the 8th NMOS transistor M5a, M5b, M6a, M6b meets the second bias voltage Vb2 jointly；5th NMOS
The drain electrode of transistor M5a, the grid of the 9th to the tenth PMOS transistor M8a, M8b, the drain electrode of the 8th PMOS transistor M7b are common
Connect the lower end of first resistor Rm1；The grid of 7th to the 8th PMOS transistor M7a, M7b, the upper end of the second capacitance Cm2 connect jointly
The upper end of first resistor Rm1；The drain electrode of 7th NMOS transistor M6a, the drain electrode of the tenth PMOS transistor M8b connect the 11st jointly
To the upper end of the grid and third capacitance Cf of the 12nd PMOS transistor M9a, M9b；The drain electrode of 12nd PMOS transistor M9b,
The drain electrode of 9th NMOS transistor M10a, the right end of the first capacitance Cm1, the upper end of the 4th capacitance CL, the second capacitance Cm2 lower end
Output end vo ut is met jointly；The left end of first capacitance Cm1 connects the source electrode of the 8th NMOS transistor M6b；Nine, the tenth NMOS crystal
The grid of pipe M10a, M10b, the lower end of third capacitance Cf connect the right end of second resistance Rm2 jointly.
The technical characterstic and effect of the present invention：
Under the conditions of low-voltage and low-power dissipation nano-scale, which can be insensitive to technique, and with compared with
High gain, stability and lower power consumption.
Description of the drawings：
The topological diagram of Fig. 1 operational amplifiers.
The circuit diagram of Fig. 2 operational amplifiers.
Specific implementation mode
In order to realize under nanometer technology size, two-stage calculation amplifier has stronger robustness, the change for technique
Change it is insensitive, the present invention use pseudo cascode-compensation technologies bias voltage and body bias technology, tying
Carry out the stability that frequency compensation maintains amplifier using two-way active feedback on structure.It is final to realize under nanometer technology size, it puts
Big device is insensitive to technique, and has higher gain and stability.
The present invention proposes a kind of high-gain two-stage calculation amplifier insensitive for technique under nano-scale, described
Amplifier is made of two gain stages, two active feedback loops and a biasing circuit.
The amplifier is made of two gain stages, two active feedback loops and a biasing circuit etc..First gain
Grade include PMOS transistor M0a, M0b, M1a, M1b, M2a, M2b, M7a, M7b, M8a, M8b and NMOS transistor M3a, M3b,
M4a, M4b, M5a, M5b, M6a, M6b etc.；Transadmittance gain grade gm1 is realized by PMOS transistor M1a, M1b, M2a, M2b；Second
Gain stage includes PMOS transistor M9a, M9b and NMOS transistor M10a, M10b etc.；GmL is by PMOS transistor for transadmittance gain grade
M9a, M9b are realized.First active feedback loop include：Capacitance Cm1, mutual conductance gma1 and resistance 1/gma1 and PMOS transistor
M6a, M6b etc.；Resistance 1/gma1 and mutual conductance gma1 are realized by PMOS transistor M6a, M6b etc. respectively.Second feedback control loop
Including：Capacitance Cm2, resistance Rm, transadmittance gain grade gma2 and PMOS transistor M7a, M7b etc.；Mutual conductance gma2 is by PMOS transistor
M7a, M7b etc. are realized.Biasing circuit include PMOS transistor M11a, M11b and NMOS transistor M12a, M12b, M13a,
M13b etc..Two active feedback loops are connected across between the output end of gain stage gm1 and the output end of output stage gmL.Wherein
Two gain stages provide DC current gain respectively；Two active feedback loops are respectively provided with source Left half-plane zero, are put with improving
The stability of big device, and expand its range for driving load capacity；Biasing circuit is pseudo cascode PMOS transistors
M0a, M0b, M1a, M1b, M2a, M2b, M7a, M7b, M8a, M8b, M9a, M9b, M11a, M11b and NMOS transistor M3a,
M3b, M4a, M4b, M5a, M5b, M6a, M6b, M10a, M10b, M12a, M12b, M13a, M13b etc. provide bias voltage.
Specific implementing circuit principle such as attached drawing：The amplifier by first to the 14th PMOS transistor M0a, M0b,
M1a, M1b, M2a, M2b, M7a, M7b, M8a, M8b, M9a, M9b, M11a, M11b and the first to the 14th NMOS transistor
M3a, M3b, M4a, M4b, M5a, M5b, M6a, M6b, M10a, M10b, M12a, M12b, M13a, M13b totally 28 MOS transistors,
Four capacitances, that is, compensating electric capacity Cm1, Cm2, floating gate capacitance Cf and load capacitance CL, a resistance Rm composition；Wherein：
The drain electrode of first PMOS transistor M0a connects the source electrode of the second PMOS transistor M0b；
The drain electrode of third PMOS transistor M1a connects the source electrode of the 4th PMOS transistor M1b；
The drain electrode of 5th PMOS transistor M2a connects the source electrode of the 6th PMOS transistor M2b；
The drain electrode of 7th PMOS transistor M7a connects the source electrode of the 8th PMOS transistor M7b；
The drain electrode of 9th PMOS transistor M8a connects the source electrode of the tenth PMOS transistor M8b；
The drain electrode of 11st PMOS transistor M9a connects the source electrode of the 12nd PMOS transistor M9b；
The drain electrode of 13rd PMOS transistor M11a connects the source electrode of the 14th PMOS transistor M11b；
The source electrode of first NMOS transistor M3a connects the drain electrode of the second NMOS transistor M3b；
The source electrode of third NMOS transistor M4a connects the drain electrode of the 4th NMOS transistor M4b；
The source electrode of 5th NMOS transistor M5a connects the drain electrode of the 6th NMOS transistor M5b；
The source electrode of 7th NMOS transistor M6a connects the drain electrode of the 8th NMOS transistor M6b；
The source electrode of 9th NMOS transistor M10a connects the drain electrode of the tenth NMOS transistor M10b；
The source electrode of 11st NMOS transistor M12a connects the drain electrode of the tenth bi-NMOS transistor M12b；
The source electrode of 13rd NMOS transistor M13a connects the drain electrode of the 14th NMOS transistor M13b；
The first, third, the five, the seven, the nine, the 11st, the 13rd PMOS transistor M0a, M1a, M2a, M7a, M8a,
The substrate of M9a, M11a, the upper end of bias current sources Ibias meet power vd D jointly；The second, the eight, the ten, the 12nd, the tenth
The substrate of four PMOS transistor M0b, M7b, M8b, M9b, M11b meets bias voltage Vbp jointly；
The first, the seven, the nine, the 11st, the source electrode of the 13rd PMOS transistor M0a, M7a, M8a, M9a, M11a is common
Meet power vd D；The second, the source electrode of the 4th, the tenth, the 12nd, the 14th NMOS transistor M3b, M4b, M10b, M12b, M13b
Common ground connection GND；
The first, third, the five, the seven, the nine, the 11st, the 13rd NMOS transistor M3a, M4a, M5a, M6a, M10a,
The substrate of M12a, M13a and the substrate of the four, the 6th PMOS transistors M1b, M2b meet bias voltage Vbn jointly；The second, the 4th,
Six, the eight, the ten, the 12nd, the substrate of the 14th NMOS transistor M3b, M4b, M5b, M6b, M10b, M12b, M13b and
The lower end of 4th capacitance CL is grounded GND jointly；
The first, second, the ten three, the grid of the 14th PMOS transistor M0a, M0b, M11a, M11b connects the 14th jointly
The drain electrode of PMOS transistor M11b and the drain electrode of the 13rd NMOS transistor M13a；The drain electrode of second PMOS transistor M0b connects
Three, the source electrode of the 5th PMOS transistor M1a, M2a；Third, the 4th PMOS transistor M1a, M1b grid connect input terminal jointly
Vn；The grid of five, the 6th PMOS transistors M2a, M2b meets input terminal Vp jointly；
The drain electrode of 4th PMOS transistor M1b, the drain electrode of the first NMOS transistor M3a connect the 6th NMOS transistor jointly
The source electrode of M5b；The drain electrode of 6th PMOS transistor M2b, the drain electrode of third NMOS transistor M4a connect the 8th NMOS transistor jointly
The source electrode of M6b；
First to fourth, the 11st to the 14th NMOS transistor M3a, M3b, M4a, M4b, M12a, M12b, M13a,
The grid of M13b, the left end of second resistance Rm2 are connect jointly under the drain electrode and current source Ibias of the 11st NMOS transistor M12a
End；The grid of 5th to the 8th NMOS transistor M5a, M5b, M6a, M6b meets the second bias voltage Vb2 jointly；5th NMOS is brilliant
The drain electrode of body pipe M5a, the drain electrode of the grid, the 8th PMOS transistor M7b of the 9th to the tenth PMOS transistor M8a, M8b connect jointly
The lower end of first resistor Rm1；The grid of 7th to the 8th PMOS transistor M7a, M7b, the upper end of the second capacitance Cm2 connect jointly
The upper end of one resistance Rm1；The drain electrode of 7th NMOS transistor M6a, the drain electrode of the tenth PMOS transistor M8b connect jointly the 11st to
The upper end of the grid and third capacitance Cf of 12nd PMOS transistor M9a, M9b；The drain electrode of 12nd PMOS transistor M9b,
The drain electrode of nine NMOS transistor M10a, the right end of the first capacitance Cm1, the upper end of the 4th capacitance CL, the lower end of the second capacitance Cm2 are total
It is same to meet output end vo ut；The left end of first capacitance Cm1 connects the source electrode of the 8th NMOS transistor M6b；Nine, the tenth NMOS transistors
The grid of M10a, M10b, the lower end of third capacitance Cf connect the right end of second resistance Rm2 jointly.
Third is chosen to the grid of the 6th PMOS transistor M1a, M1b, M2a, M2b as input terminal Vn and Vp, difference is defeated
Enter difference mode signal.Output end vo ut is arrived after folded common source and common grid is output to the amplification of the second gain stage.Synchronous signal is from output
End feeds back to the output end of the first gain stage by two-way active feedback path respectively.Amplifier output end loading resistor and
Load capacitance can be responded with the small signal communication of test amplifier and the step response of big signal.The result shows that this money two-stage calculation
Amplifier can be insensitive to technique under the conditions of high-gain, and has stability and lower power consumption.
Claims (2)
1. a kind of high-gain two-stage calculation amplifier insensitive suitable for technique under nano-scale, characterized in that increased by two
Beneficial grade, two active feedback loops and a biasing circuit composition；Two gain stages include the transadmittance gain grade gm1 being sequentially connected in series
With output stage gmL；Two active feedback loops：One includes capacitance Cm1, transadmittance gain grade gma1 and resistance 1/gma1, resistance
1/gma1 and mutual conductance gma1 are realized by PMOS transistor M6a, M6b respectively；Another includes capacitance Cm2, resistance Rm, mutual conductance increasing
Beneficial grade gma2, mutual conductance gma2 are realized by PMOS transistor M7a, M7b；Two active feedback loops are connected across gain stage gm1
Between output, output stage gmL outputs；First gain stage include PMOS transistor M0a, M0b, M1a, M1b, M2a, M2b, M8a,
M8b and NMOS transistor M3a, M3b, M4a, M4b, M5a, M5b；Transadmittance gain grade gm1 by PMOS transistor M1a, M1b, M2a,
M2b is realized；Second gain stage includes PMOS transistor M9a, M9b and NMOS transistor M10a, M10b；Transadmittance gain grade gmL
It is made of PMOS transistor M9a, M9b；Biasing circuit include PMOS transistor M11a, M11b and NMOS transistor M12a, M12b,
M13a、M13b；Two active feedback loops are connected across between the output end of gain stage gm1 and the output end of output stage gmL；Its
In two gain stages DC current gain is provided respectively；Two active feedback loops are respectively provided with source Left half-plane zero, to improve
The stability of amplifier, and expand its range for driving load capacity；Biasing circuit is pseudo cascode PMOS transistors
M0a, M0b, M1a, M1b, M2a, M2b, M7a, M7b, M8a, M8b, M9a, M9b, M11a, M11b and NMOS transistor M3a,
M3b, M4a, M4b, M5a, M5b, M6a, M6b, M10a, M10b, M12a, M12b, M13a, M13b provide bias voltage.
2. the high-gain two-stage calculation amplifier insensitive suitable for technique under nano-scale as described in claim 1, special
Sign is, the amplifier by first to the 14th PMOS transistor M0a, M0b, M1a, M1b, M2a, M2b, M7a, M7b, M8a,
M8b, M9a, M9b, M11a, M11b and first to the 14th NMOS transistor M3a, M3b, M4a, M4b, M5a, M5b, M6a,
Totally 28 MOS transistors, four capacitances, that is, compensating electric capacity Cm1, Cm2 float by M6b, M10a, M10b, M12a, M12b, M13a, M13b
Grid capacitance Cf and load capacitance CL are set, two resistance Rm1, Rm2 are constituted；
Wherein：
The drain electrode of first PMOS transistor M0a connects the source electrode of the second PMOS transistor M0b；
The drain electrode of third PMOS transistor M1a connects the source electrode of the 4th PMOS transistor M1b；
The drain electrode of 5th PMOS transistor M2a connects the source electrode of the 6th PMOS transistor M2b；
The drain electrode of 7th PMOS transistor M7a connects the source electrode of the 8th PMOS transistor M7b；
The drain electrode of 9th PMOS transistor M8a connects the source electrode of the tenth PMOS transistor M8b；
The drain electrode of 11st PMOS transistor M9a connects the source electrode of the 12nd PMOS transistor M9b；
The drain electrode of 13rd PMOS transistor M11a connects the source electrode of the 14th PMOS transistor M11b；
The source electrode of first NMOS transistor M3a connects the drain electrode of the second NMOS transistor M3b；
The source electrode of third NMOS transistor M4a connects the drain electrode of the 4th NMOS transistor M4b；
The source electrode of 5th NMOS transistor M5a connects the drain electrode of the 6th NMOS transistor M5b；
The source electrode of 7th NMOS transistor M6a connects the drain electrode of the 8th NMOS transistor M6b；
The source electrode of 9th NMOS transistor M10a connects the drain electrode of the tenth NMOS transistor M10b；
The source electrode of 11st NMOS transistor M12a connects the drain electrode of the tenth bi-NMOS transistor M12b；
The source electrode of 13rd NMOS transistor M13a connects the drain electrode of the 14th NMOS transistor M13b；
The first, third, the five, the seven, the nine, the 11st, the 13rd PMOS transistor M0a, M1a, M2a, M7a, M8a, M9a,
The substrate of M11a, the upper end of bias current sources Ibias meet power vd D jointly；The second, the eight, the ten, the 12nd, the 14th
The substrate of PMOS transistor M0b, M7b, M8b, M9b, M11b meet bias voltage Vbp jointly；
The first, the seven, the nine, the 11st, the source electrode of the 13rd PMOS transistor M0a, M7a, M8a, M9a, M11a connects electricity jointly
Source VDD；The second, the four, the ten, the 12nd, the source electrode of the 14th NMOS transistor M3b, M4b, M10b, M12b, M13b is common
It is grounded GND；
The first, third, the five, the seven, the nine, the 11st, the 13rd NMOS transistor M3a, M4a, M5a, M6a, M10a,
The substrate of M12a, M13a and the substrate of the four, the 6th PMOS transistors M1b, M2b meet bias voltage Vbn jointly；The second, the 4th,
Six, the eight, the ten, the 12nd, the substrate of the 14th NMOS transistor M3b, M4b, M5b, M6b, M10b, M12b, M13b and
The lower end of 4th capacitance CL is grounded GND jointly；
The first, second, the ten three, the grid of the 14th PMOS transistor M0a, M0b, M11a, M11b meets the 14th PMOS jointly
The drain electrode of transistor M11b and the drain electrode of the 13rd NMOS transistor M13a；The drain electrode of second PMOS transistor M0b connects third,
The source electrode of five PMOS transistors M1a, M2a；Third, the 4th PMOS transistor M1a, M1b grid meet input terminal Vn jointly；The
Five, the grid of the 6th PMOS transistor M2a, M2b meets input terminal Vp jointly；
The drain electrode of 4th PMOS transistor M1b, the drain electrode of the first NMOS transistor M3a connect the 6th NMOS transistor M5b's jointly
Source electrode；The drain electrode of 6th PMOS transistor M2b, the drain electrode of third NMOS transistor M4a connect the 8th NMOS transistor M6b's jointly
Source electrode；
First to fourth, the 11st to the 14th NMOS transistor M3a, M3b, M4a, M4b, M12a, M12b, M13a, M13b
Grid, second resistance Rm2 left end connect jointly the 11st NMOS transistor M12a drain electrode and current source Ibias lower end；The
The grid of five to the 8th NMOS transistor M5a, M5b, M6a, M6b meets the second bias voltage Vb2 jointly；5th NMOS transistor
The drain electrode of M5a, the drain electrode of grid, the 8th PMOS transistor M7b of the 9th to the tenth PMOS transistor M8a, M8b connect first jointly
The lower end of resistance Rm1；The grid of 7th to the 8th PMOS transistor M7a, M7b, the upper end of the second capacitance Cm2 connect the first electricity jointly
Hinder the upper end of Rm1；The drain electrode of 7th NMOS transistor M6a, the drain electrode of the tenth PMOS transistor M8b connect the 11st to the tenth jointly
The upper end of the grid and third capacitance Cf of two PMOS transistors M9a, M9b；The drain electrode of 12nd PMOS transistor M9b, the 9th
The drain electrode of NMOS transistor M10a, the right end of the first capacitance Cm1, the upper end of the 4th capacitance CL, the lower end of the second capacitance Cm2 are common
Meet output end vo ut；The left end of first capacitance Cm1 connects the source electrode of the 8th NMOS transistor M6b；Nine, the tenth NMOS transistors
The grid of M10a, M10b, the lower end of third capacitance Cf connect the right end of second resistance Rm2 jointly.
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| US9893689B2 (en) * | 2016-06-24 | 2018-02-13 | Stmicroelectronics S.R.L. | System and method for a multistage operational amplifier |
| CN107666312B (en) * | 2017-11-09 | 2023-09-01 | 苏州大学 | CMOS transconductance unit circuit with wide input voltage range and high linearity |
Citations (4)
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| CN101729027A (en) * | 2009-10-30 | 2010-06-09 | 华南理工大学 | High gain amplifier circuit |
| CN102075151A (en) * | 2010-12-22 | 2011-05-25 | 清华大学 | Complementary circulation folding gain bootstrapping operational amplifier circuit with preamplifier |
| CN102394582A (en) * | 2011-10-14 | 2012-03-28 | 西安电子科技大学 | Substrate drive low voltage operational amplifier circuit |
| CN104656733A (en) * | 2015-02-12 | 2015-05-27 | 天津大学 | LDO (low dropout regulator) capable of outputting ultra-low quiescent current in self-adaptation way |
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2015
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|---|---|---|---|---|
| CN101729027A (en) * | 2009-10-30 | 2010-06-09 | 华南理工大学 | High gain amplifier circuit |
| CN102075151A (en) * | 2010-12-22 | 2011-05-25 | 清华大学 | Complementary circulation folding gain bootstrapping operational amplifier circuit with preamplifier |
| CN102394582A (en) * | 2011-10-14 | 2012-03-28 | 西安电子科技大学 | Substrate drive low voltage operational amplifier circuit |
| CN104656733A (en) * | 2015-02-12 | 2015-05-27 | 天津大学 | LDO (low dropout regulator) capable of outputting ultra-low quiescent current in self-adaptation way |
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| "A 1-V Process-Insensitive Current-Scalable Two-Stage Opamp With Enhanced DC Gain and Settling Behavior in 65-nm Digital CMOS";Mohammad等;《IEEE JOURNAL OF SOLID-STATE CIRCUITS》;20110331;第46卷(第3期);第660-668页 * |
| "Cross Feedforward Cascode Compensation for Low-Power Three-Stage Amplifier With Large Capacitive Load";Sau Siong Chong等;《IEEE JOURNAL OF SOLID-STATE CIRCUITS》;20120930;第47卷(第9期);第2227页摘要、2228页右栏第3段-2232页左栏第1段、附图2-5 * |
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