CN104656733A - LDO (low dropout regulator) capable of outputting ultra-low quiescent current in self-adaptation way - Google Patents
LDO (low dropout regulator) capable of outputting ultra-low quiescent current in self-adaptation way Download PDFInfo
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Abstract
The invention relates to a large-scale integrated circuit, and provides a LDO (low dropout regulator) capable of outputting ultra-low quiescent current in a self-adaptation way. An LDO circuit can maintain high stability under the wide-range load condition, and has the characteristics of ultra-low quiescent current and fast response particularly under the load-free condition. Therefore the LDO has the technical scheme that the LDO capable of outputting ultra-low quiescent current in the self-adaptation way consists of two gain amplification stages, two CMOS (complementary metal oxide semiconductor) power transistor loops, a feedback loop, an overshoot reducing loop and a frequency compensation loop, wherein input signals are input by an inverted input end of the first gain amplification stage and are then output sequentially through the second gain amplification stage and the first CMOS power transistor loop, and the output of the first gain amplification stage is directly output to the output end of the first CMOS power transistor loop through the second CMOS power transistor loop. The large-scale integrated circuit is mainly applied to the design manufacturing of large-scale integrated circuits.
Description
Technical field
The present invention relates to large scale integrated circuit, low voltage and low power circuits, low pressure difference linear voltage regulator (LDO).Specifically, the low pressure difference linear voltage regulator that self-adaptation exports ultra low quiescent current is related to.
Background technology
The Power Management Unit of Modern High-Speed development needs many voltage modulators to power to each functional module.For the module of high-performance, highly sensitive digital-to-analogue or mixed signal, low pressure difference linear voltage regulator (LDO) is ideal selection.But in the load capacitance situation driving hundreds of pf, it is very very difficult that LDO can keep stable.The research of OCL output capacitance-less LDO (OCL-LDO) is very popular direction because it can reduce hundreds of I/O pad on chip line between stray capacitance on the impact of chip internal.
In addition for this kind of portable unit of battery of mobile phone, very crucial during low quiescent power supply current, because it can extend the life of a cell.OCL output capacitance-less LDO can carry out compromise to performances such as the loop stability of the quiescent dissipation of battery and LDO and transient responses and consider.
Summary of the invention
For overcoming the deficiencies in the prior art, a kind of self-adaptation is provided to export the LDO of ultra low quiescent current.This LDO circuit can keep highly stable under the loading condition of wide region, especially under immunization with gD DNA vaccine, has the feature of ultralow quiescent current and response fast.The technical scheme that the present invention takes is: self-adaptation exports the low pressure difference linear voltage regulator of ultra low quiescent current, is made up of two gain amplification stage, two CMOS power crystal tube loops, backfeed loop, reduction overshoot loop and frequency compensation loops.Input signal exports through the second amplifier stage, a CMOS power crystal tube loop after being inputted by the inverting input of the first gain amplification stage successively; The output of the first gain amplification stage also directly outputs to a CMOS power transistor loop output by the 2nd CMOS power crystal tube loop; Backfeed loop is connected between the in-phase input end of the first gain amplification stage, a CMOS power transistor loop output; Frequency compensation loop is connected between the output terminal of the first gain amplification stage, a CMOS power transistor loop output; Reduce overshoot loop and be connected to a CMOS power transistor loop output.
Described LDO concrete structure is: by the first to the 14 PMOS transistor M10, M11, M12, M15, M16, M101, M21, M22, M131, M23, M26, M27, MP1, MP2 and first is to the 16 nmos pass transistor M13, M14, M132, M133, M17, M18, M171, M181, M19, M20, M24, M25, M28, M31, M321, M322 is totally 30 MOS transistor, four electric capacity and building-out capacitor Ca, Cm, Cz, CL and five resistance and resistance R1, R2, Rm, Rz, RL is formed jointly, wherein:
The source electrode of the first to the 14 PMOS transistor M10, M11, M12, M15, M16, M101, M21, M22, M23, M26, M27, MP1, MP2 meets power supply VDD jointly; Except the second to the 3rd PMOS transistor M11, M12, the substrate termination power supply VDD of the first, the 4th to the 14 PMOS transistor M10, M15, M16, M101, M21, M22, M23, M26, M27, MP1, MP2; First to the 8th, the 11 to the 14, the source electrode common ground GND of the 16 nmos pass transistor M13, M14, M132, M133, M17, M18, M171, M181, M24, M25, M28, M31, M322; The substrate terminal ground connection GND of first to the 16 nmos pass transistor M13, M14, M132, M133, M17, M18, M171, M181, M19, M20, M24, M25, M28, M31, M321, M322;
The grid of the first PMOS transistor M10 meets the first bias voltage Vb1 jointly, drain electrode connects the second to the 3rd PMOS transistor M11, the source electrode of M12 and the drain electrode of substrate and the 4th PMOS transistor M15; The grid of the 6th PMOS transistor M10, M101 meets the first bias voltage Vb1 jointly; The grid of the first to the second PMOS transistor M11, M12 meets input common mode voltage Vcm and reference data voltage Vref respectively and holds; First PMOS transistor M11, first, the drain electrode of the 5th nmos pass transistor M13, M17, the grid of the 7th nmos pass transistor M171 connect the source electrode of the 9th nmos pass transistor M19 jointly; The left end of the drain electrode of the second PMOS transistor M12, the second nmos pass transistor M14, the 6th nmos pass transistor M18, the grid of the 8th nmos pass transistor M181, the first electric capacity Ca connects the source electrode of the tenth nmos pass transistor M20 jointly;
The drain electrode of the 7th nmos pass transistor M171, the grid of the 9th nmos pass transistor M19 connect the lower end of the first resistance R1 jointly; The drain electrode of the 8th nmos pass transistor M181, the grid of the tenth nmos pass transistor M20 connect the lower end of the second resistance R2 jointly; The upper end of the first to the second resistance R1, R2 connects the drain electrode of the 6th PMOS transistor M101 jointly; The grid of the 7th to the 8th PMOS transistor M21, M22, the drain electrode of the 7th PMOS transistor M21 connect the drain electrode of the tenth nmos pass transistor M19 jointly; The grid of the 9th to the tenth PMOS transistor M131, M23, the 13 PMOS transistor MP1 connects the drain electrode of the tenth nmos pass transistor M20, the 8th PMOS transistor M22 jointly; The grid of first to fourth nmos pass transistor M13, M14, M132, M133 connects the drain electrode of the 9th PMOS transistor M131, the 4th nmos pass transistor M132 jointly; 5th to the 6th, the grid of the 13 nmos pass transistor M17, M18, M28, the left end of the 3rd resistance Rm meet the second bias voltage Vb2 jointly;
The grid of the 11 to the tenth bi-NMOS transistor M24, M25 connects the drain electrode of the 11 nmos pass transistor M24, the tenth PMOS transistor M23 jointly; The drain electrode of the tenth bi-NMOS transistor M25, the 11 PMOS transistor M26, the upper end of the second electric capacity Cm connect the grid of the 14 PMOS transistor MP2 jointly; The grid of the 11 to the 12 PMOS transistor M26, M27 connects the drain electrode of the 12 PMOS transistor M27, the 13 nmos pass transistor M28 jointly; The drain electrode of the 13 PMOS transistor MP1, the upper end of the 4th resistance Rz, the drain electrode of the 14 nmos pass transistor M31, the upper end of load capacitance CL, the upper end of pull-up resistor RL meet output terminal VOUT jointly; The lower end of the upper end ground connection four resistance Rz of the 3rd electric capacity Cz, lower end ground connection; The grid of the 14 nmos pass transistor M31, the lower end of the second electric capacity Cm connect the right-hand member of the 3rd resistance Rm jointly; The grid of the 15 nmos pass transistor M321 and drain electrode connect the drain electrode of the 14 PMOS transistor MP2 jointly; The source electrode of the grid of the 16 nmos pass transistor M322 and drain electrode, the 15 nmos pass transistor M321 meets common mode feedback voltage Vcm jointly.
Compared with the prior art, technical characterstic of the present invention and effect:
Under low-voltage and low-power dissipation (μ W) condition, the LDO of this ultra low quiescent current can drive the load capacitance of wide region (hundreds of pF), has low quiescent current and response speed faster simultaneously.
Accompanying drawing explanation
The topological diagram of the LDO of Fig. 1 ultra low quiescent current
The embodiment schematic diagram of the LDO of Fig. 2 ultra low quiescent current
Embodiment
In recent years about the research of OCL-LDO mostly have low quiescent current direction and quick responder to.The present invention can propose a ultra low quiescent current, fast response and need the OCL-LDO of very little load current.This LDO adopts adaptive power transistor technology.In time driving larger load current, this OCL-LDO can realize the conversion from two-layer configuration to tertiary structure.It can also keep highly stable under the loading condition of wide region in addition, especially under immunization with gD DNA vaccine, has ultralow quiescent current.
The present invention proposes the LDO that a kind of self-adaptation exports ultra low quiescent current, described LDO is made up of two gain amplification stage, two CMOS power crystal tube loops, backfeed loop, reduction overshoot loop and frequency compensation loops.Two gain amplification stage are respectively: transadmittance gain input stage Av1, the second high-gain stage Av2.Two CMOS power crystal tube loops are respectively: transadmittance gain level MP1 and transadmittance gain level MP2.
Concrete implementing circuit schematic diagram is as follows:
Two gain amplification stage are that the first gain amplification stage (comprises the the first to the second, the 6th, the 7th to the 8th PMOS transistor M11, M12, M101, M21 and M22 respectively, 5th to the tenth nmos pass transistor M17, M18, M171, M181, M19 and M20, the first to the second resistance R1, R2.); Second gain amplification stage (comprises the tenth to the 12 PMOS transistor M23, M26 and M27, the tenth to the 13 nmos pass transistor M24, M25 and M28.)。Two CMOS power crystal tube loops are respectively: a CMOS power crystal tube loop (comprising the 13 PMOS transistor MP1); 2nd CMOS power crystal tube loop (comprising the 14 PMOS transistor MP2).Backfeed loop comprises: the 15 to the 16 nmos pass transistor M321, M322, the second PMOS transistor M12.Frequency compensation loop comprises: the tenth nmos pass transistor M20, the first, the 3rd electric capacity Ca, Cz and the 4th resistance Rz.Reduce overshoot loop to comprise: the 14 nmos pass transistor M31, the second electric capacity Cm and the 3rd resistance Rm.
Described LDO is by the first to the 14 PMOS transistor M10, M11, M12, M15, M16, M101, M21, M22, M131, M23, M26, M27, MP1, MP2 and first is to the 16 nmos pass transistor M13, M14, M132, M133, M17, M18, M171, M181, M19, M20, M24, M25, M28, M31, M321, M322 is totally 30 MOS transistor, four electric capacity and building-out capacitor Ca, Cm, Cz, CL and five resistance and resistance R1, R2, Rm, Rz, RL is formed jointly, wherein:
The source electrode of the first to the 14 PMOS transistor M10, M11, M12, M15, M16, M101, M21, M22, M23, M26, M27, MP1, MP2 meets power supply VDD jointly; Except the second to the 3rd PMOS transistor M11, M12, the substrate termination power supply VDD of the first, the 4th to the 14 PMOS transistor M10, M15, M16, M101, M21, M22, M23, M26, M27, MP1, MP2; First to the 8th, the 11 to the 14, the source electrode common ground GND of the 16 nmos pass transistor M13, M14, M132, M133, M17, M18, M171, M181, M24, M25, M28, M31, M322; The substrate terminal ground connection GND of first to the 16 nmos pass transistor M13, M14, M132, M133, M17, M18, M171, M181, M19, M20, M24, M25, M28, M31, M321, M322.
The grid of the first PMOS transistor M10 meets the first bias voltage Vb1 jointly, drain electrode connects the second to the 3rd PMOS transistor M11, the source electrode of M12 and the drain electrode of substrate and the 4th PMOS transistor M15; The grid of the 6th PMOS transistor M10, M101 meets the first bias voltage Vb1 jointly; The grid of the first to the second PMOS transistor M11, M12 meets input common mode voltage Vcm and reference data voltage Vref respectively and holds; First PMOS transistor M11, first, the drain electrode of the 5th nmos pass transistor M13, M17, the grid of the 7th nmos pass transistor M171 connect the source electrode of the 9th nmos pass transistor M19 jointly; The left end of the drain electrode of the second PMOS transistor M12, the second nmos pass transistor M14, the 6th nmos pass transistor M18, the grid of the 8th nmos pass transistor M181, the first electric capacity Ca connects the source electrode of the tenth nmos pass transistor M20 jointly.
The drain electrode of the 7th nmos pass transistor M171, the grid of the 9th nmos pass transistor M19 connect the lower end of the first resistance R1 jointly; The drain electrode of the 8th nmos pass transistor M181, the grid of the tenth nmos pass transistor M20 connect the lower end of the second resistance R2 jointly; The upper end of the first to the second resistance R1, R2 connects the drain electrode of the 6th PMOS transistor M101 jointly; The grid of the 7th to the 8th PMOS transistor M21, M22, the drain electrode of the 7th PMOS transistor M21 connect the drain electrode of the tenth nmos pass transistor M19 jointly; The grid of the 9th to the tenth PMOS transistor M131, M23, the 13 PMOS transistor MP1 connects the drain electrode of the tenth nmos pass transistor M20, the 8th PMOS transistor M22 jointly; The grid of first to fourth nmos pass transistor M13, M14, M132, M133 connects the drain electrode of the 9th PMOS transistor M131, the 4th nmos pass transistor M132 jointly; 5th to the 6th, the grid of the 13 nmos pass transistor M17, M18, M28, the left end of the 3rd resistance Rm meet the second bias voltage Vb2 jointly.
The grid of the 11 to the tenth bi-NMOS transistor M24, M25 connects the drain electrode of the 11 nmos pass transistor M24, the tenth PMOS transistor M23 jointly; The drain electrode of the tenth bi-NMOS transistor M25, the 11 PMOS transistor M26, the upper end of the second electric capacity Cm connect the grid of the 14 PMOS transistor MP2 jointly; The grid of the 11 to the 12 PMOS transistor M26, M27 connects the drain electrode of the 12 PMOS transistor M27, the 13 nmos pass transistor M28 jointly; The drain electrode of the 13 PMOS transistor MP1, the upper end of the 4th resistance Rz, the drain electrode of the 14 nmos pass transistor M31, the upper end of load capacitance CL, the upper end of pull-up resistor RL meet output terminal VOUT jointly; The lower end of the upper end ground connection four resistance Rz of the 3rd electric capacity Cz, lower end ground connection; The grid of the 14 nmos pass transistor M31, the lower end of the second electric capacity Cm connect the right-hand member of the 3rd resistance Rm jointly; The grid of the 15 nmos pass transistor M321 and drain electrode connect the drain electrode of the 14 PMOS transistor MP2 jointly; The source electrode of the grid of the 16 nmos pass transistor M322 and drain electrode, the 15 nmos pass transistor M321 meets input common mode voltage Vcm jointly.
Choose the 3rd PMOS transistor M12 as reference voltage input, the second PMOS transistor M11 as common-mode feedback input end.Then signal is through the first dynamic bias input stage, reduces overshoot level to the second adaptive gain level, the 3rd power transistor amplifier stage, the 4th; Synchronous signal arrives output terminal through two-way in addition: a road is frequency compensation level, and a road is feedback stage; So far signal completes feedback ratio in loop comparatively and amplify.The small-signal AC response of LDO and the step response of large-signal can be tested at the output terminal loading resistor of LDO and heavy load electric capacity.Result shows that the LDO of this money ultra low quiescent current can drive heavy load electric capacity (tens pF), has high linearity and response speed faster simultaneously.
Claims (2)
1. self-adaptation exports a low pressure difference linear voltage regulator for ultra low quiescent current, it is characterized in that, is made up of two gain amplification stage, two CMOS power crystal tube loops, backfeed loop, reduction overshoot loop and frequency compensation loops; Input signal exports through the second amplifier stage, a CMOS power crystal tube loop after being inputted by the inverting input of the first gain amplification stage successively; The output of the first gain amplification stage also directly outputs to a CMOS power transistor loop output by the 2nd CMOS power crystal tube loop; Backfeed loop is connected between the in-phase input end of the first gain amplification stage, a CMOS power transistor loop output; Frequency compensation loop is connected between the output terminal of the first gain amplification stage, a CMOS power transistor loop output; Reduce overshoot loop and be connected to a CMOS power transistor loop output.
2. self-adaptation as claimed in claim 1 exports the low pressure difference linear voltage regulator of ultra low quiescent current, it is characterized in that, described LDO concrete structure is: by the first to the 14 PMOS transistor M10, M11, M12, M15, M16, M101, M21, M22, M131, M23, M26, M27, MP1, MP2 and first is to the 16 nmos pass transistor M13, M14, M132, M133, M17, M18, M171, M181, M19, M20, M24, M25, M28, M31, M321, M322 is totally 30 MOS transistor, four electric capacity and building-out capacitor Ca, Cm, Cz, CL and five resistance and resistance R1, R2, Rm, Rz, RL is formed jointly, wherein:
The source electrode of the first to the 14 PMOS transistor M10, M11, M12, M15, M16, M101, M21, M22, M23, M26, M27, MP1, MP2 meets power supply VDD jointly; Except the second to the 3rd PMOS transistor M11, M12, the substrate termination power supply VDD of the first, the 4th to the 14 PMOS transistor M10, M15, M16, M101, M21, M22, M23, M26, M27, MP1, MP2; First to the 8th, the 11 to the 14, the source electrode common ground GND of the 16 nmos pass transistor M13, M14, M132, M133, M17, M18, M171, M181, M24, M25, M28, M31, M322; The substrate terminal ground connection GND of first to the 16 nmos pass transistor M13, M14, M132, M133, M17, M18, M171, M181, M19, M20, M24, M25, M28, M31, M321, M322;
The grid of the first PMOS transistor M10 meets the first bias voltage Vb1 jointly, drain electrode connects the second to the 3rd PMOS transistor M11, the source electrode of M12 and the drain electrode of substrate and the 4th PMOS transistor M15; The grid of the 6th PMOS transistor M10, M101 meets the first bias voltage Vb1 jointly; The grid of the first to the second PMOS transistor M11, M12 meets input common mode voltage Vcm and reference data voltage Vref respectively and holds; First PMOS transistor M11, first, the drain electrode of the 5th nmos pass transistor M13, M17, the grid of the 7th nmos pass transistor M171 connect the source electrode of the 9th nmos pass transistor M19 jointly; The left end of the drain electrode of the second PMOS transistor M12, the second nmos pass transistor M14, the 6th nmos pass transistor M18, the grid of the 8th nmos pass transistor M181, the first electric capacity Ca connects the source electrode of the tenth nmos pass transistor M20 jointly;
The drain electrode of the 7th nmos pass transistor M171, the grid of the 9th nmos pass transistor M19 connect the lower end of the first resistance R1 jointly; The drain electrode of the 8th nmos pass transistor M181, the grid of the tenth nmos pass transistor M20 connect the lower end of the second resistance R2 jointly; The upper end of the first to the second resistance R1, R2 connects the drain electrode of the 6th PMOS transistor M101 jointly; The grid of the 7th to the 8th PMOS transistor M21, M22, the drain electrode of the 7th PMOS transistor M21 connect the drain electrode of the tenth nmos pass transistor M19 jointly; The grid of the 9th to the tenth PMOS transistor M131, M23, the 13 PMOS transistor MP1 connects the drain electrode of the tenth nmos pass transistor M20, the 8th PMOS transistor M22 jointly; The grid of first to fourth nmos pass transistor M13, M14, M132, M133 connects the drain electrode of the 9th PMOS transistor M131, the 4th nmos pass transistor M132 jointly; 5th to the 6th, the grid of the 13 nmos pass transistor M17, M18, M28, the left end of the 3rd resistance Rm meet the second bias voltage Vb2 jointly;
The grid of the 11 to the tenth bi-NMOS transistor M24, M25 connects the drain electrode of the 11 nmos pass transistor M24, the tenth PMOS transistor M23 jointly; The drain electrode of the tenth bi-NMOS transistor M25, the 11 PMOS transistor M26, the upper end of the second electric capacity Cm connect the grid of the 14 PMOS transistor MP2 jointly; The grid of the 11 to the 12 PMOS transistor M26, M27 connects the drain electrode of the 12 PMOS transistor M27, the 13 nmos pass transistor M28 jointly; The drain electrode of the 13 PMOS transistor MP1, the upper end of the 4th resistance Rz, the drain electrode of the 14 nmos pass transistor M31, the upper end of load capacitance CL, the upper end of pull-up resistor RL meet output terminal VOUT jointly; The lower end of the upper end ground connection four resistance Rz of the 3rd electric capacity Cz, lower end ground connection; The grid of the 14 nmos pass transistor M31, the lower end of the second electric capacity Cm connect the right-hand member of the 3rd resistance Rm jointly; The grid of the 15 nmos pass transistor M321 and drain electrode connect the drain electrode of the 14 PMOS transistor MP2 jointly; The source electrode of the grid of the 16 nmos pass transistor M322 and drain electrode, the 15 nmos pass transistor M321 meets common mode feedback voltage Vcm jointly.
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
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| CN105425888A (en) * | 2015-12-29 | 2016-03-23 | 天津大学 | Low-output-current LDO (low dropout regulator) circuit applicable to power management and having Q-value adjusting function |
| CN105468082A (en) * | 2015-12-29 | 2016-04-06 | 天津大学 | Low-quiescent-current and large-load-driving LDO circuit suitable for power supply management |
| CN105652946A (en) * | 2016-03-04 | 2016-06-08 | 广东顺德中山大学卡内基梅隆大学国际联合研究院 | Adaptive-bias low-load-regulation low dropout linear voltage stabilizer |
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Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6710583B2 (en) * | 2001-09-28 | 2004-03-23 | Catalyst Semiconductor, Inc. | Low dropout voltage regulator with non-miller frequency compensation |
| US6806690B2 (en) * | 2001-12-18 | 2004-10-19 | Texas Instruments Incorporated | Ultra-low quiescent current low dropout (LDO) voltage regulator with dynamic bias and bandwidth |
| CN1848018A (en) * | 2005-04-15 | 2006-10-18 | 矽创电子股份有限公司 | Fast restoring low voltage drop linear voltage stabilizer |
| CN101369161A (en) * | 2008-10-14 | 2009-02-18 | 复旦大学 | Low-voltage difference linear voltage stabilizer without off-chip compensation capacitor |
| CN101943925A (en) * | 2009-07-06 | 2011-01-12 | 北京中电华大电子设计有限责任公司 | Discharge circuit for voltage regulators |
| CN102707754A (en) * | 2012-05-30 | 2012-10-03 | 昆山锐芯微电子有限公司 | Low dropout regulator |
| CN102915061A (en) * | 2011-08-05 | 2013-02-06 | 深圳市汇春科技有限公司 | Low-voltage stabilizer for ultra-low static current |
| CN104063003A (en) * | 2014-06-27 | 2014-09-24 | 合肥工业大学 | Low-power dissipation off-chip-capacitor-free LDO (Low Dropout Regulator) integrating slew rate enhancing circuit |
-
2015
- 2015-02-12 CN CN201510076036.2A patent/CN104656733B/en not_active Expired - Fee Related
Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6710583B2 (en) * | 2001-09-28 | 2004-03-23 | Catalyst Semiconductor, Inc. | Low dropout voltage regulator with non-miller frequency compensation |
| US6806690B2 (en) * | 2001-12-18 | 2004-10-19 | Texas Instruments Incorporated | Ultra-low quiescent current low dropout (LDO) voltage regulator with dynamic bias and bandwidth |
| CN1848018A (en) * | 2005-04-15 | 2006-10-18 | 矽创电子股份有限公司 | Fast restoring low voltage drop linear voltage stabilizer |
| CN101369161A (en) * | 2008-10-14 | 2009-02-18 | 复旦大学 | Low-voltage difference linear voltage stabilizer without off-chip compensation capacitor |
| CN101943925A (en) * | 2009-07-06 | 2011-01-12 | 北京中电华大电子设计有限责任公司 | Discharge circuit for voltage regulators |
| CN102915061A (en) * | 2011-08-05 | 2013-02-06 | 深圳市汇春科技有限公司 | Low-voltage stabilizer for ultra-low static current |
| CN102707754A (en) * | 2012-05-30 | 2012-10-03 | 昆山锐芯微电子有限公司 | Low dropout regulator |
| CN104063003A (en) * | 2014-06-27 | 2014-09-24 | 合肥工业大学 | Low-power dissipation off-chip-capacitor-free LDO (Low Dropout Regulator) integrating slew rate enhancing circuit |
Cited By (17)
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|---|---|---|---|---|
| CN106354186A (en) * | 2015-07-21 | 2017-01-25 | 炬芯（珠海）科技有限公司 | Low-voltage-difference linear voltage stabilizer |
| CN105356856B (en) * | 2015-11-03 | 2018-10-16 | 天津大学 | The high-gain two-stage calculation amplifier insensitive suitable for technique under nano-scale |
| CN105356856A (en) * | 2015-11-03 | 2016-02-24 | 天津大学 | High-gain two-stage operational amplifier not sensitive to process in nanoscale |
| CN105425888A (en) * | 2015-12-29 | 2016-03-23 | 天津大学 | Low-output-current LDO (low dropout regulator) circuit applicable to power management and having Q-value adjusting function |
| CN105468082A (en) * | 2015-12-29 | 2016-04-06 | 天津大学 | Low-quiescent-current and large-load-driving LDO circuit suitable for power supply management |
| CN105468082B (en) * | 2015-12-29 | 2017-05-10 | 天津大学 | Low-quiescent-current and large-load-driving LDO circuit suitable for power supply management |
| CN105652946A (en) * | 2016-03-04 | 2016-06-08 | 广东顺德中山大学卡内基梅隆大学国际联合研究院 | Adaptive-bias low-load-regulation low dropout linear voltage stabilizer |
| EP3346351A1 (en) * | 2017-01-05 | 2018-07-11 | NXP USA, Inc. | Improved self-referenced low-dropout regulator |
| CN107479612A (en) * | 2017-10-16 | 2017-12-15 | 佛山科学技术学院 | A kind of quick response LDO circuit |
| CN107479612B (en) * | 2017-10-16 | 2023-02-28 | 佛山科学技术学院 | Quick response LDO circuit |
| CN110968145B (en) * | 2018-09-28 | 2021-09-14 | 华邦电子股份有限公司 | Low-voltage-drop voltage stabilizing circuit and voltage stabilizing method thereof |
| CN110968145A (en) * | 2018-09-28 | 2020-04-07 | 华邦电子股份有限公司 | Low-voltage-drop voltage stabilizing circuit and voltage stabilizing method thereof |
| CN109164864A (en) * | 2018-09-29 | 2019-01-08 | 西安微电子技术研究所 | A kind of line construction and control method reducing LDO power supply quiescent current |
| CN111834993A (en) * | 2020-08-17 | 2020-10-27 | 何清汉 | Automatic control system based on photovoltaic power station |
| CN113193750A (en) * | 2021-07-01 | 2021-07-30 | 成都市安比科技有限公司 | High-voltage-resistant LDO linear power supply realized by low-voltage MOSFET |
| CN114360464A (en) * | 2021-12-27 | 2022-04-15 | 北京奕斯伟计算技术有限公司 | Common voltage generating circuit, device thereof and display device |
| CN114360464B (en) * | 2021-12-27 | 2023-01-20 | 北京奕斯伟计算技术股份有限公司 | Common voltage generating circuit, device thereof and display device |
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