CN105468082B - Low-quiescent-current and large-load-driving LDO circuit suitable for power supply management - Google Patents
Low-quiescent-current and large-load-driving LDO circuit suitable for power supply management Download PDFInfo
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- CN105468082B CN105468082B CN201511030157.XA CN201511030157A CN105468082B CN 105468082 B CN105468082 B CN 105468082B CN 201511030157 A CN201511030157 A CN 201511030157A CN 105468082 B CN105468082 B CN 105468082B
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
- G05F1/10—Regulating voltage or current
- G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
- G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
- G05F1/565—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices sensing a condition of the system or its load in addition to means responsive to deviations in the output of the system, e.g. current, voltage, power factor
Abstract
The invention provides a low-quiescent-current and large-load-driving LDO circuit suitable for power supply management. One input end of a first transconductance gain input stage is connected with reference voltage, and the other input end of the first transconductance gain input stage is connected with a resistor feedback loop; the output end of the first transconductance gain input stage is divided into three ways, one way is connected with the input end of a second transconductance gain stage, one way is connected with a first active feedback buffer loop, and the third way is connected with a second active feedback buffer loop; the output end of the second transconductance gain stage is connected with a power transistor loop, the output end of the first active feedback buffer loop, the output end of the second active feedback buffer loop and the output end of the power transistor loop are all connected to the voltage output end; the power supply input end of the power transistor loop is connected with a power supply, one end of the resistor feedback loop is connected to the voltage output end, the other end of the resistor feedback loop is grounded, and the voltage output end is also grounded through series connection of a second resistor and a third capacitor and grounded through a fourth capacitor. According to the LDO circuit, conversion from a two-stage structure to a three-stage structure can be achieved, and loop stability is kept.
Description
Technical field
The present invention relates to a kind of low pressure difference linear voltage regulator.More particularly to a kind of low Static Electro suitable for power management
The LDO circuit of stream and driving heavy load.
Background technology
Modern portable electronic devices (mobile phone, digital music player, digital camera, handheld medical instrument and tester
Device etc.) need many voltage modulators to power each functional module.Low pressure difference linear voltage regulator (LDO) is non-convention
The selection thought.Because LDO chips have following technical characterstic：Accurate voltage reference, low quiescent current, low pressure drop adjustment
Pipe, the amplifier of high performance low noise, and stable and quick loop response.So these characteristics are based on, can be according to difference
Applied environment design with pointedly LDO chips.For in the case of the load capacitance for driving hundreds of pf, LDO can be protected
It is surely very very difficult to keep steady.The research of OCL output capacitance-less LDO (OCL-LDO) is very popular direction, because it reduces core
Impact of the parasitic capacitance on piece between the line of hundreds of I/O pad to chip internal.
The content of the invention
The technical problem to be solved be to provide it is a kind of drive larger or relative broad range load capacitance or
When person's resistance, keep the stable low quiescent currents suitable for power management of LDO and drive the LDO circuit of heavy load.
The technical solution adopted in the present invention is：A kind of low quiescent current suitable for power management and driving heavy load
LDO circuit, includes：Two gain amplification stages being made up of the first transadmittance gain input stage and the second transadmittance gain level respectively,
Power crystal tube loop, the first active feedback buffer loop, the second active feedback buffer loop, and resistance feedback loop, its
In, the input connection reference voltage Vref of the first transadmittance gain input stage, another input connection resistance is anti-
It is fed back to road, three tunnels of output end point of the first transadmittance gain input stage, the first via connects the input of the second transadmittance gain level, second
Road connects the first active feedback buffer loop, and the 3rd tunnel connects the second active feedback buffer loop, the second transadmittance gain level
Output end connection power crystal tube loop, the output end of the first active feedback buffer loop, the second active feedback buffering
The output end and power transistor loop output in loop is connected to voltage output end Vout, the power crystal tube loop
Power input connects power vd D, and the one end in the resistance feedback loop is connected to voltage output end Vout, and the other end is grounded,
Voltage output end Vout also passes through respectively the ground connection of connecting of second resistance Resr and the 3rd electric capacity Cout, and by the 4th electric capacity
CL is grounded.
The first described transadmittance gain input stage is made up of the second PMOS transistor M1 and the 4th PMOS transistor M2, the
Two transadmittance gain levels are made up of the 16th nmos pass transistor M15, wherein, second PMOS transistor M1 and the 4th PMOS are brilliant
The source electrode of body pipe M2 pass sequentially through jointly the second PMOS transistor M01 and the first PMOS transistor M00 connection power vd D, first
The grid of PMOS transistor M00 connects the first bias voltage Vb1, and the grid of the second PMOS transistor M01 connects the second biased electrical
Pressure Vb2, the grid connection resistance feedback loop of second PMOS transistor M1, the grid linker of the 4th PMOS transistor M2
Quasi- voltage Vref, the drain electrode of the second PMOS transistor M1 is constituted and exported all the way, and the drain electrode of the 4th PMOS transistor M2 constitutes two-way
Output, the drain electrode of second PMOS transistor M1 and the source electrode of the 7th nmos pass transistor M5 connect the 8th nmos pass transistor jointly
The drain electrode of M3, the source ground of the 8th nmos pass transistor M3, the drain electrode of the 4th PMOS transistor M2 all the way with the second active feedback
The source electrode that the 11st nmos pass transistor M6 of transadmittance gain level gma2 is constituted in buffer loop connects the 12nd NMOS crystal jointly
The drain electrode of pipe M4, the second electric capacity Cm2 separately led up in the second active feedback buffer loop is connected to voltage output end Vout,
The source ground of the tenth bi-NMOS transistor M4, the grid of the 7th nmos pass transistor M5 and the grid of the 11st nmos pass transistor M6
Common to connect the 3rd bias voltage Vb3, the grid of the tenth bi-NMOS transistor M4 and the grid of the 8th nmos pass transistor M3 are common
Connect the 4th bias voltage Vb4, the drain electrode of the 11st nmos pass transistor M6 connects the grid of the 16th nmos pass transistor M15, the
The drain electrode of 11 nmos pass transistor M6 also passes sequentially through the tenth PMOS transistor M8 and the 9th PMOS transistor M10 connection power supply
VDD, the grid of the tenth PMOS transistor M8 connects the second bias voltage Vb2, the grid and the 7th NMOS of the 9th PMOS transistor M10
The drain electrode of transistor M5 passes sequentially through first resistor Rm in the first active feedback buffer loop and the first electric capacity Cm1 connections jointly
To voltage output end Vout, the drain electrode of the 7th nmos pass transistor M5 is also by the 6th PMOS transistor M7 the first active feedback of connection
The drain electrode of the 5th PMOS transistor M9 of transadmittance gain level gma1 is constituted in buffer loop, the grid of the 5th PMOS transistor M9 leads to
First resistor Rm and the first electric capacity Cm1 crossed in the first active feedback buffer loop is connected to voltage output end Vout, and the 5th
The source electrode connection power vd D of PMOS transistor M9, the grid second bias voltage Vb2 of connection of the 6th PMOS transistor M7, the tenth
The source ground of six nmos pass transistor M15, drain electrode the 15th nmos pass transistor M14's of connection of the 16th nmos pass transistor M15
Source electrode, the grid of the 15th nmos pass transistor M14 connects the 3rd bias voltage Vb3, and the drain electrode of the 15th nmos pass transistor M14 connects
Connect described power crystal tube loop and pass sequentially through the 14th PMOS transistor M13 and the 13rd PMOS transistor M11 connects
Power vd D is met, the grid of the 14th PMOS transistor M13 connects the second bias voltage Vb2, the 13rd PMOS transistor M11
The described power crystal tube loop of grid connection.
Described power crystal tube loop includes the 17th PMOS transistor MP and the 5th electric capacity Cgd, wherein, the 17th
One end of the grid of PMOS transistor MP and the 5th electric capacity Cgd connects the grid and the tenth of the 13rd PMOS transistor M11 jointly
The drain electrode of five nmos pass transistor M14, the source electrode connection power vd D of the 17th PMOS transistor MP, the 17th PMOS transistor MP
Drain electrode and the other end of the 5th electric capacity Cgd be commonly connected to voltage output end Vout.
Described resistance feedback loop is in series by the first equivalent resistance Rf1 and the second equivalent resistance Rf2, wherein,
The end that first equivalent resistance Rf1 and the second equivalent resistance Rf2 are connected constitutes feedback end and connects in the first transadmittance gain input stage
The second PMOS transistor M1 grid, the other end of the first equivalent resistance Rf1 is connected to voltage output end Vout, and second is equivalent
The other end ground connection of resistance Rf2.
The first described equivalent resistance Rf1 include the 18th PMOS transistor M16, the 19th PMOS transistor M17 and
20th PMOS transistor M18, wherein, the source electrode of the 18th PMOS transistor M16 is connected to voltage output end Vout, and the 18th
The grid of PMOS transistor M16 and the source electrode of drain electrode the 19th PMOS transistor M17 of common connection, the 19th PMOS transistor
The source electrode of the grid of M17 and drain electrode the 20th PMOS transistor M18 of common connection, the grid of the 20th PMOS transistor M18 and
Drain electrode the second equivalent resistance Rf2 of common connection.
The second described equivalent resistance Rf2 includes the 21st PMOS transistor M19, the 22nd PMOS transistor
M20 and the 23rd PMOS transistor M21, wherein, the source electrode of the 21st PMOS transistor M19 connects the first equivalent resistance
Rf1, the grid of the 21st PMOS transistor M19 and the source electrode of drain electrode the 22nd PMOS transistor M20 of common connection, second
The grid of 12 PMOS transistors M20 and the source electrode of drain electrode the 23rd PMOS transistor M21 of common connection, the 23rd PMOS
The grid and drain electrode common ground of transistor M21.
The low quiescent current suitable for power management of the present invention and the LDO circuit of driving heavy load, using active Miller
The technology of capacitive feedback and wide driving capacitive load, can drive the load capacitance or resistance of larger either relative broad range
When, keep stablizing for LDO.When the load capacitance or resistance of larger either relative broad range is driven, the LDO of the present invention can be with
The conversion from two-layer configuration to tertiary structure is realized, stablizing for LDO loops is kept.
Description of the drawings
Fig. 1 is the present invention suitable for the low quiescent current of power management and the theory diagram of the LDO circuit for driving heavy load；
Fig. 2 is the circuit theory diagrams of Fig. 1.
Specific embodiment
With reference to the low quiescent current suitable for power management and driving heavy load of embodiment and accompanying drawing to the present invention
LDO circuit be described in detail.
The low quiescent current suitable for power management of the present invention and the LDO circuit of driving heavy load, two gains are amplified
Level, a power crystal tube loop, a resistance feedback loop and two active feedback buffer loop compositions.Two gains are amplified
Level be respectively：First transadmittance gain input stage gm1 and the second gain stage gm2.
As shown in figure 1, the LDO circuit of the low quiescent current suitable for power management of the present invention and driving heavy load, bag
Include：Two gain amplification stages being made up of the first transadmittance gain input stage gm1 and the second transadmittance gain level gm2 respectively, power
Crystal tube loop B, the first active feedback buffer loop D1, the second active feedback buffer loop D2, and resistance feedback loop R,
Wherein, the input connection reference voltage Vref of the first transadmittance gain input stage gm1, another input connection electricity
Resistance backfeed loop R, three tunnels of output end point of the first transadmittance gain input stage gm1, the first via connects the second transadmittance gain level gm2
Input, the second tunnel connects the first active feedback buffer loop D1, and the 3rd tunnel connects the second active feedback buffer loop D2, described
The output end connection power crystal tube loop B of the second transadmittance gain level gm2, the output of the first active feedback buffer loop D1
End, the output end of the second active feedback buffer loop D2 and power crystal tube loop B output ends are connected to voltage output end
The power input connection power vd D of Vout, the power crystal tube loop B, one end of the resistance feedback loop R is connected to
Voltage output end Vout, other end ground connection, voltage output end Vout is also respectively by second resistance Resr and the 3rd electric capacity Cout
Series connection ground connection, and by the 4th electric capacity CL be grounded.
The concrete composition of the low quiescent current suitable for power management of the present invention and the LDO circuit of driving heavy load is as schemed
It is specific as follows shown in 2：
The first described transadmittance gain input stage gm1 is by the second PMOS transistor M1 and the 4th PMOS transistor M2 structure
Into, the second transadmittance gain level gm2 is made up of the 16th nmos pass transistor M15, wherein, second PMOS transistor M1 and
The source electrode of four PMOS transistors M2 passes sequentially through the second PMOS transistor M01 and the first PMOS transistor M00 connection power supply jointly
VDD, the grid of the first PMOS transistor M00 connects the first bias voltage Vb1, the grid connection of the second PMOS transistor M01 the
Two bias voltage Vb2, the grid connection resistance feedback loop R of second PMOS transistor M1, the 4th PMOS transistor M2
Grid connects reference voltage Vref, and the drain electrode of the second PMOS transistor M1 is constituted and exported all the way, the leakage of the 4th PMOS transistor M2
Pole constitutes two-way output, and the drain electrode of second PMOS transistor M1 and the source electrode of the 7th nmos pass transistor M5 connect the 8th jointly
The drain electrode of nmos pass transistor M3, the source ground of the 8th nmos pass transistor M3, the drain electrode of the 4th PMOS transistor M2 is all the way with
The source electrode jointly connection the of the 11st nmos pass transistor M6 of transadmittance gain level gma2 is constituted in two active feedback buffer loop D2
The drain electrode of ten bi-NMOS transistor M4, the second electric capacity Cm2 separately led up in the second active feedback buffer loop D2 is connected to
Voltage output end Vout, the source ground of the tenth bi-NMOS transistor M4, the grid and the 11st of the 7th nmos pass transistor M5
The grid of nmos pass transistor M6 connects the 3rd bias voltage Vb3, the grid and the 8th NMOS of the tenth bi-NMOS transistor M4 jointly
The grid of transistor M3 connects the 4th bias voltage Vb4 jointly, and the drain electrode of the 11st nmos pass transistor M6 connects the 16th NMOS
The grid of transistor M15, the drain electrode of the 11st nmos pass transistor M6 also passes sequentially through the tenth PMOS transistor M8 and the 9th PMOS
Transistor M10 connects power vd D, and the grid of the tenth PMOS transistor M8 connects the second bias voltage Vb2, the 9th PMOS transistor
It is first electric that the grid of the grid of M10 and the 7th nmos pass transistor M5 is passed sequentially through in the first active feedback buffer loop D1 jointly
Resistance Rm and the first electric capacity Cm1 is connected to voltage output end Vout, and the grid of the 7th nmos pass transistor M5 is also brilliant by the 6th PMOS
Body pipe M7 connects the drain electrode of the 5th PMOS transistor M9 that transadmittance gain level gma1 is constituted in the first active feedback buffer loop D1,
The grid of the 5th PMOS transistor M9 is connected by first resistor Rm and the first electric capacity Cm1 in the first active feedback buffer loop D1
Voltage output end Vout is connected to, the source electrode connection power vd D of the 5th PMOS transistor M9, the grid of the 6th PMOS transistor M7 connects
Connect the second bias voltage Vb2, the source ground of the 16th nmos pass transistor M15, the drain electrode connection of the 16th nmos pass transistor M15
The source electrode of the 15th nmos pass transistor M14, grid the 3rd bias voltage Vb3 of connection of the 15th nmos pass transistor M14, the 15th
The described power crystal tube loop B of the drain electrode connection of nmos pass transistor M14 and pass sequentially through the 14th PMOS transistor M13 and
13rd PMOS transistor M11 connects power vd D, and the grid of the 14th PMOS transistor M13 connects the second bias voltage Vb2,
Power crystal tube loop B described in the grid connection of the 13rd PMOS transistor M11.
Described power crystal tube loop B includes the 17th PMOS transistor MP and the 5th electric capacity Cgd, wherein, the tenth
One end of the grid of seven PMOS transistors MP and the 5th electric capacity Cgd grid of the 13rd PMOS transistor M11 of connection and the jointly
The drain electrode of 15 nmos pass transistor M14, the source electrode connection power vd D of the 17th PMOS transistor MP, the 17th PMOS transistor
The drain electrode of MP and the other end of the 5th electric capacity Cgd are commonly connected to voltage output end Vout.
Described resistance feedback loop R is in series by the first equivalent resistance Rf1 and the second equivalent resistance Rf2, wherein,
The end that first equivalent resistance Rf1 and the second equivalent resistance Rf2 are connected constitutes feedback end and connects the first transadmittance gain input stage gm1
In the second PMOS transistor M1 grid, the other end of the first equivalent resistance Rf1 is connected to voltage output end Vout, second etc.
The other end ground connection of effect resistance Rf2.
The first described equivalent resistance Rf1 include the 18th PMOS transistor M16, the 19th PMOS transistor M17 and
20th PMOS transistor M18, wherein, the source electrode of the 18th PMOS transistor M16 is connected to voltage output end Vout, and the 18th
The grid of PMOS transistor M16 and the source electrode of drain electrode the 19th PMOS transistor M17 of common connection, the 19th PMOS transistor
The source electrode of the grid of M17 and drain electrode the 20th PMOS transistor M18 of common connection, the grid of the 20th PMOS transistor M18 and
Drain electrode the second equivalent resistance Rf2 of common connection.
The second described equivalent resistance Rf2 includes the 21st PMOS transistor M19, the 22nd PMOS transistor
M20 and the 23rd PMOS transistor M21, wherein, the source electrode of the 21st PMOS transistor M19 connects the first equivalent resistance
Rf1, the grid of the 21st PMOS transistor M19 and the source electrode of drain electrode the 22nd PMOS transistor M20 of common connection, second
The grid of 12 PMOS transistors M20 and the source electrode of drain electrode the 23rd PMOS transistor M21 of common connection, the 23rd PMOS
The grid and drain electrode common ground of transistor M21.
The low quiescent current suitable for power management of the present invention and the LDO circuit of driving heavy load, choose the 4th PMOS
The grid of transistor M2 as reference voltage input, the 13rd PMOS transistor M11 grid as feedback signal input terminal.
Then then signal reaches output end vo ut through folded common source and common grid level, power transistor.Simultaneously through two-way active feedback
Loop and a resistance feedback loop are maintaining the stability of LDO.So far signal complete feedback ratio in loop compared with and amplify.
The step that can test the small-signal AC response of LDO and big signal in the output end loading resistor and heavy load electric capacity of LDO is rung
Should.As a result showing the LDO of this money low quiescent current can drive the heavy load electric capacity of wide scope, while having response speed faster
Degree.
Claims (5)
1. a kind of low quiescent current suitable for power management and drive heavy load LDO circuit, it is characterised in that include：
Respectively by the first transadmittance gain input stage（gm1）With the second transadmittance gain level（gm2）Two gain amplification stages for constituting, power is brilliant
Body tube loop（B）, the first active feedback buffer loop（D1）, the second active feedback buffer loop（D2）, and resistance feedback time
Road（R）, wherein, the first transadmittance gain input stage（gm1）An input connection reference voltage（Vref）, another is defeated
Enter end connection resistance feedback loop（R）, the first transadmittance gain input stage（gm1）Output end point three tunnels, first via connection second
Transadmittance gain level（gm2）Input, the second tunnel connect the first active feedback buffer loop（D1）, it is active that the 3rd tunnel connects second
Feedback buffer loop（D2）, the second transadmittance gain level（gm2）Output end connection power crystal tube loop（B）, described
One active feedback buffer loop（D1）Output end, the second active feedback buffer loop（D2）Output end and power transistor return
Road（B）Output end is connected to voltage output end（Vout）, the power crystal tube loop（B）Power input connection power supply
（VDD）, the resistance feedback loop（R）One end be connected to voltage output end（Vout）, other end ground connection, voltage output end
（Vout）Also pass through second resistance respectively（Resr）With the 3rd electric capacity（Cout）Series connection ground connection, and by the 4th electric capacity（CL）
Ground connection, described power crystal tube loop（B）Include the 17th PMOS transistor（MP）With the 5th electric capacity（Cgd）, wherein, the
17 PMOS transistors（MP）Grid and the 5th electric capacity（Cgd）Common the 13rd PMOS transistor of connection in one end（M11）'s
Grid and the 15th nmos pass transistor（M14）Drain electrode, the 17th PMOS transistor（MP）Source electrode connection power supply（VDD）, the
17 PMOS transistors（MP）Drain electrode and the 5th electric capacity（Cgd）The other end be commonly connected to voltage output end（Vout）.
2. the low quiescent current suitable for power management according to claim 1 and the LDO circuit of heavy load is driven, it is special
Levy and be, the first described transadmittance gain input stage（gm1）It is by the second PMOS transistor（M1）With the 4th PMOS transistor
（M2）Constitute, the second transadmittance gain level（gm2）It is by the 16th nmos pass transistor（M15）Constitute, wherein, the 2nd PMOS is brilliant
Body pipe（M1）With the 4th PMOS transistor（M2）Source electrode pass sequentially through the 3rd PMOS transistor jointly（M01）It is brilliant with a PMOS
Body pipe（M00）Connection power supply（VDD）, the first PMOS transistor（M00）Grid connect the first bias voltage（Vb1）, the 3rd
PMOS transistor（M01）Grid connect the second bias voltage（Vb2）, second PMOS transistor（M1）Grid connection electricity
Resistance backfeed loop（R）, the 4th PMOS transistor（M2）Grid connection reference voltage（Vref）, the second PMOS transistor（M1）'s
Drain electrode is constituted and exported all the way, the 4th PMOS transistor（M2）Drain electrode constitute two-way output, second PMOS transistor（M1）
Drain electrode and the 7th nmos pass transistor（M5）Common the 8th nmos pass transistor of connection of source electrode（M3）Drain electrode, the 8th NMOS crystal
Pipe（M3）Source ground, the 4th PMOS transistor（M2）Drain electrode all the way with the second active feedback buffer loop（D2）Middle composition
Transadmittance gain level（gma2）The 11st nmos pass transistor（M6）Common the tenth bi-NMOS transistor of connection of source electrode（M4）Leakage
Pole, separately leads up to the second active feedback buffer loop（D2）In the second electric capacity（Cm2）It is connected to voltage output end（Vout）,
Tenth bi-NMOS transistor（M4）Source ground, the 7th nmos pass transistor（M5）Grid and the 11st nmos pass transistor（M6）
Common the 3rd bias voltage of connection of grid（Vb3）, the tenth bi-NMOS transistor（M4）Grid and the 8th nmos pass transistor
（M3）Common the 4th bias voltage of connection of grid（Vb4）, the 11st nmos pass transistor（M6）Drain electrode connect the 16th NMOS
Transistor（M15）Grid, the 11st nmos pass transistor（M6）Drain electrode also pass sequentially through the tenth PMOS transistor（M8）With
Nine PMOS transistors（M10）Connection power supply（VDD）, the tenth PMOS transistor（M8）Grid connect the second bias voltage（Vb2）,
9th PMOS transistor（M10）Grid and the 7th nmos pass transistor（M5）Drain electrode pass sequentially through jointly the first active feedback delay
Refunds road（D1）In first resistor（Rm）With the first electric capacity（Cm1）It is connected to voltage output end（Vout）, the 7th NMOS crystal
Pipe（M5）Drain electrode also pass through the 6th PMOS transistor（M7）Connect the first active feedback buffer loop（D1）The mutual conductance of middle composition increases
Beneficial level（gma1）The 5th PMOS transistor（M9）Drain electrode, the 5th PMOS transistor（M9）Grid pass through the first active feedback
Buffer loop（D1）In first resistor（Rm）With the first electric capacity（Cm1）It is connected to voltage output end（Vout）, the 5th PMOS is brilliant
Body pipe（M9）Source electrode connection power supply（VDD）, the 6th PMOS transistor（M7）Grid connect the second bias voltage（Vb2）, the
16 nmos pass transistors（M15）Source ground, the 16th nmos pass transistor（M15）Drain electrode connect the 15th nmos pass transistor
（M14）Source electrode, the 15th nmos pass transistor（M14）Grid connect the 3rd bias voltage（Vb3）, the 15th nmos pass transistor
（M14）The described power crystal tube loop of drain electrode connection（B）And pass sequentially through the 14th PMOS transistor（M13）With the tenth
Three PMOS transistors（M11）Connection power supply（VDD）, the 14th PMOS transistor（M13）Grid connect the second bias voltage
（Vb2）, the 13rd PMOS transistor（M11）The described power crystal tube loop of grid connection（B）.
3. the low quiescent current suitable for power management according to claim 1 and the LDO circuit of heavy load is driven, it is special
Levy and be, described resistance feedback loop（R）It is by the first equivalent resistance（Rf1）With the second equivalent resistance（Rf2）It is in series,
Wherein, the first equivalent resistance（Rf1）With the second equivalent resistance（Rf2）The end being connected constitutes feedback end and connects the first transadmittance gain
Input stage（gm1）In the second PMOS transistor（M1）Grid, the first equivalent resistance（Rf1）The other end to be connected to voltage defeated
Go out end（Vout）, the second equivalent resistance（Rf2）The other end ground connection.
4. the low quiescent current suitable for power management according to claim 3 and the LDO circuit of heavy load is driven, it is special
Levy and be, the first described equivalent resistance（Rf1）Include the 18th PMOS transistor（M16）, the 19th PMOS transistor
（M17）With the 20th PMOS transistor（M18）, wherein, the 18th PMOS transistor（M16）Source electrode be connected to voltage output end
（Vout）, the 18th PMOS transistor（M16）Grid and drain electrode the 19th PMOS transistor of common connection（M17）Source electrode,
19th PMOS transistor（M17）Grid and drain electrode the 20th PMOS transistor of common connection（M18）Source electrode, the 20th
PMOS transistor（M18）Grid and drain electrode the second equivalent resistance of common connection（Rf2）.
5. the low quiescent current suitable for power management according to claim 3 and the LDO circuit of heavy load is driven, it is special
Levy and be, the second described equivalent resistance（Rf2）Include the 21st PMOS transistor（M19）, the 22nd PMOS crystal
Pipe（M20）With the 23rd PMOS transistor（M21）, wherein, the 21st PMOS transistor（M19）Source electrode connection first etc.
Effect resistance（Rf1）, the 21st PMOS transistor（M19）Grid and drain electrode the 22nd PMOS transistor of common connection
（M20）Source electrode, the 22nd PMOS transistor（M20）Grid and drain electrode the 23rd PMOS transistor of common connection
（M21）Source electrode, the 23rd PMOS transistor（M21）Grid and drain electrode common ground.
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| CN201511030157.XA CN105468082B (en) | 2015-12-29 | 2015-12-29 | Low-quiescent-current and large-load-driving LDO circuit suitable for power supply management |
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| CN201511030157.XA CN105468082B (en) | 2015-12-29 | 2015-12-29 | Low-quiescent-current and large-load-driving LDO circuit suitable for power supply management |
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| CN108062139A (en) * | 2018-02-06 | 2018-05-22 | 上海毅栈半导体科技有限公司 | A kind of LDO circuit of the LDO circuit of ultra low quiescent power consumption and the ultra low quiescent power consumption of driving heavy load |
| CN109164864B (en) * | 2018-09-29 | 2019-07-23 | 西安微电子技术研究所 | A kind of line construction and control method reducing LDO power supply quiescent current |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101957627A (en) * | 2010-11-02 | 2011-01-26 | 深圳市富满电子有限公司南山分公司 | LDO constant voltage control circuit |
| CN103760943A (en) * | 2014-01-13 | 2014-04-30 | 合肥工业大学 | Slew rate enhancement circuit applicable to LDO regulators (low dropout regulators) |
| CN104656733A (en) * | 2015-02-12 | 2015-05-27 | 天津大学 | LDO (low dropout regulator) capable of outputting ultra-low quiescent current in self-adaptation way |
| CN104950975A (en) * | 2015-06-30 | 2015-09-30 | 电子科技大学 | Low dropout voltage regulator |
| CN205263698U (en) * | 2015-12-29 | 2016-05-25 | 天津大学 | LDO circuit of low quiescent current and drive heavy load suitable for power management |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US8872492B2 (en) * | 2010-04-29 | 2014-10-28 | Qualcomm Incorporated | On-chip low voltage capacitor-less low dropout regulator with Q-control |
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Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101957627A (en) * | 2010-11-02 | 2011-01-26 | 深圳市富满电子有限公司南山分公司 | LDO constant voltage control circuit |
| CN103760943A (en) * | 2014-01-13 | 2014-04-30 | 合肥工业大学 | Slew rate enhancement circuit applicable to LDO regulators (low dropout regulators) |
| CN104656733A (en) * | 2015-02-12 | 2015-05-27 | 天津大学 | LDO (low dropout regulator) capable of outputting ultra-low quiescent current in self-adaptation way |
| CN104950975A (en) * | 2015-06-30 | 2015-09-30 | 电子科技大学 | Low dropout voltage regulator |
| CN205263698U (en) * | 2015-12-29 | 2016-05-25 | 天津大学 | LDO circuit of low quiescent current and drive heavy load suitable for power management |
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| CN105468082A (en) | 2016-04-06 |
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