CN205263698U - LDO circuit of low quiescent current and drive heavy load suitable for power management - Google Patents
LDO circuit of low quiescent current and drive heavy load suitable for power management Download PDFInfo
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- CN205263698U CN205263698U CN201521138924.4U CN201521138924U CN205263698U CN 205263698 U CN205263698 U CN 205263698U CN 201521138924 U CN201521138924 U CN 201521138924U CN 205263698 U CN205263698 U CN 205263698U
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Abstract
The utility model provides a LDO circuit of low quiescent current and drive heavy load suitable for power management, reference voltage is connected to an input of first mutual conductance gain input stage, another input connecting resistance feedback loop, the output of first mutual conductance gain input stage divides the three routes, the input of connecting second mutual conductance gain stage all the way, connect first active feedback buffering return circuit all the way, second active feedback buffering return circuit is connected on the third way, the power transistor return circuit is connected to the output of second mutual conductance gain stage, the output in first active feedback buffering return circuit, the output and the power transistor return circuit output in second active feedback buffering return circuit all are connected to the voltage output end, the power input end in power transistor return circuit is connected, resistance feedback loop's one end is connected to the voltage output end, and the other terminal of the capacitor is connected to the ground, the voltage output end is still respectively through the series connection ground connection of second resistance with third electric capacity, through the fourth capacity ground. The utility model discloses can realize the conversion from the two -stage structure to tertiary structure, keep the loop stable.
Description
Technical field
The utility model relates to a kind of low pressure difference linear voltage regulator. Particularly relate to a kind of low quiescent current that is applicable to power managementWith the LDO circuit that drives heavy load.
Background technology
Modern portable electronic devices (mobile phone, digital music player, digital camera, handheld medical instrument and tester etc.)Need many voltage modulators to power to each functional module. Low pressure difference linear voltage regulator (LDO) is idealSelect. Because LDO chip has following technical characterstic: accurate voltage reference, low quiescent current, low pressure drop adjustment pipe,The amplifier of high performance low noise, and stable and loop response fast. So based on these characteristics, can be according to different answeringProvide LDO chip targetedly by Environment Design. For driving in the load capacitance situation of hundreds of pf, LDO can keepStable is very very difficult. The research of OCL output capacitance-less LDO (OCL-LDO) is very popular direction, because it reducesThe impact of parasitic capacitance on chip between the line of hundreds of I/Opad on chip internal.
Summary of the invention
Technical problem to be solved in the utility model is, provide a kind of drive large or relative broad range load capacitance orWhen resistance, keep the low quiescent current that is applicable to power management that LDO is stable and the LDO circuit that drives heavy load.
The technical scheme that the utility model adopts is: a kind of low quiescent current that is applicable to power management and drive heavy loadLDO circuit, includes: two gain amplifying stages that formed by the first transadmittance gain input stage and the second transadmittance gain level respectively,Power crystal tube loop, the first active feedback buffer loop, the second active feedback buffer loop, and resistance feedback loop, itsIn, an input of described the first transadmittance gain input stage connects reference voltage V ref, another input contact resistance feedbackLoop, the output Fen San road of the first transadmittance gain input stage, the first via connects the input of the second transadmittance gain level, the second tunnelConnect the first active feedback buffer loop, Third Road connects the second active feedback buffer loop, described the second transadmittance gain level defeatedGo out end and connect power crystal tube loop, the output of described the first active feedback buffer loop, the second active feedback buffer loopOutput and power crystal tube loop output are all connected to voltage output end Vout, the power supply input of described power crystal tube loopEnd connects power vd D, and the one end in described resistance feedback loop is connected to voltage output end Vout, other end ground connection, Voltage-outputEnd Vout is also respectively by the ground connection of connecting of the second resistance R esr and the 3rd capacitor C out, and passes through the 4th capacitor C L ground connection.
The first described transadmittance gain input stage is to be made up of the 2nd PMOS transistor M1 and the 4th PMOS transistor M2,The second transadmittance gain level is to be made up of the 16 nmos pass transistor M15, wherein, described the 2nd PMOS transistor M1 andThe source electrode of the 4th PMOS transistor M2 is jointly successively by the 2nd PMOS transistor M01 and a PMOS transistor M00Connect power vd D, the grid of a PMOS transistor M00 connects the first bias voltage Vb1, the 2nd PMOS transistorThe grid of M01 connects the second bias voltage Vb2, the grid contact resistance backfeed loop of described the 2nd PMOS transistor M1,The grid of the 4th PMOS transistor M2 connects reference voltage V ref, and it is defeated that the drain electrode of the 2nd PMOS transistor M1 forms a roadGo out, the drain electrode of the 4th PMOS transistor M2 forms two-way output, the drain electrode of described the 2nd PMOS transistor M1 and the 7thThe common drain electrode that connects the 8th nmos pass transistor M3 of source electrode of nmos pass transistor M5, the 8th nmos pass transistor M3Source ground, in drain electrode one road of the 4th PMOS transistor M2 and the second active feedback buffer loop, form transadmittance gain levelThe common drain electrode that connects the tenth bi-NMOS transistor M4 of source electrode of the 11 nmos pass transistor M6 of gma2, another roadBe connected to voltage output end Vout, the 12 NMOS crystal by the second capacitor C m2 in the second active feedback buffer loopThe source ground of pipe M4, the 7th grid of nmos pass transistor M5 and the grid of the 11 nmos pass transistor M6 connect jointlyMeet the 3rd bias voltage Vb3, the grid of the grid of the tenth bi-NMOS transistor M4 and the 8th nmos pass transistor M3 is commonConnect the 4th bias voltage Vb4, the drain electrode of the 11 nmos pass transistor M6 connects the 16 nmos pass transistor M15'sGrid, the drain electrode of the 11 nmos pass transistor M6 is also successively by the tenth PMOS transistor M8 and the 9th PMOS crystalline substanceBody pipe M10 connects power vd D, and the grid of the tenth PMOS transistor M8 meets the second bias voltage Vb2, the 9th PMOSThe drain electrode of the grid of transistor M10 and the 7th nmos pass transistor M5 is jointly successively by the first active feedback buffer loopThe first resistance R m and the first capacitor C m1 be connected to voltage output end Vout, the drain electrode of the 7th nmos pass transistor M5 is alsoConnect the 5th PMOS that forms transadmittance gain level gma1 in the first active feedback buffer loop by the 6th PMOS transistor M7The drain electrode of transistor M9, the grid of the 5th PMOS transistor M9 is by the first resistance in the first active feedback buffer loopRm and the first capacitor C m1 are connected to voltage output end Vout, and the source electrode of the 5th PMOS transistor M9 connects power vd D,The grid of the 6th PMOS transistor M7 connects the second bias voltage Vb2, and the source electrode of the 16 nmos pass transistor M15 connectsGround, the drain electrode of the 16 nmos pass transistor M15 connects the source electrode of the 15 nmos pass transistor M14, the 15 NMOSThe grid of transistor M14 connects the 3rd bias voltage Vb3, and the drain electrode of the 15 nmos pass transistor M14 connects described meritRate transistor loop and be connected power supply with the 13 PMOS transistor M11 by the 14 PMOS transistor M13 successivelyVDD, the grid of the 14 PMOS transistor M13 connects the second bias voltage Vb2, the 13 PMOS transistor M11Grid connect described power crystal tube loop.
Described power crystal tube loop includes the 17 PMOS transistor MP and the 5th capacitor C gd, wherein, and the 17The grid of PMOS transistor MP and one end of the 5th capacitor C gd are connected the grid of the 13 PMOS transistor M11 jointlyWith the drain electrode of the 15 nmos pass transistor M14, the source electrode of the 17 PMOS transistor MP connects power vd D, the tenthSeven drain electrodes of PMOS transistor MP and the other end of the 5th capacitor C gd are connected to voltage output end Vout jointly.
Described resistance feedback loop is in series by the first equivalent resistance Rf1 and the second equivalent resistance Rf2, wherein, and firstThe end that equivalent resistance Rf1 is connected with the second equivalent resistance Rf2 forms feedback end and is connected second in the first transadmittance gain input stageThe grid of PMOS transistor M1, the other end of the first equivalent resistance Rf1 is connected to voltage output end Vout, the second equivalent electricThe other end ground connection of resistance Rf2.
The first described equivalent resistance Rf1 includes the 18 PMOS transistor M16, the 19 PMOS transistor M17With the 20 PMOS transistor M18, wherein, the source electrode of the 18 PMOS transistor M16 is connected to voltage output end Vout,The grid of the 18 PMOS transistor M16 and the common source electrode that is connected the 19 PMOS transistor M17 of drain electrode, the 19The grid of PMOS transistor M17 and the common source electrode that is connected the 20 PMOS transistor M18 of drain electrode, the 20 PMOSThe grid of transistor M18 is connected the second equivalent resistance Rf2 jointly with drain electrode.
The second described equivalent resistance Rf2 includes the 21 PMOS transistor M19, the 22 PMOS transistorM20 and the 23 PMOS transistor M21, wherein, the source electrode connection first of the 21 PMOS transistor M19 etc.Common the 22 PMOS transistor M20 that is connected of the grid of effect resistance R _ f 1, the 21 PMOS transistor M19 and drain electrodeSource electrode, the grid of the 22 PMOS transistor M20 with drain electrode be jointly connected the 23 PMOS transistor M21'sSource electrode, the grid of the 23 PMOS transistor M21 and drain electrode common ground.
The LDO circuit that is applicable to the low quiescent current of power management and drives heavy load of the present utility model, adopts active Miller electricityHold feedback and the technology of wide driving capacitive load, can be in the time driving the load capacitance of large or relative broad range or resistance, guarantorHold the stable of LDO. In the time driving the load capacitance of large or relative broad range or resistance, LDO of the present utility model canTo realize the conversion from two-layer configuration to tertiary structure, keep the stable of LDO loop.
Brief description of the drawings
Fig. 1 is the theory diagram that the utility model is applicable to the low quiescent current of power management and the LDO circuit of driving heavy load;
Fig. 2 is the circuit theory diagrams of Fig. 1.
Detailed description of the invention
Be applicable to the low quiescent current of power management and drive heavy load of the present utility model below in conjunction with embodiment and accompanying drawingLDO circuit is described in detail.
The LDO circuit that is applicable to the low quiescent current of power management and drives heavy load of the present utility model, two gains are amplifiedLevel, a power crystal tube loop, a resistance feedback loop and two active feedback buffer loop compositions. Two gains are amplifiedLevel respectively: the first transadmittance gain input stage gm1 and the second gain stage gm2.
As shown in Figure 1, the LDO circuit that is applicable to the low quiescent current of power management and drives heavy load of the present utility model, bagDraw together: two gain amplifying stages that formed by the first transadmittance gain input stage gm1 and the second transadmittance gain level gm2 respectively, powerTransistor loop B, the first active feedback buffer loop D1, the second active feedback buffer loop D2, and resistance feedback loop R,Wherein, an input of described the first transadmittance gain input stage gm1 connects reference voltage V ref, and another input connects electricityResistance backfeed loop R, the output Fen San road of the first transadmittance gain input stage gm1, the first via connects the second transadmittance gain level gm2Input, the second tunnel connects the first active feedback buffer loop D1, Third Road connects the second active feedback buffer loop D2,The output of described the second transadmittance gain level gm2 connects power crystal tube loop B, described the first active feedback buffer loop D1The output of output, the second active feedback buffer loop D2 and power crystal tube loop B output to be all connected to voltage defeatedGo out to hold Vout, the power input of described power crystal tube loop B connects power vd D, one of described resistance feedback loop REnd is connected to voltage output end Vout, other end ground connection, and voltage output end Vout is also respectively by the second resistance R esr and the 3rdThe series connection ground connection of capacitor C out, and by the 4th capacitor C L ground connection.
The concrete formation that is applicable to the low quiescent current of power management and the LDO circuit of driving heavy load of the present utility model is as Fig. 2Shown in, specific as follows:
The first described transadmittance gain input stage gm1 is by the 2nd PMOS transistor M1 and the 4th PMOS transistor M2Form, the second transadmittance gain level gm2 is made up of the 16 nmos pass transistor M15, wherein, and described the 2nd PMOS crystalline substanceThe source electrode of body pipe M1 and the 4th PMOS transistor M2 is jointly successively by the 2nd PMOS transistor M01 and a PMOSTransistor M00 connects power vd D, and the grid of a PMOS transistor M00 connects the first bias voltage Vb1, secondThe grid of PMOS transistor M01 connects the second bias voltage Vb2, and the grid of described the 2nd PMOS transistor M1 connects electricityResistance backfeed loop R, the grid of the 4th PMOS transistor M2 connects reference voltage V ref, the 2nd PMOS transistor M1'sDrain electrode forms a road output, and the drain electrode of the 4th PMOS transistor M2 forms two-way output, described the 2nd PMOS transistorThe source electrode of the drain electrode of M1 and the 7th nmos pass transistor M5 is connected the drain electrode of the 8th nmos pass transistor M3, the 8th jointlyThe source ground of nmos pass transistor M3, drain electrode one road of the 4th PMOS transistor M2 and the second active feedback buffer loopIn D2, form common the 12 NMOS crystal that connects of source electrode of the 11 nmos pass transistor M6 of transadmittance gain level gma2The drain electrode of pipe M4, the second capacitor C m2 of separately leading up in the second active feedback buffer loop D2 is connected to voltage output endVout, the source ground of the tenth bi-NMOS transistor M4, the grid of the 7th nmos pass transistor M5 and the 11 NMOSCommon the 3rd bias voltage Vb3, the grid of the tenth bi-NMOS transistor M4 and the 8th NMOS of connecting of grid of transistor M6Common the 4th bias voltage Vb4 that connects of grid of transistor M3, the drain electrode of the 11 nmos pass transistor M6 connects the 16The grid of nmos pass transistor M15, the drain electrode of the 11 nmos pass transistor M6 is also successively by the tenth PMOS transistorM8 is connected power vd D with the 9th PMOS transistor M10, and the grid of the tenth PMOS transistor M8 connects the second biased electricalPress Vb2, the 9th grid of PMOS transistor M10 and the grid of the 7th nmos pass transistor M5 are jointly successively by firstThe first resistance R m and the first capacitor C m1 in active feedback buffer loop D1 are connected to voltage output end Vout, the 7th NMOSThe grid of transistor M5 is also connected in the first active feedback buffer loop D1 and is formed mutual conductance by the 6th PMOS transistor M7The drain electrode of the 5th PMOS transistor M9 of gain stage gma1, the grid of the 5th PMOS transistor M9 is active by firstThe first resistance R m and the first capacitor C m1 in feedback buffer loop D1 are connected to voltage output end Vout, the 5th PMOS crystalline substanceThe source electrode of body pipe M9 connects power vd D, and the grid of the 6th PMOS transistor M7 connects the second bias voltage Vb2, the tenthThe source ground of six nmos pass transistor M15, the drain electrode of the 16 nmos pass transistor M15 connects the 15 NMOS crystalline substanceThe source electrode of body pipe M14, the grid of the 15 nmos pass transistor M14 connects the 3rd bias voltage Vb3, the 15 NMOSThe drain electrode of transistor M14 connect described power crystal tube loop B and successively by the 14 PMOS transistor M13 andThe 13 PMOS transistor M11 connects power vd D, and the grid of the 14 PMOS transistor M13 connects the second biased electricalPress Vb2, the grid of the 13 PMOS transistor M11 connects described power crystal tube loop B.
Described power crystal tube loop B includes the 17 PMOS transistor MP and the 5th capacitor C gd, wherein, and the tenthSeven grids of PMOS transistor MP and one end of the 5th capacitor C gd are connected the grid of the 13 PMOS transistor M11 jointlyThe drain electrode of the utmost point and the 15 nmos pass transistor M14, the source electrode of the 17 PMOS transistor MP connects power vd D, the17 drain electrodes of PMOS transistor MP and the other end of the 5th capacitor C gd are connected to voltage output end Vout jointly.
Described resistance feedback loop R is in series by the first equivalent resistance Rf1 and the second equivalent resistance Rf2, wherein, theThe end that one equivalent resistance R _ f 1 is connected with the second equivalent resistance Rf2 forms feedback end and is connected in the first transadmittance gain input stage gm1The grid of the 2nd PMOS transistor M1, the other end of the first equivalent resistance Rf1 is connected to voltage output end Vout, secondThe other end ground connection of equivalent resistance Rf2.
The first described equivalent resistance Rf1 includes the 18 PMOS transistor M16, the 19 PMOS transistor M17With the 20 PMOS transistor M18, wherein, the source electrode of the 18 PMOS transistor M16 is connected to voltage output end Vout,The grid of the 18 PMOS transistor M16 and the common source electrode that is connected the 19 PMOS transistor M17 of drain electrode, the 19The grid of PMOS transistor M17 and the common source electrode that is connected the 20 PMOS transistor M18 of drain electrode, the 20 PMOSThe grid of transistor M18 is connected the second equivalent resistance Rf2 jointly with drain electrode.
The second described equivalent resistance Rf2 includes the 21 PMOS transistor M19, the 22 PMOS transistorM20 and the 23 PMOS transistor M21, wherein, the source electrode connection first of the 21 PMOS transistor M19 etc.Common the 22 PMOS transistor M20 that is connected of the grid of effect resistance R _ f 1, the 21 PMOS transistor M19 and drain electrodeSource electrode, the grid of the 22 PMOS transistor M20 with drain electrode be jointly connected the 23 PMOS transistor M21'sSource electrode, the grid of the 23 PMOS transistor M21 and drain electrode common ground.
The LDO circuit that is applicable to the low quiescent current of power management and drives heavy load of the present utility model, chooses the 4th PMOSThe grid of transistor M2 is inputted as feedback signal as the grid of reference voltage input, the 13 PMOS transistor M11End. Then signal is through folded common source and common grid level, and power transistor, then arrives output end vo ut. Pass through two-way active simultaneouslyBackfeed loop and resistance feedback loop maintain the stability of LDO. So far signal has completed the feedback ratio in loop and has putGreatly. Output loading resistor and heavy load electric capacity at LDO can be tested the small-signal AC response of LDO and the rank of large-signalResponse jumps. Result shows that the LDO of this money low quiescent current can drive the heavy load electric capacity of wide region, has faster simultaneously and ringsAnswer speed.
Claims (6)
1. be applicable to the low quiescent current of power management and a LDO circuit for driving heavy load, it is characterized in that, include:Two gain amplifying stages that formed by the first transadmittance gain input stage (gm1) and the second transadmittance gain level (gm2) respectively, meritRate transistor loop (B), the first active feedback buffer loop (D1), the second active feedback buffer loop (D2), Yi Ji electricityResistance backfeed loop (R), wherein, an input of described the first transadmittance gain input stage (gm1) connects reference voltage (Vref),Another input contact resistance backfeed loop (R), the output Fen San road of the first transadmittance gain input stage (gm1), firstRoad connects the input of the second transadmittance gain level (gm2), and the second tunnel connects the first active feedback buffer loop (D1), the 3rdRoad connects the second active feedback buffer loop (D2), and the output of described the second transadmittance gain level (gm2) connects power crystalTube loop (B), the output of described the first active feedback buffer loop (D1), the second active feedback buffer loop (D2)Output and power crystal tube loop (B) output be all connected to voltage output end (Vout), described power crystal tube loop(B) power input connects power supply (VDD), and the one end in described resistance feedback loop (R) is connected to voltage output end(Vout), other end ground connection, voltage output end (Vout) is also respectively by the second resistance (Resr) and the 3rd electric capacity (Cout)Series connection ground connection, and by the 4th electric capacity (CL) ground connection.
2. the LDO circuit that is applicable to the low quiescent current of power management and drives heavy load according to claim 1, itsBe characterised in that, the first described transadmittance gain input stage (gm1) is by the 2nd PMOS transistor (M1) and the 4th PMOSTransistor (M2) forms, and the second transadmittance gain level (gm2) is to be made up of the 16 nmos pass transistor (M15), itsIn, the source electrode of described the 2nd PMOS transistor (M1) and the 4th PMOS transistor (M2) is jointly successively by secondPMOS transistor (M01) is connected power supply (VDD), a PMOS transistor with a PMOS transistor (M00)(M00) grid connects the first bias voltage (Vb1), and the grid of the 2nd PMOS transistor (M01) connects the second biasingVoltage (Vb2), the grid contact resistance backfeed loop (R) of described the 2nd PMOS transistor (M1), the 4th PMOSThe grid of transistor (M2) connects reference voltage (Vref), and it is defeated that the drain electrode of the 2nd PMOS transistor (M1) forms a roadGo out, the drain electrode of the 4th PMOS transistor (M2) forms two-way output, the drain electrode of described the 2nd PMOS transistor (M1)With the common drain electrode that is connected the 8th nmos pass transistor (M3) of source electrode of the 7th nmos pass transistor (M5), the 8th NMOSThe source ground of transistor (M3), drain electrode one tunnel of the 4th PMOS transistor (M2) and the second active feedback buffer loop(D2) in, form the common connection the 12 of source electrode of the 11 nmos pass transistor (M6) of transadmittance gain level (gma2)The drain electrode of nmos pass transistor (M4), second electric capacity (Cm2) of separately leading up in the second active feedback buffer loop (D2)Be connected to voltage output end (Vout), the source ground of the tenth bi-NMOS transistor (M4), the 7th nmos pass transistor(M5) grid of grid and the 11 nmos pass transistor (M6) is connected the 3rd bias voltage (Vb3), the tenth jointlyThe grid of the grid of bi-NMOS transistor (M4) and the 8th nmos pass transistor (M3) is connected the 4th bias voltage jointly(Vb4), the drain electrode of the 11 nmos pass transistor (M6) connects the grid of the 16 nmos pass transistor (M15),The drain electrode of the 11 nmos pass transistor (M6) is also successively by the tenth PMOS transistor (M8) and the 9th PMOS crystalline substanceBody pipe (M10) connects power supply (VDD), and the grid of the tenth PMOS transistor (M8) connects the second bias voltage (Vb2),The drain electrode of the grid of the 9th PMOS transistor (M10) and the 7th nmos pass transistor (M5) has by first jointly successivelyThe first resistance (Rm) and the first electric capacity (Cm1) in source feedback buffer loop (D1) are connected to voltage output end (Vout),The drain electrode of the 7th nmos pass transistor (M5) also connects the first active feedback buffering by the 6th PMOS transistor (M7)In loop (D1), form the drain electrode of the 5th PMOS transistor (M9) of transadmittance gain level (gma1), the 5th PMOSThe grid of transistor (M9) is by the first resistance (Rm) and the first electric capacity (Cm1) in the first active feedback buffer loop (D1)Be connected to voltage output end (Vout), the source electrode of the 5th PMOS transistor (M9) connects power supply (VDD), the 6th PMOSThe grid of transistor (M7) connects the second bias voltage (Vb2), the source ground of the 16 nmos pass transistor (M15),The drain electrode of the 16 nmos pass transistor (M15) connects the source electrode of the 15 nmos pass transistor (M14), the 15 NMOSThe grid of transistor (M14) connects the 3rd bias voltage (Vb3), and the drain electrode of the 15 nmos pass transistor (M14) connectsConnect described power crystal tube loop (B) and pass through successively the 14 PMOS transistor (M13) and the 13 PMOSTransistor (M11) connects power supply (VDD), and the grid of the 14 PMOS transistor (M13) connects the second bias voltage(Vb2), the grid of the 13 PMOS transistor (M11) connects described power crystal tube loop (B).
3. the LDO circuit that is applicable to the low quiescent current of power management and drives heavy load according to claim 1, itsBe characterised in that, described power crystal tube loop (B) includes the 17 PMOS transistor (MP) and the 5th electric capacity (Cgd),Wherein, one end of the grid of the 17 PMOS transistor (MP) and the 5th electric capacity (Cgd) is connected the 13 PMOS jointlyThe grid of transistor (M11) and the drain electrode of the 15 nmos pass transistor (M14), the 17 PMOS transistor (MP)Source electrode connect power supply (VDD), the other end of the drain electrode of the 17 PMOS transistor (MP) and the 5th electric capacity (Cgd)Jointly be connected to voltage output end (Vout).
4. the LDO circuit that is applicable to the low quiescent current of power management and drives heavy load according to claim 1, itsBe characterised in that, described resistance feedback loop (R) is by the first equivalent resistance (Rf1) and the second equivalent resistance (Rf2) stringConnection forms, and wherein, end that the first equivalent resistance (Rf1) is connected with the second equivalent resistance (Rf2) formation feedback end is connected theThe grid of the 2nd PMOS transistor (M1) in one transadmittance gain input stage (gm1), the first equivalent resistance (Rf1)The other end is connected to voltage output end (Vout), the other end ground connection of the second equivalent resistance (Rf2).
5. the LDO circuit that is applicable to the low quiescent current of power management and drives heavy load according to claim 4, itsBe characterised in that, described the first equivalent resistance (Rf1) includes the 18 PMOS transistor (M16), the 19 PMOSTransistor (M17) and the 20 PMOS transistor (M18), wherein, the source of the 18 PMOS transistor (M16)The utmost point is connected to voltage output end (Vout), and the grid of the 18 PMOS transistor (M16) is connected the 19 jointly with drain electrodeThe source electrode of PMOS transistor (M17), the grid of the 19 PMOS transistor (M17) is connected the 20 jointly with drain electrodeThe source electrode of PMOS transistor (M18), the grid of the 20 PMOS transistor (M18) and drain electrode are jointly connected second etc.Effect resistance (Rf2).
6. the LDO circuit that is applicable to the low quiescent current of power management and drives heavy load according to claim 4, itsBe characterised in that, described the second equivalent resistance (Rf2) includes the 21 PMOS transistor (M19), the 22PMOS transistor (M20) and the 23 PMOS transistor (M21), wherein, the 21 PMOS transistor (M19)Source electrode connect the first equivalent resistance (Rf1), the grid of the 21 PMOS transistor (M19) and drain electrode are jointly connected theThe source electrode of 22 PMOS transistors (M20), the grid of the 22 PMOS transistor (M20) and drain electrode connect jointlyConnect the source electrode of the 23 PMOS transistor (M21), the grid of the 23 PMOS transistor (M21) and drain electrode are altogetherSame ground connection.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201521138924.4U CN205263698U (en) | 2015-12-29 | 2015-12-29 | LDO circuit of low quiescent current and drive heavy load suitable for power management |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201521138924.4U CN205263698U (en) | 2015-12-29 | 2015-12-29 | LDO circuit of low quiescent current and drive heavy load suitable for power management |
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| CN205263698U true CN205263698U (en) | 2016-05-25 |
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| CN201521138924.4U Withdrawn - After Issue CN205263698U (en) | 2015-12-29 | 2015-12-29 | LDO circuit of low quiescent current and drive heavy load suitable for power management |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105468082A (en) * | 2015-12-29 | 2016-04-06 | 天津大学 | Low-quiescent-current and large-load-driving LDO circuit suitable for power supply management |
| CN107863129A (en) * | 2016-09-22 | 2018-03-30 | 中芯国际集成电路制造(上海)有限公司 | A kind of circuit and the method being programmed using the circuit to electrically programmable fuse circuit |
| CN109327198A (en) * | 2017-07-31 | 2019-02-12 | 哈曼国际工业有限公司 | More collapsible cascodes of feedback control loop instrument |
| CN112542956A (en) * | 2020-12-08 | 2021-03-23 | 东南大学 | Wide dynamic range self-biased differential drive rectifier circuit |
-
2015
- 2015-12-29 CN CN201521138924.4U patent/CN205263698U/en not_active Withdrawn - After Issue
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105468082A (en) * | 2015-12-29 | 2016-04-06 | 天津大学 | Low-quiescent-current and large-load-driving LDO circuit suitable for power supply management |
| CN105468082B (en) * | 2015-12-29 | 2017-05-10 | 天津大学 | Low-quiescent-current and large-load-driving LDO circuit suitable for power supply management |
| CN107863129A (en) * | 2016-09-22 | 2018-03-30 | 中芯国际集成电路制造(上海)有限公司 | A kind of circuit and the method being programmed using the circuit to electrically programmable fuse circuit |
| CN107863129B (en) * | 2016-09-22 | 2020-09-29 | 中芯国际集成电路制造(上海)有限公司 | Circuit and method for programming electrically programmable fuse circuit by using same |
| CN109327198A (en) * | 2017-07-31 | 2019-02-12 | 哈曼国际工业有限公司 | More collapsible cascodes of feedback control loop instrument |
| CN109327198B (en) * | 2017-07-31 | 2023-09-19 | 哈曼国际工业有限公司 | Multi-feedback loop instrument folding type gate-cathode amplifier |
| CN112542956A (en) * | 2020-12-08 | 2021-03-23 | 东南大学 | Wide dynamic range self-biased differential drive rectifier circuit |
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Granted publication date: 20160525 Effective date of abandoning: 20170510 |
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