CN201936213U - Low tension voltage stabilizer - Google Patents

Abstract

The utility model discloses a low tension voltage stabilizer which introduces an appended zero pole into a low tension voltage stabilizing circuit so as to improve the stability of the low tension voltage stabilizing circuit, specifically a feedback loop formed by connecting a compensation capacitor and a compensation resistor in series can be accessed between the grid leak poles of a PMOS (p-channel metal oxide semiconductor) drive pipe, the value of the compensation capacitor and the compensation resistor is set, a second main pole of the voltage stabilizer is lowered with low voltage by the appended zero point generated by a compensation circuit, simultaneously the appended pole brought by the added compensation circuit is compensated by the zero point generated by the capacitance output by the low tension voltage stabilizer circuit, the phase margin of the circuit is improved, better stability of the low tension voltage stabilizer circuit can be realized, and the output end is not oscillated.

Description

Low dropout voltage regulator

Technical field

The utility model belongs to the low-pressure drop voltage-stabilizing circuit field, is specifically related to a kind of low dropout voltage regulator.

Background technology

In low dropout (LDO) regulator circuit design, loop stability be a part and parcel.Fig. 1 is the structural representation of existing low dropout (LDO) regulator circuit.Referring to Fig. 1, low dropout (LDO) regulator circuit 10 is mainly by error amplifier circuit 100, and PMOS driving tube 110 and resistance-feedback network 120 constitute.The positive input of error amplifier circuit 100 meets input reference voltage Vref, the grid G of the output termination PMOS driving tube 110 of error amplifier circuit 100, and, input reference voltage Vref is produced by bandgap voltage reference circuit.The output of PMOS driving tube 110 drain D by resistance-feedback network 120 first resistance R 1 and second resistance R, 2 dividing potential drops after feed back to the reverse input end of error amplifier circuit 100.Be connected to the output capacitance Co that falls stabilizer output voltage in order to stabilizing low voltage at output point Vout.Resr is the equivalent series resistance of output capacitance Co, and Iload is the load current of circuit.

Fig. 2 is the small-signal model figure of low dropout (LDO) regulator circuit shown in Figure 1.Wherein Roa is the output impedance of error amplifier circuit 100, and Cgs is the grid source capacitance of PMOS driving tube, and Cgd is the grid leak electrode capacitance of PMOS driving tube.GmVgs is the current source of the gate source voltage Vgs control of PMOS driving tube, r ₀Output impedance for the PMOS driving tube.The small-signal model of low dropout (LDO) regulator circuit shown in Figure 2 is carried out zero limit analysis as can be known, and the value of its output capacitance Co is the stray capacitance on error amplifier circuit 100 output points generally, so this point is output dominant pole P1 usually.The angular frequency of output dominant pole P1 _P1For:

${\mathrm{\&omega;}}_{\mathrm{<figure-callout\; id="1"\; label="P"\; filenames="HDA0000041593670000011.png"\; state="\{\{state\}\}">P</figure-callout>}1}=\frac{1}{r_0{C}_0}---\left(1\right)$

Wherein: r ₀Be the output impedance of stablizing the PMOS driving tube of loop.

The second dominant pole P2 is positioned at the output terminal of error amplifier circuit 100, and by the output impedance Roa of error amplifier circuit 100, the grid source capacitor C gs of PMOS driving tube 110 and the shunt capacitance of gate leakage capacitance Cgd obtain.The angular frequency of the second dominant pole P2 _P2For:

${\mathrm{\&omega;}}_{P2}\&ap;\frac{1}{R_{\mathrm{oa}}(C_{\mathrm{gs}}+C_{\mathrm{gd}})}---\left(2\right)$

Because there is equivalent series resistance Resr in output capacitance Co, circuit can exist one zero point Z1.Zero point Z1 angular frequency _Z1For:

${\mathrm{\&omega;}}_{\mathrm{<figure-callout\; id="1"\; label="Z"\; filenames="HDA0000041593670000011.png"\; state="\{\{state\}\}">Z</figure-callout>}1}=\frac{1}{R_{\mathrm{esr}}{C}_0}---\left(3\right)$

Fig. 3 is the amplitude-versus-frequency curve figure of low dropout (LDO) regulator circuit shown in Figure 1.As shown in Figure 3,90 degree phase shifted cancellation that zero point, Z1 brought the negative 90 degree phase shifts that bring of the second dominant pole P2, this shows, as long as it is stable preferably to make the unity gain bandwidth of voltage stabilizer less than the 3rd dominant pole P3 loop be had.

More than analyze and supposed that the frequency of Z1 at zero point is lower than the frequency of the second dominant pole P2, or the frequency of the two is mutually close, because the influence that the positive phase shifted cancellation second dominant pole P2 negative of Z1 at zero point is moved.But in some practical applications, often require the output capacitance Co value of low dropout (LDO) regulator circuit less, because output capacitance Co adopts ceramic disc capacitor usually, the variation of its capacitance and resistance value is subjected to the influence of flow-route and temperature very big, in particular, the value of output capacitance Co and equivalent series resistance Resr thereof can be very little under some situation, thereby make that the angular frequency of Z1 at zero point is very high, and Fig. 4 promptly is that low dropout (LDO) regulator circuit shown in Figure 1 is in the angular frequency at zero point _Z1Amplitude-versus-frequency curve figure when too high.In this case, Z1 can't compensate the phase shift of the second dominant pole P2 at zero point, and the stability of low dropout (LDO) regulator circuit shows as variation stabilizer output voltage and vibration can occur, makes the circuit cisco unity malfunction.

Summary of the invention

In order to solve the technical matters that exists in the background technology, the utility model provides a kind of low dropout voltage regulator, the phase margin that it has improved low-pressure drop voltage-stabilizing circuit can not vibrated its output terminal, thereby can guarantee that low-pressure drop voltage-stabilizing circuit has advantages of higher stability.

Technical solution of the present utility model is as follows:

A kind of low dropout voltage regulator comprises error amplifier circuit 100, and the positive input of this error amplifier circuit 100 meets input reference voltage Vref, the output terminal of its reverse input end connecting resistance feedback network 120, the grid G of its output termination PMOS driving tube 110; The source S of described PMOS driving tube 110 meets supply voltage VDD, and its drain D meets the output end vo ut of low dropout voltage regulator; One termination power voltage VDD of described resistance-feedback network 120, other end ground connection, the reverse input end of the output termination error amplifier circuit 100 of this resistance-feedback network 120; Its special character is: be connected to backfeed loop 130 between the drain D of described PMOS driving tube 110 and the grid G, this backfeed loop 130 is to comprise the compensating resistance Rc that is in series and the RC backfeed loop of building-out capacitor Cc.

Above-described compensating resistance Rc and building-out capacitor Cc are advisable to satisfy following condition:

(i) angular frequency of the second dominant pole P2 _P2Be substantially equal to the angular frequency of additional zero Zc _Zc:

$\frac{1}{C_c{R}_c}\&Proportional;\frac{1}{R_{\mathrm{oa}}(C_c+C_{\mathrm{gs}}+C_{\mathrm{gd}})},$

The (ii) angular frequency of additional pole Pc _PcBe substantially equal to the angular frequency of Z1 at zero point _Z1:

$\frac{1}{R_c(C_c//C_{\mathrm{gs}})}\&Proportional;\frac{1}{R_{\mathrm{esr}}{C}_o},$

Wherein: Cc is the building-out capacitor of backfeed loop 130, Rc is the compensating resistance of backfeed loop 130, Roa is the output impedance of error amplifier circuit 100, Cgs is the grid source capacitance of PMOS driving tube, Cgd is the grid leak electrode capacitance of PMOS driving tube, Co is an output capacitance, and Resr is the equivalent series resistance of output capacitance Co.

Above-described compensating resistance Rc and building-out capacitor Cc are to satisfy following condition for the most desirable:

(i) angular frequency of the second dominant pole P2 _P2Angular frequency with additional zero Zc _ZcEquate:

$\frac{1}{C_c{R}_c}=\frac{1}{R_{\mathrm{oa}}(C_c+C_{\mathrm{gs}}+C_{\mathrm{gd}})},$

The (ii) angular frequency of additional pole Pc _PcAngular frequency with Z1 at zero point _Z1Equate:

$\frac{1}{R_c(C_c//C_{\mathrm{gs}})}=\frac{1}{R_{\mathrm{esr}}{C}_o}.$

Above-described resistance-feedback network 120 generally can adopt first resistance R 1 and second resistance R 2 that are in series to constitute.

Advantage of the present utility model is as follows:

Stability is high.The utility model angular frequency is ω _ZcAdditional zero Zc offset angle frequency be ω _P2The second dominant pole P2, the angular frequency that produces with output capacitance Co is ω _Z1Z1 offset angle frequency at zero point be ω _PcAdditional pole Pc, improved the phase margin of low-pressure drop voltage-stabilizing circuit, its output terminal can not vibrated, thereby can guarantee that low-pressure drop voltage-stabilizing circuit has advantages of higher stability.

Implementation is simple.The utility model only need add components and parts seldom in low dropout (LDO) regulator circuit, simple in structure, is easy to realize.

Circuit power consumption is relatively low.Because the added components and parts of the utility model are passive device, therefore, it realizes can not increasing the power consumption of low dropout (LDO) regulator circuit.

Description of drawings

Fig. 1 is the structural representation of existing low dropout (LDO) regulator circuit;

Fig. 2 is the small-signal analysis illustraton of model of existing low dropout (LDO) regulator circuit;

Fig. 3 is the amplitude-versus-frequency curve figure of existing low dropout (LDO) regulator circuit shown in Figure 1;

Fig. 4 is the amplitude-versus-frequency curve figure of existing low dropout (LDO) regulator circuit shown in Figure 1 under the too high situation of angular frequency at zero point;

Fig. 5 is a circuit structure principle schematic of the present utility model;

Fig. 6 is a small-signal analysis illustraton of model of the present utility model;

Fig. 7 is that the utility model adopts the RC feedback to carry out the amplitude-versus-frequency curve figure of zero compensation.

The explanation of accompanying drawing drawing:

The 10-low dropout (LDO) regulator circuit, 100-error amplifier circuit, 110-driving tube, 120-resistance-feedback network, 130-backfeed loop; The Rc-compensating resistance, Cc-building-out capacitor, the output impedance of the error amplifier of Roa-low dropout voltage regulator, the grid source capacitance of Cgs PMOS driving tube, the grid leak electrode capacitance of Cgd-PMOS driving tube, r ₀The output impedance of the PMOS driving tube of-low dropout voltage regulator, the output capacitance of Co-low dropout voltage regulator, the equivalent series resistance of the output capacitance Co of Resr-low dropout voltage regulator, R1-first resistance, R2-second resistance.

Embodiment

The utility model is introduced additional zero Zc and additional pole Pc in low dropout (LDO) regulator circuit, utilize additional zero Zc and additional pole Pc to improve the stability of low dropout (LDO) regulator circuit, specifically can between the grid G of PMOS driving tube and drain D, insert the backfeed loop that constitutes by building-out capacitor Cc and compensating resistance Rc series connection, the value of design compensation capacitor C c and compensating resistance Rc makes the angular frequency of the additional zero Zc that building-out capacitor Cc and compensating resistance Rc produced _ZcBe substantially equal to the angular frequency of the second dominant pole P2 of low dropout (LDO) regulator circuit self _P2, make the angular frequency of the additional pole Pc that the loop produced of the grid leak electrode capacitance Cgd of building-out capacitor Cc, compensating resistance Rc and PMOS driving tube simultaneously _PcBe substantially equal to low dropout (LDO) regulator circuit zero point Z1 angular frequency _Z1Thereby, make the angular frequency of the second dominant pole P2 of low dropout (LDO) regulator circuit self _P2By the angular frequency of additional zero Zc _ZcCompensation, the angular frequency of additional pole Pc _PcBy the external output capacitance of circuit zero point Z1 angular frequency _Z1Compensate, then the phase margin of circuit improves, low dropout (LDO) regulator circuit can be realized preferably stability, its output terminal can not vibrate.

Referring to Fig. 5, low dropout voltage regulator of the present utility model is to have added the RC backfeed loop that compensating resistance Rc and building-out capacitor Cc are in series and constitute between the drain D of the PMOS of existing low dropout (LDO) regulator circuit shown in Figure 1 driving tube 110 and grid G.The positive input of error amplifier circuit 100 meets input reference voltage Vref, the output terminal of its reverse input end connecting resistance feedback network 120, the grid G of its output termination PMOS driving tube 110.The source S of PMOS driving tube 110 meets supply voltage VDD, and its drain D is the output end vo ut of low dropout (LDO) regulator circuit.One termination power voltage VDD of resistance-feedback network 120, other end ground connection, the reverse input end of the output termination error amplifier circuit 100 of this resistance-feedback network 120.Resistance-feedback network 120 is made of first resistance R 1 that is in series and second resistance R 2.The input end of resistance-feedback network 120 is ends of second resistance R 2, and the other end of second resistance R 2 and first resistance R 1 are joined, and the end that second resistance R 2 and first resistance R 1 are joined is the output terminal of resistance-feedback network 120, the other end ground connection of first resistance R 1.

The value of compensating resistance Rc and building-out capacitor Cc is advisable to satisfy following condition:

(i) angular frequency of the second dominant pole P2 _P2Be substantially equal to the angular frequency of additional zero Zc _Zc:

$\frac{1}{C_c{R}_c}\&Proportional;\frac{1}{R_{\mathrm{oa}}(C_c+C_{\mathrm{gs}}+C_{\mathrm{gd}})},$

The (ii) angular frequency of additional pole Pc _PcBe substantially equal to the angular frequency of Z1 at zero point _Z1:

$\frac{1}{R_c(C_c//C_{\mathrm{gs}})}\&Proportional;\frac{1}{R_{\mathrm{esr}}{C}_o}.$

The value of compensating resistance Rc and building-out capacitor Cc is the best to satisfy following condition:

(i) angular frequency of the second dominant pole P2 _P2Angular frequency with additional zero Zc _ZcEquate:

$\frac{1}{C_c{R}_c}=\frac{1}{R_{\mathrm{oa}}(C_c+C_{\mathrm{gs}}+C_{\mathrm{gd}})},$

The (ii) angular frequency of additional pole Pc _PcAngular frequency with Z1 at zero point _Z1Equate:

$\frac{1}{R_c(C_c//C_{\mathrm{gs}})}=\frac{1}{R_{\mathrm{esr}}{C}_o}.$

Referring to figure Fig. 6, it is the small-signal model figure of low dropout (LDO) regulator circuit shown in Figure 5, and wherein Roa is the output impedance of error amplifier 100, and Cgs is the grid source electric capacity of PMOS driving tube, and Cgd is the gate leakage capacitance of PMOS driving tube.GmVgs is the current source of gate pmos source voltage Vgs control, r ₀Output impedance for the PMOS driving tube.

Usually, the electric current that PMOS driving tube 110 flows through is bigger, and its output impedance r0 will be much larger than the loaded impedance RL of low dropout (LDO) regulator circuit.And, because output capacitance Co is generally nF or uF rank, the stray capacitance of low dropout (LDO) regulator circuit inside (Cgs, Cgd etc.) is generally the pF rank, so the output capacitance Co of low dropout voltage regulator will be much larger than the internal capacitance of low dropout voltage regulator, the output limit is dominant pole P1.Analyze the angular frequency of the dominant pole P1 that obtains low dropout (LDO) regulator circuit thus _P1For:

${\mathrm{\&omega;}}_{\mathrm{<figure-callout\; id="1"\; label="p"\; filenames="HDA0000041593670000011.png"\; state="\{\{state\}\}">p</figure-callout>}1}=\frac{1}{R_{\mathrm{oa}}[(1+g_m{r}_0)(C_c+C_{\mathrm{gd}})+C_{\mathrm{gs}}]+r_0(C_c+C_{\mathrm{gd}}+C_0)}\&ap;\frac{1}{r_0{C}_0}---\left(4\right)$

The angular frequency of the second dominant pole P2 _P2For:

${\mathrm{\&omega;}}_{p2}=\frac{R_{\mathrm{oa}}[(1+g_m{r}_o)(C_c+C_{\mathrm{gd}})+C_{\mathrm{gs}}]+r_0(C_c+C_{\mathrm{gd}}+C_o)}{R_{\mathrm{oa}}{r}_0[(C_c+C_{\mathrm{gd}})C_{\mathrm{gs}}+(C_c+C_{\mathrm{gd}})C_o+C_{\mathrm{gs}}{C}_o]}\&ap;\frac{1}{R_{\mathrm{oa}}(C_c+C_{\mathrm{gs}}+C_{\mathrm{gd}})}---\left(5\right)$

Output capacitance Co goes up that series equivalent resistance produces zero point Z1 angular frequency _Z1For:

${\mathrm{\&omega;}}_{z1}\&ap;\frac{1}{R_{\mathrm{esr}}{C}_o}---\left(6\right)$

The backfeed loop that compensating resistance Rc that the utility model adds between the grid leak utmost point of the PMOS of low dropout (LDO) regulator circuit driving tube and building-out capacitor Cc form, the angular frequency of the additional zero Zc that it produced _ZcFor:

${\mathrm{\&omega;}}_{\mathrm{zc}}\&ap;\frac{1}{C_c{R}_c}---\left(7\right)$

Grid G, the transition function between the drain D of PMOS driving tube are:

$H\left(s\right)\&ap;\frac{(R_c+\frac{1}{s{C}_c})\frac{1}{{\mathrm{sC}}_{\mathrm{gd}}}}{R_c+\frac{1}{{\mathrm{sC}}_c}+\frac{1}{{\mathrm{sC}}_{\mathrm{gd}}}}---\left(8\right)$

(8) in the formula, promptly be the additional zero Zc that is produced by compensating resistance Rc and building-out capacitor Cc the zero point that is obtained by molecule, and by denominator obtain limit be the additional pole that the grid source capacitance Cgs by compensating resistance Rc, building-out capacitor Cc and PMOS driving tube is produced, the angular frequency of this additional pole _PcFor

${\mathrm{\&omega;}}_{\mathrm{pc}}\&ap;\frac{1}{R_c(C_c//C_{\mathrm{gs}})}---\left(9\right)$

In the circuit analysis of above-mentioned institute, very little or output capacitance Co goes up the equivalent resistance Resr of series connection when very little as external output capacitance Co, its generation zero point Z1 angular frequency _Z1Angular frequency much larger than the second dominant pole P2 of system _P2By the compensating resistance Rc and the building-out capacitor Cc in rational design of feedback loop, the angular frequency of the additional zero Zc that produces with backfeed loop _ZcCompensate the angular frequency of the second dominant pole P2, make the angular frequency of the limit of backfeed loop generation _PcBe output electric capacity zero point Z1 angular frequency _Z1Compensate, that is, make the angular frequency of the second dominant pole P2 _P2Be substantially equal to the angular frequency of additional zero Zc _Zc, the angular frequency of additional pole Pc _PcBe substantially equal to the angular frequency of Z1 at zero point _Z1Optimal design is to satisfy following formula:

$\frac{1}{C_c{R}_c}=\frac{1}{R_s(C_c+C_{\mathrm{gs}}+C_{\mathrm{gd}})}---\left(10\right)$

$\frac{1}{R_c(C_c//C_{\mathrm{gs}})}=\frac{1}{R_{\mathrm{esr}}{C}_o}---\left(11\right)$

Shown in Figure 7 is the amplitude-versus-frequency curve that the utility model satisfies the optimal design of (10) formula, (11) formula, its phase margin that demonstrates low dropout (LDO) regulator circuit improves, thereby can guarantee that its output terminal can not vibrate, therefore make low-pressure drop voltage-stabilizing circuit have advantages of higher stability.

Claims (4)

1. low dropout voltage regulator, comprise error amplifier circuit (100), the positive input of this error amplifier circuit (100) connects input reference voltage (Vref), the output terminal of its reverse input end connecting resistance feedback network (120), the grid (G) of its output termination PMOS driving tube (110); The source electrode (S) of described PMOS driving tube (110) connects supply voltage (VDD), and its drain electrode (D) connects the output terminal (Vout) of low dropout voltage regulator; One termination power voltage (VDD) of described resistance-feedback network (120), other end ground connection, the reverse input end of the output termination error amplifier circuit (100) of this resistance-feedback network (120); It is characterized in that: be connected to backfeed loop (130) between the drain electrode (D) of described PMOS driving tube (110) and the grid (G), this backfeed loop (130) is to comprise the compensating resistance (Rc) that is in series and the RC backfeed loop of building-out capacitor (Cc).

2. low dropout voltage regulator according to claim 1 is characterized in that, described compensating resistance (Rc) and building-out capacitor (Cc) satisfy following condition:

(i) angular frequency of second dominant pole (P2) _P2Be substantially equal to the angular frequency of additional zero (Zc) _Zc:

$\frac{1}{C_c{R}_c}\&Proportional;\frac{1}{R_{\mathrm{oa}}(C_c+C_{\mathrm{gs}}+C_{\mathrm{gd}})},$

The (ii) angular frequency of additional pole (Pc) _PcBe substantially equal to the angular frequency of zero point (Z1) _Z1:

$\frac{1}{R_c(C_c//C_{\mathrm{gs}})}\&Proportional;\frac{1}{R_{\mathrm{esr}}{C}_o},$

Wherein: Cc is the building-out capacitor of backfeed loop (130), Rc is the compensating resistance of backfeed loop (130), Roa is the output impedance of error amplifier circuit (100), Cgs is the grid source capacitance of PMOS driving tube, Cgd is the grid leak electrode capacitance of PMOS driving tube, Co is an output capacitance, and Resr is the equivalent series resistance of output capacitance (Co).

3. low dropout voltage regulator according to claim 1 and 2 is characterized in that: described compensating resistance (Rc) and building-out capacitor (Cc) satisfy following condition:

(i) angular frequency of second dominant pole (P2) _P2Angular frequency with additional zero (Zc) _ZcEquate:

$\frac{1}{C_c{R}_c}=\frac{1}{R_{\mathrm{oa}}(C_c+C_{\mathrm{gs}}+C_{\mathrm{gd}})},$

The (ii) angular frequency of additional pole (Pc) _PcAngular frequency with zero point (Z1) _Z1Equate:

$\frac{1}{R_c(C_c//C_{\mathrm{gs}})}=\frac{1}{R_{\mathrm{esr}}{C}_o}.$

4. low dropout voltage regulator according to claim 3 is characterized in that: described resistance-feedback network (120) comprises first resistance (R1) and second resistance (R2) that is in series.

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