CN102830741A - Dual-loop low dropout regulator - Google Patents

Abstract

The invention discloses a dual-loop low dropout regulator, which comprises a first loop and a second loop, wherein the first loop is a three-level amplifier formed by a first amplifier stage, a second amplifier stage, a third amplifier stage, a first compensation network and a second compensation network, and a second loop is a three-level amplifier formed by a second amplifier stage, a fourth amplifier stage, a fifth amplifier stage and a third compensation network. According to the invention, a constant-voltage output of the LDO (Low Dropout Regulator) is controlled by the first loop, an output current of LDO is limited by the second loop so as to prevent the output current from exceeding an over-current point when an over-current condition appears, and the second compensation network and the output port of the LDO are externally connected with a load capacitor, so that a pseudo ESR (Equivalent Series Resistance) zero setting compensation network is integrated in the first loop, and the frequency compensation of the first loop is realized; and meanwhile, the second amplifier stage of the second loop and the second amplifier stage of the first loop are shared, so that the conventional dual-loop LDO circuit is simplified, and the area and the consumption of a chip are reduced.

Description

The double loop low pressure difference linear voltage regulator

Technical field

The invention belongs to the power management techniques field, be specifically related to the design of a kind of low pressure difference linear voltage regulator (LDO, Low Dropout Regulator).

Background technology

Along with the development of integrated circuit to SoC (System on Chip) direction, PMU progressively is integrated into chip internal, and is playing the part of important role.Low pressure difference linear voltage regulator is as an important kind in the power management module, owing to providing low noise, high-precision stable power-supplying voltage to be widely used can for the analog module of noise-sensitive.

Aspect the LDO reliability; The factor such as limited, the LDO overload of foundation, power supply power supply capacity owing to power on; LDO is in astable duty through regular meeting, problems can occur for these reasons: (1) is set up in the process at LDO, and loop negative feedback mechanism is impelled the externally big electric current of output of power tube; Therefore the LDO supply module might be dragged down, and causes other module inefficacy in the system; (2) in LDO output short-circuit or when overload,, output current is excessive, causes the LDO temperature to raise until burning.

In the problem that unsteady state occurs, adopt overheat protector and current foldback circuit to solve the problems referred to above to above-mentioned LDO usually.Traditional overcurrent protection is designed with three kinds, and a kind of is to adopt comparer detection power pipe whether to export overcurrent, behind overcurrent, directly power tube is turn-offed, and the shortcoming of sort circuit is that the circuit overcurrent returns to the long time of normal need; Second kind is the electric current limit of turning back, and the output current behind the overcurrent is limited in a less value, neither has very big power consumption; Do not need the long period can make circuit be transformed into operate as normal from overcurrent yet; But its shortcoming is the turn back cut-off current of electric current limit to be in the LDO operate as normal output current scope, and electric current limit loop was difficult for withdrawing from when fault was eliminated, and caused the LDO cisco unity malfunction; And the electric current limit of turning back has extra current limliting loop and big adjustment pipe usually, increased chip area; The third is constant current-limiting circuit; When sort circuit occurs in the overcurrent condition; Output current is limited in the mistake flow point of setting, and traditional method is to adopt the constant current loop that is independent of the constant voltage loop to come the output current of monitor power pipe, when the overcurrent occurrence condition is set up; It is the constant current value that is provided with that the power controlling pipe makes output current; Such as level and smooth peak electricity ductility limit technology, but often adopt the mode of logic control between constant voltage loop independent of each other and constant current loop, to switch, extra adjustment pipe has increased chip area in control complicacy and the constant current loop.

Aspect the LDO stability Design; The LDO of electric capacity compensation utilizes equivalent series resistance (Equivalent Series Resistance, ESR) the effective traditional method that zero point, realization compensated of generation, the peak of increase output transient response of plug-in load capacitance outside the employing sheet; And ESR can fluctuate; Discreteness is very big, and the ESR that needs is bigger, is difficult to realize.

Summary of the invention

The objective of the invention is to the present invention proposes a kind of double loop low pressure difference linear voltage regulator in order to solve the problems referred to above that existing LDO exists.

Technical scheme of the present invention: a kind of double loop low pressure difference linear voltage regulator; Specifically comprise: first loop and second loop; Wherein, First loop is the third stage amplifier that is made up of first amplifier stage, second amplifier stage, the 3rd amplifier stage, first corrective network and second corrective network, and second loop is the third stage amplifier that is made up of second amplifier stage, the 4th amplifier stage, the 5th amplifier stage and the 3rd corrective network;

The positive input of described first amplifier stage connects the input end of outside reference voltage source as the reference voltage source signal of said linear voltage regulator; The negative input of first amplifier stage links to each other with the 4th end of second corrective network; The output terminal of first amplifier stage links to each other with first negative input of second amplifier stage, first end of first corrective network, and the offset side of first amplifier stage is the offset signal input end; Second negative input of described second amplifier stage links to each other with second end of the output terminal of the 5th amplifier stage, the 3rd corrective network; The output terminal of second amplifier stage links to each other with second end of first corrective network, the first input end of the 4th amplifier stage, first end of second corrective network, the input end of the 3rd amplifier stage, and the offset side of second amplifier stage is the offset signal input end; Second end of the output terminal of described the 3rd amplifier stage, second corrective network, second input end of the 4th amplifier stage connect the output terminal as said LDO, and the feedback end of the 3rd amplifier stage is connected as said LDO output end voltage feedback end with the 3rd end of second corrective network.First output terminal of said the 4th amplifier stage links to each other with first end of the 3rd corrective network, and second output terminal of the 4th amplifier stage links to each other with the 4th end of the 3rd corrective network; The negative input of described the 5th amplifier stage links to each other with the 3rd end of the 3rd corrective network, and the offset side of the 5th amplifier stage is the offset signal input end.

Beneficial effect of the present invention:

1, double loop LDO of the present invention; First loop control LDO constant voltage by first amplifier stage, second amplifier stage, the 3rd amplifier stage, first corrective network and second corrective network constitute is together exported; The output current of second loop restriction LDO that constitutes by second amplifier stage, the 4th amplifier stage, the 5th amplifier stage and the 3rd corrective network; Avoid that output current surpassed flow point when the overcurrent condition occurs; And second corrective network realizes that with LDO output port external load electric capacity pseudo-ESR zeroing corrective network is integrated in first loop, has realized the compensation of first frequency loop.

2, the minimum input voltage of the LDO work of the present invention's proposition is 5.5V, uses the external load electric capacity of 2uF to carry out emulation, and LDO of the present invention can drive the electric current of 15mA and only need the quiescent current of 50uA.Under light, heavy duty; The phase margin minimum of LDO first loop proposed by the invention is 47.6 °; Can guarantee system stability, simultaneously unity gain bandwidth is respectively 93.68KHz and 5.23MHz when light, heavy duty, and the LDO that the present invention designed; Have in limited time in the power supply power supply capacity, can stablize in the time at 500us and set up.

3, when the overcurrent condition occurs; The LDO that the present invention proposes limits external output current amplitude through second loop; Solve the temperature rise that over-current phenomenon avoidance causes, burn, power supply such as is dragged down at problem; Simultaneously second loop, second amplifier stage and first loop, second amplifier stage are shared has simplified traditional double loop LDO circuit, has reduced chip area and power consumption.The pseudo-ESR structure of LDO of the present invention replaces the ESR of the output capacitance in the traditional scheme; Solve traditional scheme ESR and can increase the peak that exports transient response; And ESR can fluctuate, the big problem of discreteness, and circuit contains pseudo-ESR structure; On the zero limit characteristic of system, have the effect identical, and the power consumption almost of extra increase is zero with external ESR.

Description of drawings

The LDO structural representation that Fig. 1 proposes for the present invention.

Fig. 2 is the integrated circuit structural representation of the LDO of the present invention's proposition.

Fig. 3 is the small-signal equivalent circuit synoptic diagram of error amplifier ERROR_AMP.

Fig. 4 is the first loop small-signal equivalent circuit synoptic diagram of LDO.

Fig. 5 is the second loop small-signal equivalent circuit synoptic diagram of LDO.

Fig. 6 is first frequency loop response synoptic diagram of LDO of the present invention.

Fig. 7 is the whole pictorial diagram of the load transient response of LDO of the present invention.

Fig. 8 is the process of setting up and the output current pictorial diagram of LDO.

Embodiment

Below in conjunction with accompanying drawing and specific embodiment the present invention is done further explanation.

As shown in Figure 1, double loop LDO circuit of the present invention specifically comprises: first loop and second loop.First loop is the third stage amplifier that is made up of the first amplifier stage AMP1, the second amplifier stage AMP2, the 3rd amplifier stage AMP3, the first corrective network CPNET1 and the second corrective network CPNET2; Wherein, AMP1, AMP2 and CPNET1 constitute error amplifier ERROR_AMP.Second loop is the third stage amplifier that is made up of the second amplifier stage AMP2, the 4th amplifier stage AMP4, the 5th amplifier stage AMP5 and the 3rd corrective network CPNET3.

Concrete annexation is: the positive input of the said first amplifier stage AMP1 connects the input end of outside reference voltage source VREF as the reference voltage source signal of said linear voltage regulator; The negative input of the first amplifier stage AMP1 links to each other with the 4th end of the second corrective network CPNET2; The output terminal of the first amplifier stage AMP1 links to each other with first negative input of the second amplifier stage AMP2, first end of the first corrective network CPNET1, and the offset side of the first amplifier stage AMP1 is used to import the first outside offset signal VB1 and links to each other; Second negative input of the described second amplifier stage AMP2 links to each other with second end of the output terminal of the 5th amplifier stage AMP5, the 3rd corrective network CPNET3; The output terminal of the second amplifier stage AMP2 links to each other with second end of the first corrective network CPNET1, the first input end of the 4th amplifier stage AMP4, first end of the second corrective network CPNET2, the input end of the 3rd amplifier stage AMP3, the offset side of AMP2 be used to import the second outside offset signal VB2 and link to each other; Second input end of second end of the output terminal of said the 3rd amplifier stage AMP3, the second corrective network CPNET2, the 4th amplifier stage AMP4 connects the output terminal as said LDO, and the feedback end of the 3rd amplifier stage AMP3 is connected as said LDO output end voltage feedback end with the 3rd end of the second corrective network CPNET2; First output terminal of said the 4th amplifier stage AMP4 links to each other with first end of the 3rd corrective network CPNET3, and the AMP4 second output terminal end of the 4th amplifier stage links to each other with the 4th end of the 3rd corrective network CPNET3; The negative input of said the 5th amplifier stage AMP5 links to each other with the 3rd end of the 3rd corrective network CPNET3, and the offset side of the 5th amplifier stage is used to import the 3rd outside offset signal VB3 and links to each other.

The offset signal VB1 here, VB2 and VB3 are separate, can select according to actual needs.

Fig. 2 has provided a kind of practical implementation figure of said structure, wherein:

The first amplifier stage AMP1 by PMOS manage MP1, MP4, MP5, NMOS pipe MN1, MN2 constitutes; Wherein, the grid of MP1 is as AMP1 offset side input offset signal VB1, and the source electrode of MP1 meets external power source VDD; The grid of MP4 pipe is as the positive input of AMP1; The source electrode of MP4 links to each other with the drain electrode of the source electrode of MP5, MP1 pipe, and the drain electrode of MP4, the grid of MN1 and drain electrode link to each other with the grid of MN2, and the grid of MP5 is the negative input of AMP1; The drain electrode of MP5 links to each other as the AMP1 output terminal with the drain electrode of MN2, the source electrode of MN1 and the source grounding of MN2.

The second amplifier stage AMP2 by PMOS manage MP3, NMOS pipe MN3 pipe, the MN4 pipe constitutes, wherein, the grid of MP3 is the AMP2 offset side; VB2 links to each other with offset signal; The drain electrode of MP3 links to each other as the output terminal of AMP2 with the drain electrode of MN3, and the grid of MN3 is as first negative input of AMP2, and the source electrode of MN3 links to each other with the drain electrode of MN4; The grid of MN4 is as second negative input of AMP2, the source ground of MN4.

The 3rd amplifier stage AMP3 manages MP11, resistance R 8, R9 by PMOS and constitutes; Wherein, The grid of MP11 is as the input end of AMP3, and the drain electrode of MP11 links to each other as the output terminal of AMP3 with first end of R8, and second end of R8 links to each other as the feedback end of AMP3 with first end of R9; The second end ground connection of R9, the source electrode of MP11 all is connected to external power source VDD.

The first corrective network CPNET1 is made up of resistance R 1 and capacitor C 1, and wherein, first end of R1 is as first end of CPNET1, and second end of R1 links to each other with first end of C1, and second end of C1 is second end of CPNET1.

The second corrective network CPNET2 manages MP10 by PMOS, and resistance R 6, R7 and C4 constitute, wherein; The grid of MP10 is first end of CPNET2; The drain electrode of MP10 links to each other with first end of R7, first end of C4, and the source electrode of MP10 meets external power source VDD, and second end of R7 is second end of CPNET2; Second end of R6 is the 3rd end of CPNET2, and second end of C4 and first end of R6 resistance are connected to the 4th end of CPNET2.

The 4th amplifier stage AMP4 manages MP7, MP8, MP9 pipe and resistance R 3, resistance R 5 by PMOS and constitutes, and wherein, the grid of MP7 is as the first input end of AMP4; The drain electrode of MP7 links to each other with the source electrode of MP8, as second output terminal of AMP4; The drain electrode of MP8 links to each other with first end of R3, as first output terminal of AMP4; The grid of MP8 links to each other with the drain electrode of the grid of MP9, MP9, first end of R5, the second end ground connection of R3 and R5, and the source electrode of MP9 is second input end of AMP4.

The 5th amplifier stage AMP5 manages MP2 by PMOS, and NMOS pipe MN5 and resistance R 2 constitute, wherein; The grid of MP2 is the offset side of AMP5; VB3 links to each other with offset signal, and the drain electrode of MP2 links to each other as the output terminal of AMP5 with first end of the drain electrode of MN5, R2, and the grid of MN5 is as the negative input of AMP5; The source electrode of MP2 meets external power source VDD, the equal ground connection of second end of the source electrode of MN5 and R2.

The 3rd corrective network CPNET3 is made up of resistance R 4, capacitor C 2 and C3; Wherein, First end of resistance R 4 is first end of CPNET3, and first end of C3 is second end of CPNET3, and second end of R4, second end of C2 link to each other with second end of C3; Be the 3rd end of CPNET3, first end of C2 is the 4th end of CPNET3.

In first loop; MN1 and MN2 are the mirror image active load of AMP1, and MP4 and MP5 constitute the differential input of AMP1, and the MP3 of AMP2 and MN3 constitute single tube and amplify the buffer level; MP2 and R2 are that MN4 provides gate bias voltage; Make MN4 in LDO constant voltage output procedure, be operated in linear zone, buffer level driving power pipe MP11, resistance R 8 constitutes LDO output potential-divider network and sampling output signal VOUT with R9; Feed back to the positive input of AMP1, PMOS pipe MP10, R7 and capacitor C 4 constitute pseudo-ESR and load capacitance C _LZeroing compensation first loop, C ₄, R ₈And R ₉Constitute phase compensating network, the zero limit size that resistance R 6 control phase corrective networks produce realizes effectively compensation.The whole formation of foregoing circuit first loop is realized constant voltage output during the LDO steady operation.

In second loop, the electric current of MP7 pipe sample-power pipe MP11 converts the sampling voltage signal into through R3, amplifies through MN5 pipe, constant current source capsule MP2 and resistance R 2, makes the output current of buffer level adjustment power tube MP11 through the MN4 pipe; The auxiliary MP7 of MP8, MP9 and R5 realizes accurate current mirror, and C2, MP8 and resistance R 3 constitute phase compensating network, and R4 regulates the size of the zero limit of this phase compensating network generation, realizes effectively compensation, and C3 is a miller compensation electric capacity.The whole formation of foregoing circuit second loop, after the overcurrent condition occurs, the external output current amplitude of restriction LDO, the approximate constant current of realization is exported.

When the LDO output overcurrent, OUT and VOUT node are all lower, and the MP7 in second loop manages the big electric current of sample-power pipe MP11 and the VSAM node potential is raise; Thereby make the MN5 pipe get into the saturation region by cut-off region; AMP4 is operated in magnifying state, makes the MN4 pipe get into the saturation region by the linear zone of constant voltage process, forces first loop to withdraw from loop control; Make AMP2 output voltage OUT regulate the power tube MP11 grid current potential of LDO by the MN4 pipe, the size of current that adjustment MP11 externally provides does

Wherein, R ₃The resistance of expression resistance R 3,

Be the breadth length ratio ratio of MP11 pipe and MP7 pipe, V _{GS (MN5)}Gate source voltage for the MN5 pipe.Can know that by above analysis second loop can be set the higher limit of the external output current of LDO, guarantee that output current is limited to setting value when LDO output overcurrent condition occurs $k\frac{V_{\mathrm{GS}\left(\mathrm{MN}5\right)}}{R_3}.$

The small-signal equivalent circuit of the error amplifier ERROR_AMP of LDO proposed by the invention is as shown in Figure 3, can be considered the general two stage amplifer that has zero-regulator resistor and miller compensation.G among Fig. 3 _M1And g _M2Be respectively the mutual conductance of AMP1 and AMP2, r _Out1And r _Out2Be respectively the output impedance of AMP1 and AMP2, ERROR_AMP exists lower two limits and a zero point, is respectively:

${\mathrm{<figure-callout\; id="1"\; label="p"\; filenames="HDA00002093819600022.png"\; state="\{\{state\}\}">p</figure-callout>}}_1\&cong;\frac{1}{g_{m2}{r}_{\mathrm{out}1}{r}_{\mathrm{out}2}{C}_1}---\left(1\right)$

${\mathrm{<figure-callout\; id="2"\; label="p"\; filenames="HDA00002093819600013.png"\; state="\{\{state\}\}">p</figure-callout>}}_2\&cong;\frac{g_{m2}}{C_{\mathrm{out}2}}---\left(2\right)$

${\mathrm{<figure-callout\; id="1"\; label="z"\; filenames="HDA00002093819600022.png"\; state="\{\{state\}\}">z</figure-callout>}}_1\&cong;\frac{1}{C_1(1/g_{m2}-R_1)}---\left(3\right)$

Wherein, g _M2Be the mutual conductance of MN3 pipe, C ₁Be the appearance value of miller compensation capacitor C 1, R ₁Be the resistance of zero-regulator resistor R1, C _Out2Be OUT node equivalent capacity.

The low-frequency gain of ERROR_AMP is: Av=g _M1r _Out1g _M2r _Out2. (4)

Ignore high frequency zero limit, the transition function of ERROR_AMP can be expressed as:

$H{\left(s\right)}_{\mathrm{EA}}=g_{m1}{r}_{\mathrm{out}1}{g}_{m2}{r}_{\mathrm{out}2}\frac{(1+\frac{s}{z_1})}{(1+\frac{s}{p_1})(1+\frac{s}{p_2})}---\left(5\right)$

The LDO that the present invention proposes is stablizing under the constant voltage output state, because the electric current that the electric current that the MP11 pipe flows through is set less than second loop causes MP7 pipe sampling current less, the last voltage drop of R3 is not enough to opening M N5 pipe.Therefore can remove the AUXIAMP circuit, breaking off the LFB tag line is LFB and LFBA, between LFAB and LFBA, adds ac small signal, carries out the first loop AC signal transition function and calculates.Be connected to load capacitance C at the VOUT port _LAnd resistance R _L, it is as shown in Figure 4 to get equivalent ac small signal circuit.Among Fig. 4, g _M1, g _M2And g _MpBe respectively the mutual conductance of AMP1, AMP2 and power tube MP11, r _Out1, r _Out2And r _oBe respectively output resistance and the VOUT port equivalence output resistance of AMP1 and AMP2, wherein, r _o=r _Mp11|| (R ₈+ R ₉) || R _L, R ₈, R ₉The resistance of representing resistance R 8, R9 respectively.Ignoring high frequency zero limit, is input port with the OUT node, and LFBA is an output port, and its transition function can be expressed as:

$H_1\left(s\right)=\frac{(R_6{R}_8+R_6{R}_9+R_8{R}_9)[{\mathrm{<figure-callout\; id="2"\; label="s"\; filenames="HDA00002093819600013.png"\; state="\{\{state\}\}">s</figure-callout>}}^2\frac{1}{k}{C}_4{C}_L{R}_7+s(1+\frac{R_7}{k{R}_L})C_4]+R_9}{[s(R_6{R}_9+R_6{R}_8+R_8{R}_9)C_4+R_8+R_9](s{C}_L{r}_o+1)}---\left(6\right)$

If

H ₁(s) can be reduced to

$H_1\left(s\right)=\frac{(R_8{R}_9+R_6{R}_8+R_6{R}_9)[{\mathrm{<figure-callout\; id="2"\; label="s"\; filenames="HDA00002093819600013.png"\; state="\{\{state\}\}">s</figure-callout>}}^2\frac{1}{k}{C}_4{C}_L{R}_7+s{C}_4]+R_9}{[s(R_6{R}_9+R_6{R}_8+R_8{R}_9)C_4+R_8+R_9](s{C}_L{r}_o+1)}---\left(7\right)$

If

(m is a constant) and $\frac{R_7}{k}<<\frac{C_4}{C_L}[{\mathrm{MR}}_9+(m+1)R_6],$ H then ₁(s) can be reduced to

$H_1\left(s\right)=\frac{\left\{{\mathrm{sC}}_4\right[{\mathrm{mR}}_9+(m+1)R_6]+1\}(s\frac{1}{k}{C}_L{R}_7+1)}{\left\{\right[{\mathrm{mR}}_9+(m+1)R_6]{\mathrm{sC}}_4+m+1\}(s{C}_L{r}_o+1)}---\left(8\right)$

Zero limit is:

$z_2=\frac{1}{C_4[m{R}_9+(m+1)R_6]}---\left(9\right)$

$z_3=\frac{1}{\frac{1}{k}{C}_L{R}_7}---\left(10\right)$

$p_3=\frac{1}{C_L{r}_o}---\left(11\right)$

$p_4=\frac{1}{C_4(\frac{m}{m+1}{R}_9+R_6)}---\left(12\right)$

H then ₁(s) can be reduced to

$H_1\left(s\right)=\frac{1}{m+1}\&times;\frac{(1+\frac{s}{z_2})(1+\frac{s}{z_3})}{(1+\frac{s}{p_3})(1+\frac{s}{p_4})}---\left(13\right)$

The first loop low-frequency gain of LDO of the present invention is:

Av=g _m1r _out1g _m2r _out2g _mpr _o （14）

The transition function H (s) of first loop _CV=H (s) _EA* H ₁(s) can be expressed as:

$H{\left(s\right)}_{\mathrm{CV}}=g_{m1}{r}_{\mathrm{out}1}{g}_{m2}{r}_{\mathrm{out}2}{g}_{\mathrm{mp}}{r}_o\frac{1}{m+1}\&times;\frac{(1+\frac{s}{z_1})}{(1+\frac{s}{p_1})(1+\frac{s}{p_2})}\&times;\frac{(1+\frac{s}{z_2})(1+\frac{s}{z_3})}{(1+\frac{s}{p_3})(1+\frac{s}{p_4})}---\left(15\right)$

Utilize ESR resistance and load capacitance C outward with traditional sheet _LThe generation zero compensation is compared, and extra left half-plane zero point has been introduced in the internal frequency compensation method that LDO of the present invention adopted

Almost do not have the power consumption equivalence and be the ESR resistance R _ESR=R ₇/ k and C _LAt the zero point that produces, outer ESR resistance of sheet and load capacitance C have been realized need not _LProduce zero compensation, be used for offsetting limit p ₁, embodied the notion of pseudo-ESR.The single order high pass feedback network function of phase compensation is commonly used to optimize the performance of LDO; Such as transient response, PSRR and noise; Resistance R 6, R8, R9 and capacitor C 4 constitute single order high pass phase compensating network; Realize comparing with traditional resistance R 8, R9 and capacitor C 4 only utilized, introduce resistance R 6 and reduced the area that resistance takies, zero point z ₁Be used for offsetting p ₂Limit, thus make first loop stability.

The LDO that the present invention proposes is under the overcurrent condition, and VOUT and OUT node voltage are lower, and potential-divider network feedback voltage LFB node voltage is less than the VREF magnitude of voltage, and the output of the first order of ERROR_AMP is forced the MN3 tube grid to draw high.Remove the first order of ERROR_AMP, ignore the effect of MN3 pipe, the grid that breaks off the MN4 pipe becomes two node PFB and PFBA with PFB, add ac small signal, carries out the second loop ac small signal transition function and calculates.Equivalence ac small signal circuit is as shown in Figure 5.G among Fig. 5 _Mp7, g _Mp8, g _Mn4, g _Mn5Be respectively the mutual conductance of metal-oxide-semiconductor MP7, MP8, MN4 and MN5, C _I, C _II, C _IIIBe respectively AMP2, the AMP4 of second loop, the output equivalent electric capacity of AMP5, wherein, C _IThe gate capacitance that includes power tube MP11, C _IIIn do not consider the equivalent capacity of miller compensation capacitor C 3, C at MN5 pipe input end _IIIIn do not consider the effect of C3, R yet _IIt is the equivalent output resistance of the AMP4 of second loop.The zero limit of second loop can be represented as follows:

${\mathrm{<figure-callout\; id="1"\; label="z"\; filenames="HDA00002093819600022.png"\; state="\{\{state\}\}">z</figure-callout>}}_{1\mathrm{cc}}=\frac{g_{\mathrm{mp}8}}{R_4{C}_2(\frac{1}{R_3}+g_{\mathrm{mp}8}+\frac{1}{R_4})}---\left(16\right)$

${\mathrm{<figure-callout\; id="1"\; label="p"\; filenames="HDA00002093819600022.png"\; state="\{\{state\}\}">p</figure-callout>}}_{1\mathrm{cc}}=\frac{1}{C_I{R}_I}---\left(17\right)$

${\mathrm{<figure-callout\; id="2"\; label="p"\; filenames="HDA00002093819600013.png"\; state="\{\{state\}\}">p</figure-callout>}}_{2\mathrm{cc}}=\frac{g_{\mathrm{mp}8}+\frac{1}{R_3}}{R_4(g_{\mathrm{mn}5}{R}_2{C}_3+C_2)(\frac{1}{R_3}+g_{\mathrm{mp}8}+\frac{1}{R_4})}---\left(18\right)$

Wherein, R _I≈ r _Omp3, be the output resistance of MP3, the limit p of PFB node _3ccBecause negative feedback, its output impedance is little, and equivalent capacity is also little, so p _3ccBe high frequency poles.

The second loop low-frequency gain of LDO of the present invention is:

Av=g _mn4R _Ig _mp7R ₃g _mn5R ₂ （19）

Ignoring high frequency zero limit, is input port with the PFBA node, and PFB is an output port, and its transition function can be expressed as:

${H\left(s\right)}_{\mathrm{CC}}=g_{\mathrm{mn}4}{R}_I{g}_{\mathrm{mp}7}{R}_3{g}_{\mathrm{mn}5}{\mathrm{<figure-callout\; id="2"\; label="R"\; filenames="HDA00002093819600013.png"\; state="\{\{state\}\}">R</figure-callout>}}_2\&times;\frac{1+\frac{s}{{\mathrm{<figure-callout\; id="1"\; label="z"\; filenames="HDA00002093819600022.png"\; state="\{\{state\}\}">z</figure-callout>}}_{1\mathrm{cc}}}}{(1+\frac{s}{{\mathrm{<figure-callout\; id="1"\; label="p"\; filenames="HDA00002093819600022.png"\; state="\{\{state\}\}">p</figure-callout>}}_{1\mathrm{cc}}})(1+\frac{s}{{\mathrm{<figure-callout\; id="2"\; label="p"\; filenames="HDA00002093819600013.png"\; state="\{\{state\}\}">p</figure-callout>}}_{2\mathrm{cc}}})}---\left(20\right)$

Under the overcurrent condition; Set the external output overcurrent protective current of LDO and can guarantee LDO under the overcurrent condition for , its output current is limited to

constant voltage, and to set up process the same with the LDO of common structure.Because as previously mentioned, when the overcurrent condition did not exist, over-current state can quick and stable return to pressure constant state.

Minimum input voltage in work is 5.5V, carries out emulation under the external load electric capacity of use 2uF, and LDO of the present invention can drive the electric current of 15mA and only need the quiescent current of 50uA.Under light, heavy duty, the first loop phase nargin minimum of LDO is 47.6 °, can guarantee system stability, and unity gain bandwidth is respectively 93.68KHz and 5.23MHz under light, heavy duty simultaneously.The LDO that the present invention designed has in limited time in the power supply power supply capacity, can stablize in the time at 500us and set up.

At 100ns in the time, load current I _OUTSaltus step in 100uA ~ 15mA scope, the transient response curve overall diagram of load is as shown in Figure 7, the overshoot of the output voltage of the LDO that the present invention designed or down towards the time have only 75mV.The process of setting up and the output current figure of LDO are as shown in Figure 8; The LDO that the process of setting up of the LDO that the present invention designed is more traditional will grow Time Created; But the amplitude upper limit of output current is effectively controlled, and after the overcurrent condition disappeared, LDO can the stable pressure constant state that returns to of prestissimo.

Application second loop that the present invention proposes is realized the LDO current protection technology; First loop and the shared double loop low pressure difference linear voltage regulator of the second loop local circuit; Simplify the double loop switching controls of traditional LDO, reduced the area of traditional LDO separate double loop; Use internal circuit and realize pseudo-ESR; Overcome ESR or resistance in series that traditional LDO need utilize electric capacity and realized many unfavorable factors of bringing effective zero point; Realized same loop stability effect, can be used among the SoC to other module for power supply or source of stable pressure externally is provided.

Those of ordinary skill in the art will appreciate that embodiment described here is in order to help reader understanding's principle of the present invention, should to be understood that protection scope of the present invention is not limited to such special statement and embodiment.Those of ordinary skill in the art can make various other various concrete distortion and combinations that do not break away from essence of the present invention according to these teachings disclosed by the invention, and these distortion and combination are still in protection scope of the present invention.

Claims (9)

1. double loop low pressure difference linear voltage regulator; Specifically comprise: first loop and second loop; Wherein, First loop is the third stage amplifier that is made up of first amplifier stage, second amplifier stage, the 3rd amplifier stage, first corrective network and second corrective network, and second loop is the third stage amplifier that is made up of second amplifier stage, the 4th amplifier stage, the 5th amplifier stage and the 3rd corrective network;

The positive input of said first amplifier stage connects the input end of outside reference voltage source as the reference voltage source signal of said linear voltage regulator; The negative input of first amplifier stage links to each other with the 4th end of second corrective network; The output terminal of first amplifier stage links to each other with first negative input of second amplifier stage, first end of first corrective network, and the offset side of first amplifier stage is the offset signal input end; Second negative input of described second amplifier stage links to each other with second end of the output terminal of the 5th amplifier stage, the 3rd corrective network; The output terminal of second amplifier stage links to each other with second end of first corrective network, the first input end of the 4th amplifier stage, first end of second corrective network, the input end of the 3rd amplifier stage, and the offset side of second amplifier stage is the offset signal input end; Second end of the output terminal of described the 3rd amplifier stage, second corrective network, second input end of the 4th amplifier stage connect the output terminal as said LDO, and the feedback end of the 3rd amplifier stage is connected as said LDO output end voltage feedback end with the 3rd end of second corrective network.First output terminal of described the 4th amplifier stage links to each other with first end of the 3rd corrective network, and second output terminal of the 4th amplifier stage links to each other with the 4th end of the 3rd corrective network; The negative input of described the 5th amplifier stage links to each other with the 3rd end of the 3rd corrective network, and the offset side of the 5th amplifier stage is the offset signal input end.

2. linear voltage regulator according to claim 1 is characterized in that, described first amplifier stage is managed MP1, MP4, MP5 by PMOS; NMOS pipe MN1, MN2 constitute; Wherein, PMOS pipe MP1 tube grid is used to import first offset signal as the offset side of first amplifier stage, and the source electrode of MP1 connects external power source; The grid of MP4 is as the positive input of first amplifier stage; The source electrode of MP4 links to each other with the drain electrode of the source electrode of MP5, MP1, and the drain electrode of MP4, the grid of MN1 and drain electrode link to each other with the grid of MN2, and the grid of MP5 is the negative input of first amplifier stage; The drain electrode of MP5 pipe links to each other as the output terminal of first amplifier stage with the drain electrode of MN2 pipe, the source grounding of the source electrode of MN1 and MN2 pipe.

3. linear voltage regulator according to claim 1; It is characterized in that, described second amplifier stage by PMOS manage MP3, NMOS pipe MN3, the MN4 pipe constitutes, wherein; The grid of PMOS pipe MP3 is that the offset side of second amplifier stage is used to import second offset signal; The drain electrode of MP3 links to each other as the output terminal of second amplifier stage with the drain electrode of MN3, and the grid of MN3 is as first negative input of second amplifier stage, and the source electrode of MN3 links to each other with the drain electrode of MN4; The grid of MN4 is as second negative input of second amplifier stage, the source ground of MN4.

4. linear voltage regulator according to claim 1 is characterized in that, described the 3rd amplifier stage is managed MP11, resistance R 8, R9 by PMOS and constituted; Wherein, The grid of PMOS pipe MP11 is as the input end of the 3rd amplifier stage, and the MP11 drain electrode links to each other as the output terminal of the 3rd amplifier stage with first end of R8, and second end of R8 links to each other as the feedback end of the 3rd amplifier stage with first end of R9; The second end ground connection of R9, MP11 pipe source electrode is connected to external power source.

5. linear voltage regulator according to claim 1; It is characterized in that; Described first corrective network is made up of resistance R 1 and capacitor C 1, and wherein, first end of R1 is as first end of first corrective network; Second end of R1 links to each other with first end of C1, and second end of C1 is second end of first corrective network.

6. linear voltage regulator according to claim 1; It is characterized in that described second corrective network is managed MP10, resistance R 6, R7 and capacitor C 4 by PMOS and constituted, wherein; The grid of MP10 is as first end of second corrective network; The drain electrode of MP10 pipe links to each other with first end of resistance R 7, first end of capacitor C 4, and MP10 pipe source electrode connects external power source, and second end of R7 is as second end of second corrective network; Second end of resistance R 6 is the 3rd end of second corrective network, and second end of capacitor C 4 links to each other as the 4th end of second corrective network with first end of resistance R 6.

7. linear voltage regulator according to claim 1 is characterized in that, described the 4th amplifier stage is managed MP7, MP8, MP9 and resistance R 3, R5 by PMOS and constituted, and wherein, the grid of PMOS pipe MP7 is as the first input end of the 4th amplifier stage; The drain electrode of MP7 pipe links to each other with MP8 pipe source electrode, as second output terminal of the 4th amplifier stage; PMOS pipe MP8 drain electrode links to each other with first end of R3, as first output terminal of the 4th amplifier stage; The grid of PMOS pipe MP8 links to each other with the grid of MP9, the drain electrode of MP9, first end of R5, the second end ground connection of R3 and R5, and the source electrode of MP9 is second input end of the 4th amplifier stage.

8. linear voltage regulator according to claim 1; It is characterized in that; Described the 5th amplifier stage is made up of PMOS pipe MP2 pipe, NMOS pipe MN5 pipe and resistance R 2, and wherein, the grid of MP2 pipe is used to import the 3rd offset signal as the offset side of the 5th amplifier stage; The drain electrode of MP2 pipe links to each other as the output terminal of the 5th amplifier stage with first end of the drain electrode of MN5 pipe, R2; The MN5 tube grid is as the negative input of the 5th amplifier stage, and the source electrode of MP2 connects external power source, the equal ground connection of second end of the source electrode of MN5 and R2.

9. linear voltage regulator according to claim 1; It is characterized in that described the 3rd corrective network is made up of resistance R 4, capacitor C 2 and C3, wherein; First end of resistance R 4 is as first end of the 3rd corrective network; First end of capacitor C 3 is as second end of the 3rd corrective network, and second end of R4, second end of capacitor C 2 link to each other as the 3rd end of the 3rd corrective network with second end of C3, and first end of capacitor C 2 is as the 4th end of the 3rd corrective network.

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