CN113849033B - Linear voltage stabilizer with impedance attenuation compensation - Google Patents
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- CN113849033B CN113849033B CN202111134962.2A CN202111134962A CN113849033B CN 113849033 B CN113849033 B CN 113849033B CN 202111134962 A CN202111134962 A CN 202111134962A CN 113849033 B CN113849033 B CN 113849033B
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Abstract
The invention belongs to the technical field of voltage regulators, and particularly relates to a linear voltage regulator with impedance attenuation compensation. The invention improves the compensation mode of the traditional linear voltage stabilizer with off-chip capacitance, and ensures the loop stability of the linear voltage stabilizer by carrying out output impedance attenuation at the output end of the first-stage amplification stage. The invention provides a new compensation mode on the basis of using the source follower to perform frequency compensation, the mode of inserting the source follower in the middle is still adopted to perform frequency compensation on the whole, but an impedance attenuation circuit is added in the previous stage circuit in cooperation with the use of the source follower, so that the frequency compensation can still be performed through the simple first-stage source follower under the condition that the second-stage parasitic capacitance of the linear voltage stabilizer is very large. While not increasing circuit complexity and power consumption. The frequency compensation circuit is very suitable for frequency compensation of a linear voltage regulator with a large load range of off-chip capacitance.
Description
Technical Field
The invention belongs to the technical field of voltage regulators, and particularly relates to a linear voltage regulator with impedance attenuation compensation.
Background
With the advent of artificial intelligence and the world of everything interconnection, the demand for integration of various systems is increasing, and as many modules as possible are integrated together in one chip in a power management chip, including a common linear regulator module. Linear voltage regulator often adjusts the unstable power supply voltage in outside as first order premodulation module for a stable power supply rail, for chip internal circuit power supply, generally in holistic chip design, in order to guarantee the stability of linear voltage regulator output, make whole chip can the steady operation, can be generally in the external filter capacitance of output termination one piece of linear voltage regulator, the value of this electric capacity often is very big, generally at microfarad magnitude. In the design of the linear voltage regulator, the design of a loop is very important, a linear voltage regulator which is qualified in design must ensure that enough phase margin can be provided in the whole load working range, and off-chip capacitance of an output end has a close relation with the loop compensation design of the linear voltage regulator, so the loop compensation of the linear voltage regulator must be reasonably designed by considering the influence of the off-chip capacitance. For the linear voltage regulator with the off-chip capacitor, if a traditional miller compensation structure in the operational amplifier is considered, it is difficult to fix the dominant pole inside a chip due to the overlarge capacitance of the output end, that is, the output part of the first-stage amplification stage, and the miller compensation scheme will fail, resulting in the failure of loop compensation. Therefore, for such a linear regulator, a dominant pole is generally made at the output terminal. In order to pursue a lower Vdropout and improve efficiency, most linear regulators choose to use the P-type transistor as the power transistor and simultaneously play the role of the second-stage amplifier, so that a lower pole is generated inside the power transistor due to a larger parasitic capacitance and a higher output resistance of the first stage, and thus the loop is unstable. In general, the frequency compensation method is to use a first-stage source follower added between two stages of amplifiers to separate the high resistance of the first-stage output from the high capacitance of the second-stage input, and at this time, the secondary point is generated at the first-stage output.
However, when the frequency compensation is performed by using the above method, it is a common situation in the linear regulator when the output resistance of the first stage is too large and the input capacitance of the second stage is large. At this time, the source follower may exhibit a stronger inductance characteristic, which may be referred to as an active inductance, and when the characteristic of the active inductance of the source follower is more obvious, a lower conjugate pole may be introduced at the source follower. Thereby undermining the stability of the entire loop. If the compensation method of the source follower is still to be adopted, the transconductance of the source follower must be increased, or the structure such as the super source follower is directly replaced. However, this will increase the power consumption of the circuit or increase the complexity of the circuit.
Disclosure of Invention
The invention aims to provide a new compensation scheme aiming at the problem easily brought by the conventional compensation mode of the conventional linear voltage regulator with an off-chip capacitor. The loop stability of the linear voltage regulator is ensured, and meanwhile, the complexity and the power consumption of the circuit are not increased.
In order to achieve the purpose, the technical scheme of the invention is as follows:
a linear voltage regulator with impedance attenuation compensation comprises a first NPN transistor Q1, a second NPN transistor Q2, a third NPN transistor Q3, a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a fifth resistor R5, a sixth resistor R6, a seventh resistor R7, an eighth resistor R8, a ninth resistor R9, a tenth resistor R10, an eleventh resistor R11, a twelfth resistor R12, a thirteenth resistor R13, a fourteenth resistor R14, a first PMOS transistor MP1, a second PMOS transistor MP2, a third PMOS transistor MP3, a fourth PMOS transistor MP4, a fifth PMOS transistor MP5, a sixth PMOS transistor MP6, a first NMOS transistor MN1, a second NMOS transistor MN2, a third NMOS transistor MN3, a first NMOS transistor HMN1, a second LDNMOS transistor HMN2, a third LDNMOS transistor HMN3, a fourth NMOS transistor HMN4, a first LDNMOS 1, a second LDP 2, a second PMOS transistor HMP2, a first PMOS transistor HMN3, a second PMOS transistor HMN4, the device comprises a first Zener diode Z1, a second Zener diode Z2, a third Zener diode Z3 and a first native MOS diode NAMOS1;
the first NPN transistor Q1 and the second NPN transistor Q2 form a differential pair transistor, the base electrode of the first NPN transistor Q1 is connected with one end of a third resistor and one end of a fourth resistor, the emitting electrode of the first NPN transistor Q1 is grounded after passing through the first resistor R1, and the collector electrode of the first NPN transistor Q1 is connected with the other end of the third resistor, the drain electrode of the first LDPMOS transistor HMP1 and the source electrode of the third PMOS transistor MP3 after passing through the second resistor R2; the base electrode of the second NPN tube Q2 is connected with the reference voltage, the emitting electrode of the second NPN tube Q2 is grounded after passing through the first resistor R1, and the collector electrode of the second NPN tube Q2 is connected with the source electrode of the second LDNMOS tube HMN 2; the base electrode of the third NPN tube Q3 is connected with reference voltage, the emitting electrode of the third NPN tube Q3 is grounded after passing through a fifth resistor R5, and the collector electrode of the third NPN tube Q3 is connected with the source electrode of the first LDNMOS tube HMN 1;
the grid electrode of the first LDNMOS tube HMN1 is connected with an external bias voltage, and the drain electrode of the first LDNMOS tube HMN1 is connected with the drain electrode and the grid electrode of the first PMOS tube MP1, the grid electrode of the second PMOS tube MP2 and one end of the eighth resistor R8 through a sixth resistor R6; the grid electrode of the second LDNMOS tube HMN2 is connected with an external bias voltage, and the drain electrode of the second LDNMOS tube HMN2 is connected with the drain electrode of the second PMOS tube MP2 and the other end of the eighth resistor R8 through a seventh resistor R7; the source electrodes of the first PMOS tube MP1 and the second PMOS tube MP2 are connected with a power supply;
the anode of the second Zener tube Z2 is connected with the drain electrode of the second PMOS tube MP2 and the grid electrode of the first native MOS tube NAMOS1, and the cathode of the second Zener tube Z2 is connected with the power supply; the drain electrode of the first native MOS tube NAMOS1 is connected with a power supply, and the source electrode of the first native MOS tube NAMOS1 is connected with one end of a first capacitor C1, the anode of a first Zener tube Z1, the grid electrode of a first LDPMOS tube HMP1 and the grid electrode of a second LDPMOS tube HMP 2; the other end of the first capacitor C1 is connected with a power supply, and the negative electrode of the first Zener diode Z1 is connected with the power supply; the source electrode of the first LDPMOS pipe HMP1 is connected with a power supply;
the source electrode of the second LDPMOS pipe HMP2 is connected with a power supply, and the drain electrode of the second LDPMOS pipe HMP2 is connected with the negative electrode of the third Zener pipe Z3 and the source electrode of the fourth PMOS pipe MP 4; the anode of the third Zener tube Z3 is grounded;
the grid electrode and the drain electrode of the third PMOS pipe MP3 are interconnected, and the drain electrode of the third PMOS pipe MP3 is grounded after passing through a ninth resistor R9; the grid electrode of the fourth PMOS tube MP4 is connected with the drain electrode of the third PMOS tube MP3, and the drain electrode of the fourth PMOS tube MP4 is grounded after passing through a tenth resistor R10;
the source electrode of the fifth PMOS pipe MP5 is connected with the power supply, and the grid electrode and the drain electrode are interconnected; the source electrode of the sixth PMOS tube MP6 is connected with the power supply, and the grid electrode of the sixth PMOS tube MP6 is connected with the drain electrode of the fifth PMOS tube MP 5;
the drain electrode of the third LDNMOS tube HMN3 is connected with the drain electrode of the fifth PMOS tube MP5 through a thirteenth resistor R13, and the grid electrode of the third LDNMOS tube HMN3 is connected with an external bias voltage; the drain electrode of the fourth LDNMOS tube HMN4 is connected with the drain electrode of the sixth PMOS tube MP6 through a fourteenth resistor R14, and the grid electrode of the fourth LDNMOS tube HMN4 is connected with external bias voltage;
the drain electrode of the first NMOS tube MN1 is connected with the source electrode of the third LDNMOS tube HMN3, the grid electrode of the first NMOS tube MN1 is connected with the drain electrode of the fourth PMOS tube MP4, and the source electrode of the first NMOS tube MN1 is connected with the drain electrode of the third NMOS tube MN3 through an eleventh resistor R11; the drain electrode of the second NMOS tube is connected with the source electrode of the fourth LDNMOS tube HMN4, the grid electrode of the second NMOS tube is connected with the reference voltage, and the source electrode of the second NMOS tube is connected with the drain electrode of the third NMOS tube MN3 after passing through the twelfth resistor R12;
the grid electrode of the third NMOS transistor MN3 is connected with external bias voltage, and the source electrode of the third NMOS transistor is grounded;
the connection point of the drain electrode of the first LDPMOS pipe HMP1, the second resistor R2, the third resistor R3 and the source electrode of the third PMOS pipe MP3 is the output end of the linear voltage regulator.
In the above scheme, the compensation mode of the traditional linear voltage stabilizer with the off-chip capacitor is improved, and the output impedance attenuation is carried out at the output end of the first-stage amplification stage, so that the loop stability of the linear voltage stabilizer is ensured. The circuit can be divided into a first-stage amplifier, a second-stage amplifier, a source follower and an overcurrent protection module. One end of the first-stage amplifier is connected with reference voltage, the output voltage of the linear voltage stabilizer is connected with the other end after being subjected to voltage division by a resistor, and the linear voltage stabilizer is guaranteed to output stable voltage by clamping of the operational amplifier. The second-stage amplifier is a common-source amplifier composed of PMOS power tubes, plays a certain role in amplification, increases the gain of the whole operational amplifier, and simultaneously the load current of the linear voltage stabilizer can flow through the power tubes. The source follower part is used as a buffer to play a role in isolating a first-stage large output resistor and a second-stage large input capacitor, and meanwhile, an impedance attenuation resistor is added in front of the source follower, so that the output resistor of the first stage is greatly reduced, and the application range of the source follower is greatly increased. The overcurrent protection module part detects the current on the power tube, converts the current into voltage to be compared with reference voltage, and when the current flowing through the power tube is overlarge, the grid voltage of the power tube is regulated through negative feedback, so that the current flowing through the power tube is limited to a specific value, and the function of limiting the current is achieved.
The invention has the advantages that a new compensation mode is provided on the basis of using the source follower to perform frequency compensation, the frequency compensation is performed in a mode of inserting the source follower in the middle, but an impedance attenuation circuit is added in a previous stage circuit in cooperation with the source follower, so that the frequency compensation can be performed through the simple first-stage source follower under the condition that the second-stage parasitic capacitance of the linear voltage stabilizer is very large. While not increasing circuit complexity and power consumption. The frequency compensation circuit is very suitable for frequency compensation of a linear voltage regulator with a large load range of off-chip capacitance.
Drawings
Fig. 1 shows a specific circuit of a linear regulator according to the present invention.
Fig. 2 shows a first-stage operational amplifier output impedance small-signal circuit in the linear regulator of the present invention.
FIG. 3 is a circuit diagram of a linear regulator loop gain small signal according to the present invention.
Fig. 4 shows a bode plot of the loop gain of a linear regulator without an output impedance attenuation block according to the present invention.
Fig. 5 is a bode plot of the loop gain of the linear regulator with the output impedance attenuation block according to the present invention.
Detailed Description
The technical scheme of the invention is described in detail below with reference to the accompanying drawings:
the circuit of the linear voltage regulator of the present invention is shown in fig. 1. The pair of input pair tubes Q1 and Q2 is used as an amplifying device of a first stage amplifier, the voltage division output by the linear voltage stabilizer is amplified compared with the reference voltage REF, and the output is sent to the next stage as the output at the drain terminal of MP 2. The branch where the Q3 is located is used as a bias circuit, and the branch can be appropriately replaced by other types of bias circuits without influencing the use. In order to enable the linear voltage regulator to be applied in a high-voltage input environment, the HMN1 and the HMN2 are used as high-voltage pipes to resist pressure. The branch circuits where the Q1 and the Q2 are located are not symmetrical, and the collector electrode series resistor of the Q1 is connected to the output again, so that the use of a high-voltage tube can be omitted on the branch circuit, and the area is saved. The drain of the MP2 is used as the output of the first stage amplifier, and is connected to the input of the source follower NAMOS, where the source follower uses Native MOS, its threshold voltage is negative, and other properties are substantially the same as those of NMOS, and if a common NMOS is used here, the drain potential of the MP2 is the source potential of the HMP1 plus a threshold voltage, and when the linear regulator is lightly loaded, the source potential of the HMP1 is close to VIN, which may cause the MP2 to operate in a linear region rather than a saturation region, and thus the current cannot be accurately mirrored, which affects the normal operation of the whole circuit. Z1, Z2 and Z3 are Zener tubes, and protect low-voltage tubes from breakdown. The role of C1 is to ensure that VIN can be quickly coupled to the gate of HMP1 at fast power-up, so that the circuit smoothly enters an operating state after power-up. The output VOUT is divided by resistors R3 and R4 and then returns to the base of Q1, i.e., the positive terminal of the first stage operational amplifier. Forming a negative feedback to generate a stable VOUT, wherein VOUT has a value:
the working principle of the current limiting circuit is as follows: when the current flowing through the HMP1 is large, the HMP2 mirrors the current on the HMP1, the current generates a voltage through the R10 to be sent to the positive terminal of the overcurrent clamp operational amplifier, i.e. the gate of the MN1, and when the voltage on the R10 is equal to REF, the clamp circuit acts, and the magnitude of the current limit can be obtained as follows:
when the current flowing through the HMP1 exceeds I limit In the process, the gate of the HMP1 is raised through negative feedback of the operational amplifier, so that the current flowing through the HMP1 cannot be further increased.
The compensation principle of the linear regulator is described in detail below: the compensation of the linear voltage stabilizer is mainly realized by inserting a source follower NAMOS1 between the first two stages of amplifiers, and in addition, a resistor R8 is added into the output part of the amplifier at the previous stage, and the resistor is positioned between the grid and the drain of the MP2, and the output impedance of the first stage can be greatly attenuated through the resistor. Meanwhile, in this case, the current flowing through R8 is very small, and does not affect the quiescent operating point of the circuit, and the principle of R8 attenuating the output impedance of the first-stage amplifier is as follows:
looking into the output of the first stage, in order to obtain the small signal impedance, an equivalent small signal circuit as shown in fig. 2 can be obtained, and the size of the output resistor of the first stage operational amplifier can be obtained by the small signal equivalent circuit to be approximately equal to:
because Ro2 is far larger than the value of R8, the output resistance Ro1 of the first-stage operational amplifier is approximately equal to R8/2, and is greatly reduced compared with the original output resistance Ro 2.
In order to solve the loop gain expression of the whole loop of the linear voltage regulator, a small-signal circuit diagram of the whole loop can be drawn as shown in fig. 3, where Ro1 is the output resistance of the first-stage operational amplifier, C1 is the parasitic equivalent capacitance of the output of the first-stage operational amplifier to the ground, cs is the parasitic capacitance between the gate and the source of the source follower NAMOS1, rs is the small-signal output resistance of NAMOS1, and Cg is the equivalent capacitance of the gate of the power tube to the ground, and this capacitance can be very large because of the large size of the power tube. gms is the transconductance of the source follower. C2 can be considered as an external large capacitor of the linear voltage regulator, and C2 is considered as uF level in the linear voltage regulator.
From fig. 3, the loop gain can be found as:
β is a voltage dividing ratio of the voltage dividing resistance. The right half-plane zero generated therein is very high and can be ignored, because the value of the first-order coefficient C2Ro2 in the denominator is very high, the dominant pole of the loop can be obtained as follows:
it can be seen that the dominant pole of the loop is at the output, which is expected, but the computation of the secondary point is not as easy, since too large Cg results in the latter two roots of the equation in the denominator not being separate real numbers, in fact when the latter two roots have come close to each other, becoming a pair of conjugate poles. The resonant frequency of the conjugate pole can be approximated as:
conjugate poles significantly reduce the phase margin in the loop and it is therefore desirable to keep it as far away from the origin as possible. It can be seen that because Cg is large and the source follower uses only one common MOS transistor, gms is not large enough, which makes the conjugate pole close to the origin, and the effective method is to reduce Ro1, which is the meaning of the impedance attenuation resistor. Ro1 is greatly reduced due to impedance attenuation resistance, and the conjugate pole is pushed away from the origin, so that the stability of the system is ensured.
Without the use of the impedance attenuation resistor, the loop gain bode plot is shown in fig. 4 when the linear regulator is fully loaded, i.e., ro2 is at a minimum, with the dominant pole furthest from the origin and closest to the following conjugate pole, and therefore the stability is the worst, and without the use of the impedance attenuation technique, i.e., without R8. It can be seen at this point that the conjugate pole is around 50 KHz. Too close to the dominant pole, when the phase margin of the loop is about-30 °, the whole system is already quite unstable, and the compensation method of inserting a source follower between the two stages of amplifiers is not suitable for the linear regulator.
In the case of using the impedance attenuation resistor, the resulting loop gain bode plot is shown in fig. 5, also when the linear regulator is fully loaded. It can be seen that the conjugate pole is pushed to approximately 805KHz already far outside the bandwidth, and the phase margin of the loop can reach approximately 67 °.
In summary, the phase margin of the linear voltage regulator with the off-chip capacitor can be greatly improved by using the novel frequency compensation method, only one resistor is added, excessive power consumption is not consumed, the complexity of the circuit is not increased, and the novel frequency compensation method is suitable for being used as a compensation scheme of the linear voltage regulator with the off-chip capacitor.
Claims (1)
1. A linear voltage regulator with impedance attenuation compensation comprises a first NPN transistor Q1, a second NPN transistor Q2, a third NPN transistor Q3, a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a fifth resistor R5, a sixth resistor R6, a seventh resistor R7, an eighth resistor R8, a ninth resistor R9, a tenth resistor R10, an eleventh resistor R11, a twelfth resistor R12, a thirteenth resistor R13, a fourteenth resistor R14, a first PMOS transistor MP1, a second PMOS transistor MP2, a third PMOS transistor MP3, a fourth PMOS transistor MP4, a fifth PMOS transistor MP5, a sixth PMOS transistor MP6, a first NMOS transistor MN1, a second NMOS transistor MN2, a third NMOS transistor MN3, a first NMOS transistor HMN1, a second NMOS transistor LDN 2, a third PMOS transistor HMN3, a fourth NMOS transistor MN4, a first NMOS transistor HMP1, a second NMOS transistor LDP 2, a third PMOS transistor HMN3, a fourth NMOS 4, a first NMOS transistor HMP1, a second NMOS 2, a second PMOS 2, a third PMOS 2 and a third PMOS 3, a first Zener diode Z1, a second Zener diode Z2, a third Zener diode Z3 and a first native MOS diode NAMOS1;
the first NPN tube Q1 and the second NPN tube Q2 form a differential pair tube, the base electrode of the first NPN tube Q1 is connected with one end of a third resistor and one end of a fourth resistor, the emitting electrode of the first NPN tube Q1 is grounded after passing through the first resistor R1, and the collector electrode of the first NPN tube Q1 is connected with the other end of the third resistor, the drain electrode of the first LDPMOS tube HMP1 and the source electrode of the third PMOS tube MP3 after passing through the second resistor R2; the base electrode of the second NPN tube Q2 is connected with the reference voltage, the emitting electrode of the second NPN tube Q2 is grounded after passing through the first resistor R1, and the collector electrode of the second NPN tube Q2 is connected with the source electrode of the second LDNMOS tube HMN 2; the base electrode of the third NPN tube Q3 is connected with the reference voltage, the emitter electrode of the third NPN tube Q3 is grounded after passing through the fifth resistor R5, and the collector electrode of the third NPN tube Q3 is connected with the source electrode of the first LDNMOS tube HMN 1;
the grid electrode of the first LDNMOS tube HMN1 is connected with an external bias voltage, and the drain electrode of the first LDNMOS tube HMN1 is connected with the drain electrode and the grid electrode of the first PMOS tube MP1, the grid electrode of the second PMOS tube MP2 and one end of the eighth resistor R8 through a sixth resistor R6; the grid electrode of the second LDNMOS tube HMN2 is connected with an external bias voltage, and the drain electrode of the second LDNMOS tube HMN2 is connected with the drain electrode of the second PMOS tube MP2 and the other end of the eighth resistor R8 through a seventh resistor R7; the source electrodes of the first PMOS pipe MP1 and the second PMOS pipe MP2 are connected with a power supply;
the anode of the second Zener tube Z2 is connected with the drain electrode of the second PMOS tube MP2 and the grid electrode of the first native MOS tube NAMOS1, and the cathode of the second Zener tube Z2 is connected with the power supply; the drain electrode of the first native MOS tube NAMOS1 is connected with a power supply, and the source electrode of the first native MOS tube NAMOS1 is connected with one end of a first capacitor C1, the anode of a first Zener tube Z1, the grid electrode of a first LDPMOS tube HMP1 and the grid electrode of a second LDPMOS tube HMP 2; the other end of the first capacitor C1 is connected with a power supply, and the negative electrode of the first Zener diode Z1 is connected with the power supply; the source electrode of the first LDPMOS pipe HMP1 is connected with a power supply;
the source electrode of the second LDPMOS pipe HMP2 is connected with a power supply, and the drain electrode of the second LDPMOS pipe HMP2 is connected with the negative electrode of the third Zener pipe Z3 and the source electrode of the fourth PMOS pipe MP 4; the anode of the third Zener tube Z3 is grounded;
the grid electrode and the drain electrode of the third PMOS pipe MP3 are interconnected, and the drain electrode of the third PMOS pipe MP3 is grounded after passing through a ninth resistor R9; the grid electrode of the fourth PMOS transistor MP4 is connected to the drain electrode of the third PMOS transistor MP3, and the drain electrode of the fourth PMOS transistor MP4 is grounded through the tenth resistor R10;
the source electrode of the fifth PMOS pipe MP5 is connected with the power supply, and the grid electrode and the drain electrode are interconnected; the source electrode of the sixth PMOS tube MP6 is connected with the power supply, and the grid electrode of the sixth PMOS tube MP6 is connected with the drain electrode of the fifth PMOS tube MP 5;
the drain electrode of the third LDNMOS tube HMN3 is connected with the drain electrode of the fifth PMOS tube MP5 through a thirteenth resistor R13, and the grid electrode of the third LDNMOS tube HMN3 is connected with an external bias voltage; the drain electrode of the fourth LDNMOS tube HMN4 is connected with the drain electrode of the sixth PMOS tube MP6 through a fourteenth resistor R14, and the grid electrode of the fourth LDNMOS tube HMN4 is connected with an external bias voltage;
the drain electrode of the first NMOS tube MN1 is connected with the source electrode of the third LDNMOS tube HMN3, the grid electrode of the first NMOS tube MN1 is connected with the drain electrode of the fourth PMOS tube MP4, and the source electrode of the first NMOS tube MN1 is connected with the drain electrode of the third NMOS tube MN3 through an eleventh resistor R11; the drain electrode of the second NMOS tube is connected with the source electrode of the fourth LDNMOS tube HMN4, the grid electrode of the second NMOS tube is connected with the reference voltage, and the source electrode of the second NMOS tube passes through the twelfth resistor R12 and then is connected with the drain electrode of the third NMOS tube MN 3;
the grid electrode of the third NMOS tube MN3 is connected with external bias voltage, and the source electrode of the third NMOS tube is grounded;
and the connection point of the drain electrode of the first LDPMOS pipe HMP1, the second resistor R2, the third resistor R3 and the source electrode of the third PMOS pipe MP3 is the output end of the linear voltage regulator.
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