CN113849033B - Linear voltage stabilizer with impedance attenuation compensation - Google Patents

Abstract

The invention belongs to the technical field of voltage regulators, and particularly relates to a linear voltage regulator with impedance attenuation compensation. The invention improves the compensation mode of the traditional linear voltage stabilizer with off-chip capacitance, and ensures the loop stability of the linear voltage stabilizer by carrying out output impedance attenuation at the output end of the first-stage amplification stage. The invention provides a new compensation mode on the basis of using the source follower to perform frequency compensation, the mode of inserting the source follower in the middle is still adopted to perform frequency compensation on the whole, but an impedance attenuation circuit is added in the previous stage circuit in cooperation with the use of the source follower, so that the frequency compensation can still be performed through the simple first-stage source follower under the condition that the second-stage parasitic capacitance of the linear voltage stabilizer is very large. While not increasing circuit complexity and power consumption. The frequency compensation circuit is very suitable for frequency compensation of a linear voltage regulator with a large load range of off-chip capacitance.

Description

A Linear Regulator with Impedance Attenuation Compensation

technical field

The invention belongs to the technical field of voltage stabilizers, in particular to a linear voltage stabilizer with impedance attenuation compensation.

Background technique

With the advent of the era of artificial intelligence and the Internet of Everything, the integration requirements for various systems are getting higher and higher. In the power management chip, as many modules as possible will be integrated into one chip, including the commonly used linear stabilizer. pressure module. The linear regulator is often used as the first-stage pre-modulation module to adjust the external unstable power supply voltage into a stable power supply rail to supply power to the internal circuit of the chip. Usually in the overall chip design, in order to ensure the linear regulator The stability of the output enables the entire chip to work stably. Usually, an external filter capacitor is connected to the output end of the linear regulator. The value of this capacitor is often very large, generally in the microfarad level. In the design of linear regulators, the design of the loop is very important. A well-designed linear regulator must ensure that it can have sufficient phase margin in the entire load operating range. The loop compensation design of the linear regulator is closely related, so the loop compensation of this type of linear regulator must consider the influence of off-chip capacitance to carry out a reasonable design. For linear regulators with off-chip capacitors, if the traditional Miller compensation structure in op amps is considered, it is difficult to fix the main pole inside the chip due to the excessive capacitance at the output end, that is, the output of the first stage of amplification. In part, the Miller compensation scheme will fail, causing the loop compensation to fail. Therefore, for this kind of linear regulator, the main pole is generally made at the output end. In order to pursue lower Vdropout and improve efficiency, most linear regulators will choose to use the P tube as the power tube, and at the same time undertake the role of the second-stage amplifier, then the larger parasitic capacitance on the power tube and the first stage are relatively large. A high output resistance creates a lower pole internally, thus making the loop unstable. In general, the method of frequency compensation is to use a first-stage source follower to be added between the two-stage amplifiers to separate the high resistance of the first stage output from the high capacitance of the second stage input. At this time, the secondary point is generated in the first stage. Because of the lower capacitance at the output of the first stage, the secondary point can be made very high, so the stability of the loop is guaranteed.

However, when using the above method for frequency compensation, when the output resistance of the first stage is too large and the input capacitance of the second stage is large, this is a relatively common situation in linear regulators. At this time, the source follower will show relatively strong inductance characteristics, which can be called an active inductance. Low conjugate pole. Thus destroying the stability of the entire loop. At this time, if you still want to continue to use the source follower compensation method, you must try to increase the transconductance of the source follower, or directly replace the structure, such as using a super source follower or the like. But this will inevitably increase the power consumption of the circuit or increase the complexity of the circuit.

SUMMARY OF THE INVENTION

The purpose of the present invention is to propose a new compensation scheme for the problems easily brought about by the conventional compensation method of the existing linear voltage regulator with off-chip capacitance. While ensuring the stability of the linear regulator loop, it will not increase the complexity and power consumption of the circuit.

For achieving the above object, the technical scheme of the present invention is:

A linear regulator for impedance attenuation compensation, comprising a first NPN transistor Q1, a second NPN transistor Q2, a third NPN transistor Q3, a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, Fifth resistor R5, sixth resistor R6, seventh resistor R7, eighth resistor R8, ninth resistor R9, tenth resistor R10, eleventh resistor R11, twelfth resistor R12, thirteenth resistor R13, tenth resistor Four resistors R14, first PMOS transistor MP1, second PMOS transistor MP2, third PMOS transistor MP3, fourth PMOS transistor MP4, fifth PMOS transistor MP5, sixth PMOS transistor MP6, first NMOS transistor MN1, second NMOS transistor MN2, the third NMOS transistor MN3, the first LDNMOS transistor HMN1, the second LDNMOS transistor HMN2, the third LDNMOS transistor HMN3, the fourth LDNMOS transistor HMN4, the first LDPMOS transistor HMP1, the second LDPMOS transistor HMP2, the first capacitor C1, the first A Zener tube Z1, a second Zener tube Z2, a third Zener tube Z3, and a first nativeMOS tube NAMOS1;

The first NPN transistor Q1 and the second NPN transistor Q2 form a differential pair transistor, the base of the first NPN transistor Q1 is connected to one end of the third resistor and one end of the fourth resistor, and the emitter of the first NPN transistor Q1 passes through the first NPN transistor Q1. The resistor R1 is grounded, and the collector of the first NPN transistor Q1 is connected to the other end of the third resistor, the drain of the first LDPMOS transistor HMP1 and the source of the third PMOS transistor MP3 through the second resistor R2; the second NPN transistor Q2 Its base is connected to the reference voltage, its emitter is grounded after passing through the first resistor R1, and its collector is connected to the source of the second LDNMOS tube HMN2; the base of the third NPN tube Q3 is connected to the reference voltage, and its emitter is connected to the reference voltage through the fifth resistor R5 is grounded, and its collector is connected to the source of the first LDNMOS tube HMN1;

The gate of the first LDNMOS transistor HMN1 is connected to the external bias voltage, and its drain is connected to the drain and gate of the first PMOS transistor MP1, the gate of the second PMOS transistor MP2, and the gate of the eighth resistor R8 through the sixth resistor R6. One end; the gate of the second LDNMOS tube HMN2 is connected to the external bias voltage, and its drain is connected to the drain of the second PMOS tube MP2 and the other end of the eighth resistor R8 through the seventh resistor R7; the first PMOS tube MP1 and the first The source of the two PMOS transistors MP2 is connected to the power supply;

The anode of the second Zener transistor Z2 is connected to the drain of the second PMOS transistor MP2 and the gate of the first native MOS transistor NAMOS1, the cathode of the second Zener transistor Z2 is connected to the power supply; the drain of the first native MOS transistor NAMOS1 is connected to the power supply , its source is connected to one end of the first capacitor C1, the positive electrode of the first Zener tube Z1, the gate of the first LDPMOS tube HMP1 and the gate of the second LDPMOS tube HMP2; the other end of the first capacitor C1 is connected to the power supply, the first The negative pole of a Zener tube Z1 is connected to the power supply; the source of the first LDPMOS tube HMP1 is connected to the power supply;

The source of the second LDPMOS transistor HMP2 is connected to the power supply, and its drain is connected to the negative electrode of the third Zener transistor Z3 and the source of the fourth PMOS transistor MP4; the positive electrode of the third Zener transistor Z3 is grounded;

The gate and drain of the third PMOS transistor MP3 are interconnected, and its drain is grounded through the ninth resistor R9; the gate of the fourth PMOS transistor MP4 is connected to the drain of the third PMOS transistor MP3, and the drain of the fourth PMOS transistor MP4 The pole is grounded after passing through the tenth resistor R10;

The source of the fifth PMOS tube MP5 is connected to the power supply, and its gate and drain are interconnected; the source of the sixth PMOS tube MP6 is connected to the power supply, and its gate is connected to the drain of the fifth PMOS tube MP5;

The drain of the third LDNMOS transistor HMN3 is connected to the drain of the fifth PMOS transistor MP5 through the thirteenth resistor R13, and the gate of the third LDNMOS transistor HMN3 is connected to the external bias voltage; the drain of the fourth LDNMOS transistor HMN4 is connected to the drain of the fifth PMOS transistor MP5 through the tenth The fourth resistor R14 is connected to the drain of the sixth PMOS transistor MP6, and the gate of the fourth LDNMOS transistor HMN4 is connected to the external bias voltage;

The drain of the first NMOS transistor MN1 is connected to the source of the third LDNMOS transistor HMN3, the gate of the first NMOS transistor MN1 is connected to the drain of the fourth PMOS transistor MP4, and the source of the first NMOS transistor MN1 passes through the eleventh resistor R11 The drain of the third NMOS transistor MN3 is then connected; the drain of the second NMOS transistor is connected to the source of the fourth LDNMOS transistor HMN4, the gate of the second NMOS transistor is connected to the reference voltage, and its source is connected to the twelfth resistor R12. The drain of the three NMOS transistor MN3;

The gate of the third NMOS transistor MN3 is connected to the external bias voltage, and its source is grounded;

The connection point of the drain of the first LDPMOS transistor HMP1, the second resistor R2, the third resistor R3, and the source of the third PMOS transistor MP3 is the output end of the linear regulator.

In the above scheme, by improving the compensation method of the traditional linear regulator with off-chip capacitors, and by performing output impedance attenuation at the output end of the first-stage amplifying stage, the loop stability of the linear regulator is ensured. The circuit can be divided into a first-stage amplifier, a second-stage amplifier, a source follower, and an overcurrent protection module. One end of the first-stage amplifier is connected to the reference voltage, and the output voltage of the linear voltage stabilizer is connected to the other end after being divided by a resistor. Generally, the output voltage of the linear voltage stabilizer is guaranteed by the clamp of the op amp. The secondary amplifier is a common source amplifier composed of the PMOS power tube itself, which plays a certain amplification role and increases the gain of the entire operational amplifier. At the same time, the load current of the linear regulator can flow through the power tube. The source follower part is used as a buffer to isolate the large output resistance of the first stage and the large input capacitance of the second stage. At the same time, an impedance attenuation resistor is added in front of the source follower to greatly reduce the output resistance of the first stage. Smaller, the applicable range of the source follower is greatly increased. The overcurrent protection module part detects the current on the power tube, converts it into a voltage and compares it with the reference voltage. When the current flowing through the power tube is too large, the grid voltage of the power tube is adjusted by negative feedback, and the current flowing through the power tube is adjusted. Its current is limited to a specific value, which acts as a current limiter.

The beneficial effect of the present invention is that the present invention proposes a new compensation method on the basis of using the source follower for frequency compensation, and the method of inserting the source follower in the middle is still used for frequency compensation as a whole, but in the previous stage circuit The impedance attenuation circuit is added to the use of the source follower in the middle, so that the frequency can be compensated by a simple first-stage source follower even when the second-stage parasitic capacitance of the linear regulator is large. At the same time, the circuit complexity and power consumption are not increased. It is very suitable for frequency compensation of linear regulators with large load range with off-chip capacitors.

Description of drawings

Fig. 1 The specific circuit of the linear voltage stabilizer proposed by the present invention.

Fig. 2 The output impedance small signal circuit of the first-stage operational amplifier in the linear regulator proposed by the present invention.

FIG. 3 is a circuit diagram of a small-signal circuit of the loop gain of the linear regulator proposed by the present invention.

FIG. 4 is a Bode diagram of the loop gain of the linear regulator proposed by the present invention without an output impedance attenuation module.

FIG. 5 is a Bode diagram of the loop gain of the linear regulator with the output impedance attenuation module proposed by the present invention.

Detailed ways

Below in conjunction with accompanying drawing, the technical scheme of the present invention is described in detail:

The circuit of the linear regulator proposed by the present invention is shown in FIG. 1 . The pair of input-to-tube Q1 and Q2 is used as the amplifier of the first-stage amplifier. The divided voltage output by the linear regulator is compared with the reference voltage REF and then amplified, and the drain of MP2 is sent to the next stage as an output. The branch where Q3 is located is used as a bias circuit, and this circuit can also be appropriately replaced with other types of bias circuits without affecting the use. In order to make the linear regulator can be applied in the environment of high voltage input, HMN1 and HMN2 are used as high voltage tubes to resist pressure. The branches where Q1 and Q2 are located are not symmetrical. Connecting the collector series resistance of Q1 to the output can save the use of high-voltage tubes on this branch and save area. The drain of MP2 is used as the output of the first-stage amplifier and is connected to the input of the source follower NAMOS. Here, the source follower uses Native MOS, and its threshold voltage is negative. The other properties are basically the same as the NMOS tube. Using a common NMOS transistor, the drain potential of MP2 is the source potential of the power transistor HMP1 plus a threshold voltage. When the linear regulator is lightly loaded, the source potential of HMP1 is close to VIN, which will cause MP2 to work online. It cannot accurately mirror the current, which affects the normal operation of the entire circuit. Z1, Z2 and Z3 are Zener tubes that protect the low-voltage tubes from breakdown. The function of C1 is to ensure that VIN can be quickly coupled to the gate of HMP1 during fast power-on, so that the circuit can enter the working state smoothly after power-on. After the source follower is followed by the gate of HMP1, which is the input of the second stage amplifier, the output VOUT is divided by resistors R3 and R4 and then returns to the base stage of Q1, which is the positive end of the first stage op amp. A negative feedback is formed, resulting in a stable VOUT where the value of VOUT is:

The working principle of the current limiting circuit is as follows: when the current flowing through HMP1 is large, HMP2 mirrors the current on HMP1, and the current passes through R10 to generate a voltage and send it to the positive end of the overcurrent clamp op amp, that is, the gate of MN1, When the voltage on R10 is equal to REF, the clamp circuit works, and the current limit can be obtained as:

When the current flowing through HMP1 exceeds I _limit , the gate of HMP1 is raised by the negative feedback of the operational amplifier, so that the current flowing through HMP1 cannot be further increased.

The compensation principle of the linear regulator is described in detail below: the compensation of the linear regulator is mainly realized by inserting a first-stage source follower NAMOS1 between the first two stages of amplifiers. A resistor R8 is partially added, which is located between the gate and drain of MP2, through which the output impedance of the first stage can be greatly attenuated. At the same time, in this case, the current flowing through R8 is very small and will not affect the static operating point of the circuit. The principle of R8 attenuating the output impedance of the first-stage amplifier is as follows:

Looking inward from the output of the first stage, in order to find the small-signal impedance, the equivalent small-signal circuit shown in Figure 2 can be obtained. Through the small-signal equivalent circuit, it can be concluded that the output resistance of the first-stage op amp is approximately equal to :

Because ro2 is much larger than the value of R8, the output resistance Ro1≈R8/2 of the first-stage operational amplifier is greatly reduced compared with the original output resistance ro2.

In order to solve the loop gain expression of the entire loop of the linear regulator, the small-signal circuit diagram of the entire loop can be drawn as shown in Figure 3, where Ro1 is the output resistance of the first stage op amp, and C1 is the first stage The parasitic equivalent capacitance of the op amp output to ground, Cs is the parasitic capacitance between the gate and source of the source follower NAMOS1, rs is the small signal output resistance of NAMOS1, and Cg is the equivalent capacitance of the power tube gate to ground, because the power The larger the size of the tube, this capacitor can be very large. gms is the transconductance of the source follower. C2 can be considered as a large capacitor attached to the linear regulator. In this linear regulator, C2 is considered to be uF level.

From Figure 3, the loop gain can be obtained as:

β is the voltage dividing ratio of the voltage dividing resistor. The resulting right half-plane zero point is very high and can be ignored because the value of the first-order coefficient C2Ro2 in the denominator is very high, so the main pole of the loop can be obtained as:

It can be seen that the main pole of the loop is at the output, which is expected, but the calculation of the secondary point is not so easy. At this time, due to the excessive Cg, the last two roots of the equation in the denominator are not separate real numbers. At this time, the latter two roots are already close to each other and become a pair of conjugate poles. The resonant frequency of this conjugate pole can be approximately expressed as:

Conjugate poles can significantly reduce phase margin in the loop, so it is desirable to keep them as far from the origin as possible. At this point, it can be seen that because Cg is large, and the source follower only uses a common MOS tube, gms is not large enough, which will make the conjugate pole close to the origin, and the effective method is to reduce Ro1, which is exactly The significance of the aforementioned impedance attenuation resistors. Ro1 is greatly reduced due to the impedance attenuation resistance, and the conjugate pole is thus pushed away from the origin, ensuring the stability of the system.

In the case of not using the impedance attenuation resistor, when the linear regulator is fully loaded, that is, when Ro2 is the smallest, the main pole is the farthest from the origin, and is closest to the conjugate pole behind, so the stability is the worst. In the case of the attenuation technique, that is, without R8, the loop gain Bode plot is shown in Figure 4. At this point, it can be seen that the conjugate pole is around 50KHz. If it is too close to the main pole, the phase margin of the loop is about -30°, and the whole system is quite unstable. At this time, the compensation method of inserting a source follower between the two amplifiers cannot be applied to this linearity. Stabilizer.

In the case of using the impedance attenuation resistor, also when the linear regulator is fully loaded, the obtained Bode plot of the loop gain is shown in Figure 5. At this time, it can be seen that the conjugate pole is pushed to about 805KHz, which is far beyond the bandwidth. At this time, the phase margin of the loop can reach about 67°.

In summary, the use of this new frequency compensation method can greatly improve the phase margin of linear regulators with off-chip capacitors, while only adding a resistor, will not consume excessive power consumption and increase the complexity of the circuit. It is suitable for use as a compensation scheme for linear regulators with off-chip capacitors.

Claims (1)

1. A linear voltage regulator with impedance attenuation compensation comprises a first NPN transistor Q1, a second NPN transistor Q2, a third NPN transistor Q3, a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a fifth resistor R5, a sixth resistor R6, a seventh resistor R7, an eighth resistor R8, a ninth resistor R9, a tenth resistor R10, an eleventh resistor R11, a twelfth resistor R12, a thirteenth resistor R13, a fourteenth resistor R14, a first PMOS transistor MP1, a second PMOS transistor MP2, a third PMOS transistor MP3, a fourth PMOS transistor MP4, a fifth PMOS transistor MP5, a sixth PMOS transistor MP6, a first NMOS transistor MN1, a second NMOS transistor MN2, a third NMOS transistor MN3, a first NMOS transistor HMN1, a second NMOS transistor LDN 2, a third PMOS transistor HMN3, a fourth NMOS transistor MN4, a first NMOS transistor HMP1, a second NMOS transistor LDP 2, a third PMOS transistor HMN3, a fourth NMOS 4, a first NMOS transistor HMP1, a second NMOS 2, a second PMOS 2, a third PMOS 2 and a third PMOS 3, a first Zener diode Z1, a second Zener diode Z2, a third Zener diode Z3 and a first native MOS diode NAMOS1;

the first NPN tube Q1 and the second NPN tube Q2 form a differential pair tube, the base electrode of the first NPN tube Q1 is connected with one end of a third resistor and one end of a fourth resistor, the emitting electrode of the first NPN tube Q1 is grounded after passing through the first resistor R1, and the collector electrode of the first NPN tube Q1 is connected with the other end of the third resistor, the drain electrode of the first LDPMOS tube HMP1 and the source electrode of the third PMOS tube MP3 after passing through the second resistor R2; the base electrode of the second NPN tube Q2 is connected with the reference voltage, the emitting electrode of the second NPN tube Q2 is grounded after passing through the first resistor R1, and the collector electrode of the second NPN tube Q2 is connected with the source electrode of the second LDNMOS tube HMN 2; the base electrode of the third NPN tube Q3 is connected with the reference voltage, the emitter electrode of the third NPN tube Q3 is grounded after passing through the fifth resistor R5, and the collector electrode of the third NPN tube Q3 is connected with the source electrode of the first LDNMOS tube HMN 1;

the grid electrode of the first LDNMOS tube HMN1 is connected with an external bias voltage, and the drain electrode of the first LDNMOS tube HMN1 is connected with the drain electrode and the grid electrode of the first PMOS tube MP1, the grid electrode of the second PMOS tube MP2 and one end of the eighth resistor R8 through a sixth resistor R6; the grid electrode of the second LDNMOS tube HMN2 is connected with an external bias voltage, and the drain electrode of the second LDNMOS tube HMN2 is connected with the drain electrode of the second PMOS tube MP2 and the other end of the eighth resistor R8 through a seventh resistor R7; the source electrodes of the first PMOS pipe MP1 and the second PMOS pipe MP2 are connected with a power supply;

the anode of the second Zener tube Z2 is connected with the drain electrode of the second PMOS tube MP2 and the grid electrode of the first native MOS tube NAMOS1, and the cathode of the second Zener tube Z2 is connected with the power supply; the drain electrode of the first native MOS tube NAMOS1 is connected with a power supply, and the source electrode of the first native MOS tube NAMOS1 is connected with one end of a first capacitor C1, the anode of a first Zener tube Z1, the grid electrode of a first LDPMOS tube HMP1 and the grid electrode of a second LDPMOS tube HMP 2; the other end of the first capacitor C1 is connected with a power supply, and the negative electrode of the first Zener diode Z1 is connected with the power supply; the source electrode of the first LDPMOS pipe HMP1 is connected with a power supply;

the source electrode of the second LDPMOS pipe HMP2 is connected with a power supply, and the drain electrode of the second LDPMOS pipe HMP2 is connected with the negative electrode of the third Zener pipe Z3 and the source electrode of the fourth PMOS pipe MP 4; the anode of the third Zener tube Z3 is grounded;

the grid electrode and the drain electrode of the third PMOS pipe MP3 are interconnected, and the drain electrode of the third PMOS pipe MP3 is grounded after passing through a ninth resistor R9; the grid electrode of the fourth PMOS transistor MP4 is connected to the drain electrode of the third PMOS transistor MP3, and the drain electrode of the fourth PMOS transistor MP4 is grounded through the tenth resistor R10;

the source electrode of the fifth PMOS pipe MP5 is connected with the power supply, and the grid electrode and the drain electrode are interconnected; the source electrode of the sixth PMOS tube MP6 is connected with the power supply, and the grid electrode of the sixth PMOS tube MP6 is connected with the drain electrode of the fifth PMOS tube MP 5;

the drain electrode of the third LDNMOS tube HMN3 is connected with the drain electrode of the fifth PMOS tube MP5 through a thirteenth resistor R13, and the grid electrode of the third LDNMOS tube HMN3 is connected with an external bias voltage; the drain electrode of the fourth LDNMOS tube HMN4 is connected with the drain electrode of the sixth PMOS tube MP6 through a fourteenth resistor R14, and the grid electrode of the fourth LDNMOS tube HMN4 is connected with an external bias voltage;

the drain electrode of the first NMOS tube MN1 is connected with the source electrode of the third LDNMOS tube HMN3, the grid electrode of the first NMOS tube MN1 is connected with the drain electrode of the fourth PMOS tube MP4, and the source electrode of the first NMOS tube MN1 is connected with the drain electrode of the third NMOS tube MN3 through an eleventh resistor R11; the drain electrode of the second NMOS tube is connected with the source electrode of the fourth LDNMOS tube HMN4, the grid electrode of the second NMOS tube is connected with the reference voltage, and the source electrode of the second NMOS tube passes through the twelfth resistor R12 and then is connected with the drain electrode of the third NMOS tube MN 3;

the grid electrode of the third NMOS tube MN3 is connected with external bias voltage, and the source electrode of the third NMOS tube is grounded;

and the connection point of the drain electrode of the first LDPMOS pipe HMP1, the second resistor R2, the third resistor R3 and the source electrode of the third PMOS pipe MP3 is the output end of the linear voltage regulator.

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