CN210075200U - Self-calibration comparator offset voltage elimination circuit - Google Patents
Self-calibration comparator offset voltage elimination circuit Download PDFInfo
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- CN210075200U CN210075200U CN201921044002.5U CN201921044002U CN210075200U CN 210075200 U CN210075200 U CN 210075200U CN 201921044002 U CN201921044002 U CN 201921044002U CN 210075200 U CN210075200 U CN 210075200U
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Abstract
The utility model discloses a self calibration comparator offset voltage cancelling circuit, include: the comparator is configured to control the input common-mode voltage and the comparison voltage according to the enabling signal, and after voltage correction is carried out by connecting the common-mode voltage, the comparison signal is connected for signal comparison output; the calibration unit is configured to be connected with two output ends OUTP and OUTN of the comparator, feed back an output signal of the comparator to the input end according to an enabling signal and counteract offset voltage; and the switching unit is configured to realize switching input of the common mode voltage and the comparison voltage through the enabling signal. The utility model discloses a switch element inputs common mode voltage and comparative voltage with enable signal control, inputs common mode voltage when carrying out the offset voltage, realizes the offset voltage among the canceling circuit, inputs comparative voltage after eliminating the offset voltage, carries out the normal comparison output of comparator. By the circuit, the offset voltage of the comparator can be greatly reduced, and the speed of the comparator is not influenced.
Description
Technical Field
The utility model relates to an offset voltage adjustment field especially relates to a self calibration comparator offset voltage elimination circuit.
Background
With the development of semiconductor technology, especially to the deep submicron stage, the performance of memories, data receivers and analog-to-digital converters is better and better, and the requirements for the key module comparators are higher and higher, wherein offset voltage, speed and noise are important factors influencing the performance of digital-to-analog converters (successive approximation type, flash memory and pipeline type).
Fig. 1 shows a typical application of a comparator in an analog-to-digital converter, and it is obvious that the low noise, high speed, low offset voltage (Vos) of the comparator has a decisive effect on the performance of the successive approximation analog-to-digital converter. It is therefore necessary to consider eliminating or reducing the offset voltage, and this patent introduces a comparator loop structure that self-calibrates the eliminated offset voltage without significantly affecting the speed of the comparator.
SUMMERY OF THE UTILITY MODEL
An object of the utility model is to provide a self calibration comparator offset voltage cancelling circuit to above-mentioned problem.
A self-calibrating comparator offset voltage cancellation circuit, comprising: the comparator is configured to control the input common-mode voltage and the comparison voltage according to the enabling signal, and after voltage correction is carried out by connecting the common-mode voltage, the comparison signal is connected for signal comparison output; the calibration unit is configured to be connected with two output ends OUTP and OUTN of the comparator, feed back an output signal of the comparator to the input end according to an enabling signal and counteract offset voltage; and the switching unit is configured to realize switching input of the common mode voltage and the comparison voltage through the enabling signal.
The comparator includes: the amplifying unit is configured to be a main differential pair and a correction differential pair which are connected in parallel, wherein the input end of the main differential pair is connected with the comparison signal, the input end of the correction differential pair is connected with the output signal of the calibration unit, and offset voltage of the main differential pair is offset through the voltage difference of the input end of the correction differential pair; and the dynamic comparison unit is configured as a dynamic comparator and an output latch, is connected with the output signal of the amplification unit and is used for realizing voltage comparison output.
The calibration unit includes: the input terminals Vop and Von are respectively connected to the two output terminals OUTP and OUTN of the comparator.
An output terminal for outputting a feedback voltage to the comparator; a first switch set configured to control charge stealing of the first charge storage capacitor by a Vop input port signal and an enable signal; and the second switch group is configured to control the charge shift of the second charge storage capacitor through the Von input port signal and the enabling signal.
Further, the self-calibration comparator offset voltage elimination circuit further comprises a third charge storage capacitor arranged in front of the output end, and the third charge storage capacitor, the first charge storage capacitor and the second charge storage capacitor change the voltage fed back to the comparator from the output end through charging and discharging.
The calibration unit comprises a first calibration unit and a second calibration unit which are the same, the Vop input end of the first calibration unit is connected with the OUTP output end of the comparator, and the Von input end of the first calibration unit is connected with the OUTN output end of the comparator; the Vop input end of the second calibration unit is connected with the OUTN output end of the comparator, and the Von input end of the second calibration unit is connected with the OUTP output end of the comparator.
Further, the first switch group and the second switch group adopt high-threshold MOS tubes. The charge storage capacitor adopts a metal-oxide-metal structure. The switch unit comprises a plurality of switches and a NOT gate, and the selection of the input signal of the comparator is realized by controlling the switch unit through an enabling signal.
The utility model has the advantages that: the input common-mode voltage and the comparison voltage are controlled through the switch unit and the enabling signal, the common-mode voltage is input when offset voltage is conducted, the charge shift of the calibration unit is achieved through the input signal control switch group, the offset voltage of the main differential pair is offset through the voltage difference of the input end of the calibration differential pair in the comparator, the offset voltage in the circuit is eliminated, the comparison voltage is input after the offset voltage is eliminated, and normal comparison output of the comparator is conducted. By the circuit, the offset voltage of the comparator can be greatly reduced, the speed of the comparator is not influenced, and the influence on noise is small.
Drawings
FIG. 1 is a schematic diagram of a typical application of a comparator in an analog-to-digital converter;
fig. 2 is a schematic view of the overall structure of the present invention;
fig. 3 is a schematic structural diagram of the calibration unit of the present invention;
fig. 4 is a schematic structural diagram of the comparator of the present invention;
fig. 5 is a schematic diagram of the present invention showing the offset voltage Vos;
fig. 6 is a simulation diagram of waveform simulation according to the present invention.
Detailed Description
In order to clearly understand the technical features, objects, and effects of the present invention, embodiments of the present invention will be described with reference to the accompanying drawings.
In this embodiment, as shown in fig. 2, the circuit is composed of two calibration units, four switches, a not gate, and a comparator.
The common mode voltage Vcom in the circuit is connected with the switches S0, S1; the other end of the S0 is connected with the positive input electrode of the comparator, the other end of the S1 is connected with the negative input electrode of the comparator, and the control end is connected with the correction enable CAL _ EN; one end of the S2 switch is connected with the input signal vip end, the other end of the S2 switch is connected with the positive input electrode of the comparator, one end of the S3 switch is connected with the input signal vin end, the other end of the S3 switch is connected with the negative input electrode of the comparator, the S2 control end and the S3 control end are connected with the output of the logical NOT gate, and the input end of the NOT gate is connected with the correction enabling end CAL _ EN. The clock input end of the comparator is connected with the input clock. The enabling ends of the two correction units are connected with a correction enabling end CAL _ EN, von of the correction unit 1 is connected with an OUTN port of the comparator, vop is connected with an OUTP port of the comparator, and the CALP end of the output end is connected with an input end CALP port of the comparator; the von of the correction unit 2 is connected to the OUTP port of the comparator, the vop is connected to the OUTN port of the comparator, and the CALP is connected to the CALN port of the comparator. The comparator OUTP port is the system vop end, and the OUTN port is the system von end.
Calibration unit as shown in fig. 3, the calibration unit contains 8 switches and 3 charge storage capacitors. CAL _ EN connects the control terminals of switches SW1, SW2, SW5, SW 6. Vop is connected with the control end of SW0, and is connected with the input end of NOT gate 1, and the output end of NOT gate 1 is connected with the control end of SW 3. Von is connected with the control end of the SW7, and is connected with the input end of the NOT gate 2, and the output end of the NOT gate 2 is connected with the control end of the switch SW 4. One end of SW0 is connected with a power supply and is connected with SW1 in series, the other end of SW1 is connected with a charge storage capacitor Cint1 and is connected with a switch SW2, the other end of SW2 is connected with SW3 in series, the other end of SW3 is connected with an output end CALP and is connected with the anode of the charge storage capacitor Ccap and is also connected with SW4, SW4 is connected with SW5 in series, the other end of SW5 is connected with the charge storage capacitor Cint2 and is also connected with SW6, SW6 is connected with SW7 in series, and the other end of SW7 is connected with the ground. The negative electrodes of the charge storage capacitors Cint1, Cint2 and Ccalp are connected to the ground.
In order to reduce the output load of the comparator and to minimize the influence on the speed of the comparator, the 8 switches of the calibration unit are minimum sized. The structure does not need to design bias voltage separately, and can approach the set value of the on-resistance of the switch during calibration. The charge redistribution is controlled by the size ratio of Cint and cclip and the available time of the calibration loop in each period, and in order to reduce the charge leakage on the cclip, the switch is realized by using a high-threshold MOS tube, and the capacitor is of a metal-oxide-metal structure.
The comparator is shown in fig. 4, and the first stage of the comparator adds the correction differential pair MSP, MSN beside the main differential pair MDP, MDN, in parallel with the main differential pair. The first stage can be a direct current amplifying structure or a dynamic amplifying structure.
The second stage includes a dynamic comparator and a latch structure.
The offset voltage correction differential pair MSP/N is connected with the main differential pair MDP/N in parallel, and the differential voltage on the correction differential pair MSP/N is opposite to the offset voltage on the main differential pair MDP/N. The MSP/N introduces extra noise to the comparator, the larger the differential pair size, the larger the calibration range, and the more noise is introduced, so the size of the MSP/N and the size of the MDP/N need to be balanced by a proper amount.
The working process of the embodiment:
as shown in fig. 5, when the calibration is started, CAL _ EN is set to 1, switches S0, S1 are turned on, S2, S3 are turned off, the comparator differential pair voltage is common mode Vcom, and for a positive offset voltage Vos (fig. 5), the output voltage vop is high and von is low, and through the two calibration units, the charges are shifted to CALN and out of CALP, so that the CALN voltage is increased and the CALP voltage is decreased, and the offset voltage of the input differential pair MDP/N is cancelled by the differential voltage at the input end of the differential pair MSP/N, and finally, the calibration is balanced. After the balance is achieved, the comparator outputs 0 and 1 at different clock period intervals, the voltage of the CALP/N node is kept stable, and as shown in FIG. 6, the difference between Vos after the comparator is corrected and Vos before the comparator is corrected is about 10 times.
When the comparator completes the calibration, CAL _ EN is set to 0, the two calibration units are closed, the voltage of the node CALP/N keeps the calibrated state, S0, S1 is turned off, S2 and S3 are turned on, signals enter the differential pair, and the comparator starts to work.
The utility model discloses a switch element and enable signal control input common mode voltage and comparative voltage, input common mode voltage when carrying out offset voltage, the electric charge that realizes the calibration unit through input signal control switch group moves, and offset voltage that main differential pair was offset to the differential pressure of input through the differential pair of calibration in the comparator, realize the offset voltage in the cancelling circuit, input comparative voltage after eliminating offset voltage, carry out the normal comparison output of comparator, through this circuit, can realize reducing by a wide margin comparator offset voltage, and do not influence the speed of comparator, the influence to the noise is also less.
The basic principles and the main features of the invention and the advantages of the invention have been shown and described above. It will be understood by those skilled in the art that the present invention is not limited to the above embodiments, and that the foregoing embodiments and descriptions are provided only to illustrate the principles of the present invention without departing from the spirit and scope of the present invention. The scope of the invention is defined by the appended claims and equivalents thereof.
Claims (8)
1. A self-calibrating comparator offset voltage cancellation circuit, comprising:
the comparator is configured to control the input common-mode voltage and the comparison voltage according to the enabling signal, and after voltage correction is carried out by connecting the common-mode voltage, the comparison signal is connected for signal comparison output;
the calibration unit is configured to be connected with two output ends OUTP and OUTN of the comparator, feed back an output signal of the comparator to the input end according to an enabling signal and counteract offset voltage;
and the switching unit is configured to realize switching input of the common mode voltage and the comparison voltage through the enabling signal.
2. The self-calibrating comparator offset voltage cancellation circuit of claim 1, wherein the comparator comprises:
the amplifying unit is configured to be a main differential pair and a correction differential pair which are connected in parallel, wherein the input end of the main differential pair is connected with the comparison signal, the input end of the correction differential pair is connected with the output signal of the calibration unit, and offset voltage of the main differential pair is offset through the voltage difference of the input end of the correction differential pair;
and the dynamic comparison unit is configured as a dynamic comparator and an output latch, is connected with the output signal of the amplification unit and is used for realizing voltage comparison output.
3. The self-calibrating comparator offset voltage cancellation circuit of claim 1, wherein the calibration unit comprises:
the input ends Vop and Von are respectively connected with two output ends OUTP and OUTN of the comparator;
an output terminal for outputting a feedback voltage to the comparator;
a first switch set configured to control charge stealing of the first charge storage capacitor by a Vop input port signal and an enable signal;
and the second switch group is configured to control the charge shift of the second charge storage capacitor through the Von input port signal and the enabling signal.
4. The self-calibrating comparator offset voltage cancellation circuit of claim 3, further comprising a third charge storage capacitor disposed in front of the output terminal, wherein the third charge storage capacitor, the first charge storage capacitor and the second charge storage capacitor change the voltage fed back to the comparator from the output terminal through charging and discharging.
5. The self-calibrating comparator offset voltage cancellation circuit according to claim 3, wherein the calibration unit includes a first calibration unit and a second calibration unit, the same, the Vop input of the first calibration unit is connected to the OUTP output terminal of the comparator, and the Von input is connected to the OUTN output terminal of the comparator; the Vop input end of the second calibration unit is connected with the OUTN output end of the comparator, and the Von input end of the second calibration unit is connected with the OUTP output end of the comparator.
6. The self-calibrating comparator offset voltage cancellation circuit of claim 3, wherein said first switch set and said second switch set use high threshold MOS transistors.
7. The self-calibrating comparator offset voltage cancellation circuit of claim 3, wherein the charge storage capacitor is of a metal-oxide-metal structure.
8. The self-calibrating comparator offset voltage cancellation circuit of claim 1, wherein the switch unit comprises a plurality of switches and a not gate, and the selection of the comparator input signal is realized by controlling the switch unit through the enable signal.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201921044002.5U CN210075200U (en) | 2019-07-05 | 2019-07-05 | Self-calibration comparator offset voltage elimination circuit |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201921044002.5U CN210075200U (en) | 2019-07-05 | 2019-07-05 | Self-calibration comparator offset voltage elimination circuit |
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| CN210075200U true CN210075200U (en) | 2020-02-14 |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110149117A (en) * | 2019-07-05 | 2019-08-20 | 成都博思微科技有限公司 | A kind of self calibration comparator imbalance voltage cancellation circuit |
| CN115173817A (en) * | 2022-09-05 | 2022-10-11 | 深圳市单源半导体有限公司 | Differential amplification circuit, error amplification circuit and trimming method thereof |
-
2019
- 2019-07-05 CN CN201921044002.5U patent/CN210075200U/en active Active
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110149117A (en) * | 2019-07-05 | 2019-08-20 | 成都博思微科技有限公司 | A kind of self calibration comparator imbalance voltage cancellation circuit |
| CN115173817A (en) * | 2022-09-05 | 2022-10-11 | 深圳市单源半导体有限公司 | Differential amplification circuit, error amplification circuit and trimming method thereof |
| CN115173817B (en) * | 2022-09-05 | 2022-12-02 | 深圳市单源半导体有限公司 | Differential amplification circuit, error amplification circuit and trimming method thereof |
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