CN108494371A - A kind of automatic calibration circuit of amplifier input offset voltage and bearing calibration - Google Patents
A kind of automatic calibration circuit of amplifier input offset voltage and bearing calibration Download PDFInfo
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- CN108494371A CN108494371A CN201810725305.7A CN201810725305A CN108494371A CN 108494371 A CN108494371 A CN 108494371A CN 201810725305 A CN201810725305 A CN 201810725305A CN 108494371 A CN108494371 A CN 108494371A
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
- H03F1/30—Modifications of amplifiers to reduce influence of variations of temperature or supply voltage or other physical parameters
- H03F1/301—Modifications of amplifiers to reduce influence of variations of temperature or supply voltage or other physical parameters in MOSFET amplifiers
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/45—Differential amplifiers
- H03F3/45071—Differential amplifiers with semiconductor devices only
- H03F3/45076—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier
- H03F3/45179—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier using MOSFET transistors as the active amplifying circuit
- H03F3/45197—Pl types
- H03F3/45206—Folded cascode stages
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
- H03F2203/45—Indexing scheme relating to differential amplifiers
- H03F2203/45134—Indexing scheme relating to differential amplifiers the whole differential amplifier together with other coupled stages being fully differential realised
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Abstract
The present invention discloses automatic calibration circuit and its bearing calibration of a kind of amplifier input offset voltage,The automatic calibration circuit first passes through the correction of comparator itself offset voltage to complete auxiliary corrective,The breadth length ratio of metal-oxide-semiconductor in the metal-oxide-semiconductor input stage correcting circuit inside amplifier is adjusted again,To realize entire amplifier input offset voltage correction,Compared with the existing technology,The present invention modifies to the differential input stage of amplifier,The equivalent breadth length ratio of input difference metal-oxide-semiconductor pair is controlled by digital control code value,Rather than lead to the output voltage numerical approach of ovefcompensated amplifier to correct the offset voltage of the input stage of amplifier,It does not need the analog voltage that one constantly adjusts and just completes correction to fully-differential amplifier offset voltage yet,Obtained respective digital control code value can be retained after correction to improve the precision of follow up amplifier work,And stop the auxiliary corrective of figure adjustment control circuit,Save power consumption.
Description
Technical field
The present invention relates to Analog Circuit Design fields, more particularly to a kind of automatically correcting for amplifier input offset voltage
Circuit and bearing calibration.
Background technology
Operational amplifier is a basic analog circuit function module, by very extensive use, in operational amplifier
Existing DC offset voltage is also by industry extensive concern, and each major company is it is also proposed that corresponding solution is all using simulation control
Mode processed is corrected DC offset voltage, the output voltage numerical approach of the mainly logical ovefcompensated amplifier of their design
Correct the input offset voltage of amplifier, however the input stage of entire operational amplifier may still introduce offset voltage.
In some amplifier application scenarios, for example, Fig. 1 is the circuit diagram of Full differential operational amplifier typical case,
In, for the positive input terminal of fully-differential amplifier by the positive input resistance input voltage vip that resistance value is R1, negative input end passes through resistance value
For the negative input resistance input voltage vin of R1；The negative output terminal of fully-differential amplifier is connected by the positive feedback resistor that resistance value is R2
Return the positive input terminal of fully-differential amplifier, negative output terminal output voltage von；The positive output end of fully-differential amplifier is by resistance value
The negative feedback resistor of R2 connects back to the negative input end of fully-differential amplifier, positive output end output voltage vop；Then fully-differential amplifier
Fully differential output voltage
.Due to fully-differential amplifier offset voltageIn the presence of the fully differential output voltage for causing amplification to exportWith differential input voltageExpectation value of magnificationIt deposits
In deviation, especially when differential input signal vip-vin amplitude script very littles, since the presence of amplifier imbalance so that imbalance is anti-
Feedthrough voltageNumerical value relative toNumerical value
It can not ignore, it is clear that prodigious error will produce to fully differential output voltage, if caused by not to lacking of proper care due to amplifier
Imbalance feedback voltageIt is corrected, then fully differential output voltageNumerical value and differential input voltageExpectation numerical value
Differ larger.
Fig. 2 is the circuit diagram of single end operational amplifier typical case, and the negative input end of difference amplifier is logical
The negative input resistance input voltage vin that resistance value is R1 is crossed, the positive input terminal of difference amplifier is by resistance value
The positive input resistance input reference voltage vref of R1, the output end of difference amplifier pass through the negative-feedback that resistance value is R2
Resistance connects back to the negative input end of difference amplifier, and the single ended output voltage of difference amplifier is, due to single-ended
The offset voltage of amplifierIn the presence of leading to the expectation value of magnification of single ended output voltage vout and differential input voltageThere are deviations, especially when single ended output voltage vout and reference voltage
When vref difference is originally little, since the presence of amplifier imbalance causesNumerical value
It is more thanNumerical value, it is clear that prodigious error will produce to single ended output voltage vout,
At this time if not to feedback voltage of lacking of proper care caused by being lacked of proper care due to amplifierIt is entangled
Just, then the expectation value of magnification of single ended output voltage vout numerical value and differential input voltageDifference is apparent.
Invention content
Since digital control approach naturally has zero quiescent dissipation and realizes simple, it is easy to it is many excellent to carry out process transplanting
Point, the thus a kind of automatic calibration circuit of amplifier input offset voltage of present invention offer and bearing calibration：
A kind of automatic calibration circuit of amplifier input offset voltage, which is characterized in that the automatic calibration circuit includes amplification
Device signal source selection circuit, amplifier circuit, comparator signal source selection circuit, comparator and digital correction control circuit；
Figure adjustment control circuit includes the comparator Enable Pin being connect with comparator signal source selection circuit, the first auxiliary school
Positive control encoded signal end and the second auxiliary corrective control encoded signal end, under correcting enabled effect in comparator imbalance,
The first auxiliary corrective that the end output of the first auxiliary corrective control encoded signal is adjusted according to the output signal of comparator controls coding
Signal and the second auxiliary corrective of the second auxiliary corrective control encoded signal end output control encoded signal, to offset comparator certainly
The offset voltage of body；Figure adjustment control circuit further includes the amplifier imbalance school being connected with amplifier signal source selection circuit
Positive Enable Pin, the first Corrective control encoded signal end and the second Corrective control encoded signal end, in the mistake for completing comparator
Adjust voltage correction after, in conjunction with comparator signal source selection circuit and amplifier signal source selection circuit collective effect, and according to than
Compared with the first Corrective control encoded signal and the second correction that the output signal of device adjusts the output of the first Corrective control encoded signal end
The the second Corrective control encoded signal for controlling the output of encoded signal end, to realize that the input stage in amplifier circuit offsets amplifier
Offset voltage；
Amplifier signal source selection circuit is used for during masking amplifier according to the amplifier offset correction Enable Pin
Correction enable signal be that amplifier circuit inputs signal to be corrected；
Amplifier circuit is the amplifier with feedback control loop, and amplifier includes metal-oxide-semiconductor input stage correcting circuit, is used for
The tune of the first Corrective control encoded signal and the second Corrective control encoded signal of the output of figure adjustment control circuit
Under section effect, by changing the conducting situation of metal-oxide-semiconductor array in parallel in metal-oxide-semiconductor input stage correcting circuit, to draw in input stage
Enter the offset voltage that offset voltage offsets the amplifier；
Comparator signal source selection circuit, for correcting Enable Pin according to the comparator imbalance during correcting comparator
Correction enable signal be that comparator inputs signal to be corrected, and controls amplifier after the offset voltage correction for completing comparator
The output signal of circuit enters comparator；
Comparator, first auxiliary corrective control encoded signal for being exported according to the figure adjustment control circuit and institute
It states the second auxiliary corrective control encoded signal and adjusts the charge discharging resisting speed of the tunable capacitor built in comparator, and generate to compare and sentence
Disconnected result；
Wherein, the first auxiliary corrective control encoded signal and second auxiliary corrective control encoded signal are that correction is compared
The n bit groups of a pair of the complementation generated during device offset voltage itself, i.e., one of n bits group increase
One default value, another n bits group then reduce identical default value；The first auxiliary corrective control coding
Signal end and second auxiliary corrective control encoded signal end are all n BITBUS networks, and n is integer；
The first Corrective control encoded signal and the second Corrective control encoded signal are masking amplifier offset voltage mistakes
The m bit groups of a pair of the complementation generated in journey, i.e., one of m bits group increase a default value, separately
One m bits group then reduces identical default value；The m bits group is increased successively according to binary weights
Add；The first Corrective control encoded signal end and the second Corrective control encoded signal end are all m BITBUS networks, and m is whole
Number.
Further, the metal-oxide-semiconductor input stage correcting circuit includes the first correction metal-oxide-semiconductor array, the second correction metal-oxide-semiconductor battle array
Row, the one zero metal-oxide-semiconductor, the 2nd 0 metal-oxide-semiconductor, cascade load circuit and current source；
The grid of one zero metal-oxide-semiconductor connects the positive input terminal of the amplifier, and the grid of the 2nd 0 metal-oxide-semiconductor connects institute
The negative input end of amplifier is stated, the drain electrode of the one zero metal-oxide-semiconductor and the 2nd 0 metal-oxide-semiconductor loads electricity with the cascade respectively
Two input terminals on road are connected, and the source electrode of the one zero metal-oxide-semiconductor and the 2nd 0 metal-oxide-semiconductor is connected with the current source
It connects so that the one zero metal-oxide-semiconductor and the 2nd 0 metal-oxide-semiconductor constitute differential pair；Wherein described the first zero metal-oxide-semiconductor and described
The size of 20 metal-oxide-semiconductors is identical；
The first correction metal-oxide-semiconductor array is in parallel with the one zero metal-oxide-semiconductor, in the first Corrective control encoded signal
Under the control action for holding the first Corrective control encoded signal of output, the first correction metal-oxide-semiconductor array described on or off
In corresponding metal-oxide-semiconductor to realize that the offset voltage of the amplifier corrects；The second correction metal-oxide-semiconductor array and described second
Zero metal-oxide-semiconductor is in parallel, the second Corrective control encoded signal for being exported at the second Corrective control encoded signal end
Under control action, corresponding metal-oxide-semiconductor is to realize the mistake of the amplifier in the second correction metal-oxide-semiconductor array described on or off
Adjust voltage correction；The size phase of wherein described first correction metal-oxide-semiconductor array and the metal-oxide-semiconductor pair of the second correction metal-oxide-semiconductor array
Deng.
Further, the first correction metal-oxide-semiconductor array includes the MOS of the m branch in parallel with the one zero metal-oxide-semiconductor
Pipe pair；The metal-oxide-semiconductor of the m branch to including m breadth length ratio according to binary weights be multiplied first correction metal-oxide-semiconductor and
The first switch metal-oxide-semiconductor that its corresponding place branch road is in series；Wherein, the source electrodes of the described first correction metal-oxide-semiconductors of m with it is described
The source electrode of one zero metal-oxide-semiconductor is connected, the grids of the described first correction metal-oxide-semiconductors of m all with the positive input terminal phase of the amplifier
The drain electrode of connection, the m first switch metal-oxide-semiconductors is connected with the drain electrode of the one zero metal-oxide-semiconductor, the m first switches
The grid of metal-oxide-semiconductor is connected with the first Corrective control encoded signal according to the signal wire that binary weights are multiplied respectively
It connects, institute is accessed for controlling the first correction metal-oxide-semiconductor that the binary weights corresponding to breadth length ratio connected in series match
State metal-oxide-semiconductor input stage correcting circuit；
The second correction metal-oxide-semiconductor array includes the metal-oxide-semiconductor pair of the m branch in parallel with the 2nd 0 metal-oxide-semiconductor；The m
The metal-oxide-semiconductor of branch is to including that m breadth length ratio corrects metal-oxide-semiconductor and its corresponding institute according to binary weights at multiple increased second
The second switch metal-oxide-semiconductor being in series on branch road；Wherein, the grids of the described second correction metal-oxide-semiconductors of m all with the amplifier
Negative input end is connected, and the source electrode of m the second correction metal-oxide-semiconductors is connected with the source electrode of the 2nd 0 metal-oxide-semiconductor, m institute
The grid for stating the second correction metal-oxide-semiconductor is all connected with the negative input end of the amplifier, the grid of the m second switch metal-oxide-semiconductors
Pole is connected with the second Corrective control encoded signal according to the signal wire that binary weights are multiplied respectively, for controlling
It is defeated to make the second correction metal-oxide-semiconductor access metal-oxide-semiconductor that the binary weights corresponding to breadth length ratio connected in series match
Enter a grade correcting circuit；
Wherein, the first correction metal-oxide-semiconductor array and the institute that identical binary weights are corresponded in the second correction metal-oxide-semiconductor array
It is identical with the breadth length ratio of the second correction metal-oxide-semiconductor to state the first correction metal-oxide-semiconductor；The binary weights are two exponential relationships；m
It is the breadth length ratio of a first correction metal-oxide-semiconductor and smaller than the breadth length ratio of the one zero metal-oxide-semiconductor, m the second correction MOS
It is the breadth length ratio of pipe and smaller than the breadth length ratio of the 2nd 0 metal-oxide-semiconductor.
Further, when the one zero metal-oxide-semiconductor and the 2nd 0 metal-oxide-semiconductor are all NMOS tube, m first corrections
Metal-oxide-semiconductor and the m first switch metal-oxide-semiconductors are all NMOS tube；One zero metal-oxide-semiconductor and the 2nd 0 metal-oxide-semiconductor are all
When PMOS tube, the m first correction metal-oxide-semiconductors and the m first switch metal-oxide-semiconductors are all PMOS tube.
Further, the comparator includes that pre-amplification circuit, offset cancellation circuit, latch cicuit and nor gate latch
Device；First output end of pre-amplification circuit and the first input end of latch cicuit are connected to first node, and the of pre-amplification circuit
Second input terminal of two output ends and latch cicuit is connected to second node；
Pre-amplification circuit has the prime amplifier for forming comparator input terminal, the load differential metal-oxide-semiconductor pair of subject clock signal control
With the metal-oxide-semiconductor as current mirror, for input signal is amplified to the amplitude that the comparator can be identified effectively；
Latch cicuit, including the phase inverter of two head and the tail interconnection accelerate multilevel iudge process with the type of attachment of positive feedback；
Nor gate latch, for storing the signal of latch cicuit output end to retain the correction number control that correction course is obtained
Code value processed, and export the multilevel iudge result to the figure adjustment control circuit as auxiliary corrective；
Offset cancellation circuit, including the first tunable capacitor array and the second tunable capacitor array, the one of the first tunable capacitor array
End is connected to first node, the other end ground connection of the first tunable capacitor array, and one end of the second tunable capacitor array is connected to the
Two nodes, the other end ground connection of the second tunable capacitor array；Wherein, the first tunable capacitor array and the second tunable capacitor array be all
Include the branch of n item parallel connections, each branch, which is connected one, to be switched and a capacitance, n switch of the first tunable capacitor array
The first auxiliary corrective by the end output of first auxiliary corrective control encoded signal controls controlling for encoded signal, and second is adjustable
Second auxiliary corrective control coding letter of the n switch of capacitor array by the end output of second auxiliary corrective control encoded signal
Number control so that the figure adjustment control circuit is according to multilevel iudge result pair the first tunable capacitor array of auxiliary corrective
It is adjusted with the second tunable capacitor array to realize the comparator itself offset voltage correction.
Further, when the input stage of the amplifier circuit is differential pair, the amplifier is fully-differential amplifier,
Two difference output end is connected by feedback resistance with its opposite polarity differential input end；
Comparator signal source selection circuit includes the negative input end in auxiliary common-mode signal source and the comparator to be corrected
There is the first switch and the second switch of common end and there is the third of common end to switch and the with the positive input terminal of the comparator
Four switches, wherein the other end of second switch connects the negative output terminal of the fully-differential amplifier, and other the one of the 4th switch
End connects the positive output end of the fully-differential amplifier, and the other end of other end and the third switch of first switch, which all connects, to be waited for
The auxiliary common-mode signal source of correction, for controlling institute under correcting the correction enable signal effect of Enable Pin in the comparator imbalance
It states comparator and enters or exit offset voltage auxiliary corrective process；
Amplifier signal source selection circuit includes the positive input terminal in common-mode signal source and the amplifier circuit to be corrected
Have common end the 5th switchs and the 6th switchs and have with the negative input end of the amplifier circuit the 7th switch of common end
With the 8th switch, wherein the other end of the 6th switch connects the positive input terminal of the automatic calibration circuit, the 8th switch it is another
Outer one end connects the negative input end of the automatic calibration circuit, and the other end that the other end of the 5th switch and the 7th switch all connects
Common-mode signal source is received, for controlling the amplification under the effect of the correction enable signal of the amplifier offset correction Enable Pin
Device enters or exits offset voltage correction course.
Further, when the input stage of the amplifier circuit is single-ended, the amplifier is difference amplifier, defeated
Outlet is connected by feedback resistance with its negative input end；
Comparator signal source selection circuit includes the first switch for having common end with the positive input terminal of the comparator and
Two switches, wherein the other end of second switch connects the output end of the difference amplifier, and the other end of first switch connects
The reference voltage end outside the automatic calibration circuit is connect, the enabled letter of the correction for correcting Enable Pin in the comparator imbalance
Number lower control comparator of effect enters or exits imbalance auxiliary corrective process；
Amplifier signal source selection circuit include with the amplifier circuit negative input end have common end the 5th switch and
6th switch, wherein the other end of the 6th switch connects the positive input terminal of the automatic calibration circuit, the 5th switch it is another
Outer one end connects the reference voltage end outside the automatic calibration circuit, in the school of the amplifier offset correction Enable Pin
The positive enable signal effect lower control amplifier enters or exits offset correction process.
A kind of auto-correction method of amplifier input offset voltage, the auto-correction method are automatically corrected based on described
Circuit, including：
After the correction Enable Pin of the figure adjustment control circuit sets high level, the figure adjustment control circuit described first controls institute
It is high level to state comparator imbalance correction Enable Pin, and the output end of the comparator input terminal and the amplifier is disconnected,
The comparator imbalance correction terminates the output signal that foregoing description comparator does not receive the amplifier, then in the comparison
Under the action of device signal source selection circuit, the positive-negative input end of the comparator all accesses the auxiliary source to be corrected,
First auxiliary corrective is controlled encoded signal by the figure adjustment control circuit simultaneously and second auxiliary corrective controls
Encoded signal is all disposed within mid-scale value, starts the correction course to itself offset voltage of the comparator, i.e., described to put
The auxiliary corrective process of big device；The corresponding first auxiliary corrective control encoded signal of wherein described mid-scale value and described
Second auxiliary corrective controls the extreme higher position one of encoded signal, remaining position zero；
If there are the phases that itself offset voltage, the figure adjustment control circuit are exported according to the comparator for the comparator
The first auxiliary corrective control encoded signal is adjusted when the multilevel iudge fructufy answered and second auxiliary corrective control is compiled
Code signal is adjusted the capacitance of the first tunable capacitor array and the second tunable capacitor array, passes through introducing
Offset voltage existing for comparator itself described in voltage offset is corrected, until first auxiliary corrective controls encoded signal in M
The correction of itself offset voltage of the comparator terminates when circulation change between M-1, i.e., the described automatic calibration circuit terminates to assist
Correction course；The numerical value M of the wherein described first auxiliary corrective control encoded signal is used for weighing the correction accuracy of the comparator；
After the comparator itself offset voltage correction, the figure adjustment control circuit controls the comparator imbalance school
Positive Enable Pin is low level, and the comparator input terminal is connect with the output end of the amplifier to realize that the comparator connects
The output signal of the amplifier is received, it is high level then to control the amplifier Enable Pin, then in the amplifier signal source
Under the action of selection circuit, the positive-negative input end of the amplifier all accesses the signal source to be corrected, while the digital school
The first Corrective control encoded signal and the second Corrective control encoded signal are all disposed within benchmark and carved by positive control circuit
Angle value starts the correction course of the offset voltage to the amplifier；Wherein, the reference graduation value indicates first correction
The maximum metal-oxide-semiconductor of binary weights is corresponded in metal-oxide-semiconductor array and the second correction metal-oxide-semiconductor array place branch is all connected,
And remaining metal-oxide-semiconductor is when being turned off place branch, corresponding the first Corrective control encoded signal and second correction
Control the binary system array of encoded signal；
If there are offset voltage, the figure adjustment control circuits to be exported according to the comparator corresponding for the amplifier
The first Corrective control encoded signal and the second Corrective control encoded signal are adjusted when multilevel iudge fructufy, to described
The break-make of first correction metal-oxide-semiconductor array and the second correction metal-oxide-semiconductor array is adjusted, and introduces and corrects voltage in the amplification
The input stage of device offsets offset voltage existing for original, until the first Corrective control encoded signal recycles change between N and N-1
The offset voltage of amplifier correction terminates when change；The numerical value of N of the wherein described first Corrective control encoded signal is used for weighing institute
State the correction accuracy of amplifier.
Further, the bearing calibration of the comparator includes：
When the comparator has negative offset voltage, the multilevel iudge result of the comparator output is low level, then described
First auxiliary corrective control encoded signal subtracts one on the basis of the mid-scale value, the second auxiliary corrective control coding
Signal adds one on the basis of the mid-scale value, and the first auxiliary corrective control encoded signal control described first is adjustable
The capacitance that capacitor array accesses the first node reduces, and second auxiliary corrective control encoded signal control described second
The capacitance that tunable capacitor array accesses the second node increases so that the voltage decrease speed of the first node is faster than described
The voltage decrease speed of second node is equivalent to and introduces a positive differential voltage to balance out unborn negative imbalance electricity
Pressure；
When there are positive offset voltages for the comparator, then the multilevel iudge result of the comparator output is high level, then institute
It states the first auxiliary corrective control encoded signal and adds one on the basis of the mid-scale value, the second auxiliary corrective control is compiled
Code signal subtracts one on the basis of the mid-scale value, and the first auxiliary corrective control encoded signal control described first can
The capacitance that capacitor array accesses the first node is adjusted to increase, and second auxiliary corrective control encoded signal control described the
The capacitance that two tunable capacitor arrays access the second node reduces so that the voltage decrease speed of the first node is slower than institute
The voltage decrease speed for stating second node is equivalent to and introduces a negative differential voltage to balance out unborn positive imbalance
Voltage.
Further, all it is in the parallel branch of the first correction metal-oxide-semiconductor array and the second correction metal-oxide-semiconductor array
NMOS tube clock synchronization, the first correction metal-oxide-semiconductor array are the first correction NMOS tube array, and the first correction metal-oxide-semiconductor is first
NMOS tube is corrected, the second correction metal-oxide-semiconductor array is the second correction NMOS tube array, and the second correction metal-oxide-semiconductor is second
Correct NMOS tube；The bearing calibration of the amplifier includes：
When the amplifier has negative offset voltage, the multilevel iudge result of the comparator output is low level, described the
One Corrective control encoded signal adds one on the basis of the reference graduation value, and the second Corrective control encoded signal is described
Subtract one on the basis of reference graduation value, the first Corrective control encoded signal corresponds in the first correction NMOS tube array of control
The equivalent breadth length ratio for the first correction NMOS tube that grid is connected with the amplifier positive input terminal increases, the second correction control
Encoded signal processed corresponds to grid is connected with the amplifier negative input end in the second correction NMOS tube array controlled second
The equivalent breadth length ratio for correcting NMOS tube reduces so that the input stage correcting circuit exports positive differential voltage, to described
The input stage of amplifier corrects unborn negative offset voltage；
When the amplifier is there are positive offset voltage, the multilevel iudge result of the comparator output is high level, described the
One Corrective control encoded signal subtracts one on the basis of the reference graduation value, and the second control correction signal is in the benchmark
Add one on the basis of scale value, the first Corrective control encoded signal corresponds to grid in the first correction NMOS tube array controlled
The equivalent breadth length ratio for the first correction NMOS tube being connected with the amplifier positive input terminal reduces, and second Corrective control is compiled
Code signal corresponds to the second of control and corrects the second correction that grid in NMOS tube array is connected with the amplifier negative input end
The equivalent breadth length ratio of NMOS tube increases so that the negative differential voltage of the input stage correcting circuit output, in the amplification
The input stage of device corrects unborn positive offset voltage.
Further, all it is in the parallel branch of the first correction metal-oxide-semiconductor array and the second correction metal-oxide-semiconductor array
PMOS tube clock synchronization, the first correction metal-oxide-semiconductor array are the first correction PMOS tube array, and the first correction metal-oxide-semiconductor is first
PMOS tube is corrected, the second correction metal-oxide-semiconductor array is the second correction PMOS tube array, and the second correction metal-oxide-semiconductor is second
Correct PMOS tube；The bearing calibration of the amplifier includes：
When the amplifier has negative offset voltage, the multilevel iudge result of the comparator output is low level, described the
One Corrective control encoded signal subtracts one on the basis of the reference graduation value, and the second Corrective control encoded signal is described
Add one on the basis of reference graduation value, the first Corrective control encoded signal corresponds in the first correction PMOS tube array of control
The equivalent breadth length ratio for the first correction PMOS tube that grid is connected with the amplifier positive input terminal increases, the second correction control
Encoded signal processed corresponds to grid is connected with the amplifier negative input end in the second correction PMOS tube array controlled second
The equivalent breadth length ratio for correcting PMOS tube reduces so that the input stage correcting circuit exports positive differential voltage, to described
The input stage of amplifier corrects unborn negative offset voltage；
When the amplifier is there are positive offset voltage, the multilevel iudge result of the comparator output is high level, described the
One Corrective control encoded signal adds one on the basis of the reference graduation value, and the second control correction signal is in the benchmark
Subtract one on the basis of scale value, the first Corrective control encoded signal corresponds to grid in the first correction PMOS tube array controlled
The equivalent breadth length ratio for the first correction PMOS tube being connected with the amplifier positive input terminal reduces, and second Corrective control is compiled
Code signal corresponds to the second of control and corrects the second correction that grid in PMOS tube array is connected with the amplifier negative input end
The equivalent breadth length ratio of PMOS tube increases so that the negative differential voltage of the input stage correcting circuit output, in the amplification
The input stage of device corrects unborn positive offset voltage.
Further, all it is in the parallel branch of the first correction metal-oxide-semiconductor array and the second correction metal-oxide-semiconductor array
NMOS tube clock synchronization, the corresponding reference graduation value are the first correction MOS by the corresponding binary system array of inversion operation
All it is PMOS tube to the corresponding reference graduation value in the parallel branch of pipe array and the second correction metal-oxide-semiconductor array；
Wherein, the amplifier can be fully-differential amplifier that input stage is differential pair or input stage is single-ended differential amplification
Device.
Compared with the existing technology, the correction course for the entire offset voltage that technical solution of the present invention is provided all is to pass through prison
Result is exported depending on the comparator and adjusts respective digital control code, is not needed analog voltage that one constantly adjusts and is just completed pair
The correction of offset voltage of amplifier, after correction, it is only necessary to retain obtained respective digital and control code value, originally
Correction auxiliary circuit can close to save power consumption.
The automatic calibration circuit is completely suitable for the single-ended amplifier offset voltage school that input stage is difference NMOS tube pair
Just, input stage is that the fully-differential amplifier offset voltage of difference NMOS tube pair corrects, and input stage is the list of difference PMOS tube pair
It is that the fully-differential amplifier offset voltage of difference PMOS tube pair corrects to hold offset voltage of amplifier correction, input stage, these four are put
Big device form covers the application mode of most amplifiers substantially, has a wide range of application.
The automatic calibration circuit realizes that offset voltage automatically corrects in digital form completely, the correction accuracy of offset voltage
It can be by being directly adjusted realization to the breadth length ratio size of input stage MOS, rather than to amplifier output signal with range
Processing realization is carried out, extension, therefore circuit after correction are easy, can be applied to the very small situation of amplifier input voltage difference,
The application range of this alignment technique is very big.After correction, correction auxiliary circuit can completely close, and quiescent dissipation is small, and
Correction course controls in digital form, reduces noise jamming.
The other of the present invention is specifically suggested with preferred aspect in appended independence and dependent claims.Subordinate
The feature of claim can with the features of independent claims suitably according to those of clearly proposed in claim
The different combination of combination is combined.
Description of the drawings
Fig. 1 is the circuit diagram of Full differential operational amplifier typical case；
Fig. 2 is the circuit diagram of single end operational amplifier typical case；
Fig. 3 is a kind of automatic calibration circuit topological structure signal of amplifier input offset voltage provided in an embodiment of the present invention
Figure；
Fig. 4 is NMOS tube input stage correcting circuit schematic diagram in the embodiment of the present invention；
Fig. 5 is PMOS tube input stage correcting circuit schematic diagram in the embodiment of the present invention；
Fig. 6 is that input stage is that the fully-differential amplifier offset voltage of NMOS tube differential pair automatically corrects electricity in the embodiment of the present invention
Road schematic diagram；
Fig. 7 is that input stage is that the fully-differential amplifier offset voltage of PMOS tube differential pair automatically corrects electricity in the embodiment of the present invention
Road schematic diagram；
Fig. 8 is that input stage is that NMOS tube illustrates the automatic calibration circuit of single-ended amplifier offset voltage in the embodiment of the present invention
Figure；
Fig. 9 is that input stage is that PMOS tube illustrates the automatic calibration circuit of single-ended amplifier offset voltage in the embodiment of the present invention
Figure；
Figure 10 be in the embodiment of the present invention input stage be NMOS tube pair automatic calibration circuit in figure adjustment control circuit letter
The oscillogram of number port；
Figure 11 be in the embodiment of the present invention input stage be PMOS tube pair automatic calibration circuit in figure adjustment control circuit letter
The oscillogram of number port；
Figure 12 is the internal circuit schematic diagram of comparator in the embodiment of the present invention.
Specific implementation mode
The specific implementation mode of the present invention is described further below in conjunction with the accompanying drawings：
As shown in figure 3, a kind of automatic calibration circuit of amplifier input offset voltage, including amplifier signal source selection circuit,
Amplifier circuit, comparator signal source selection circuit, comparator and digital correction control circuit.
Figure adjustment control circuit, include the comparator Enable Pin cal_cmp being connect with comparator signal source selection circuit,
First auxiliary corrective controls encoded signal end amp1 and the second auxiliary corrective control encoded signal end amp2.Figure adjustment control electricity
The logic of control comparator imbalance voltage correction is in road：When comparator imbalance correction Enable Pin cal_cmp is high level, number
Word correction control circuit is defeated according to output signal v_cmp adjustment the first auxiliary corrective control encoded signals end cmp_dp of comparator
The the first auxiliary corrective control encoded signal cmp_dp [n-1 gone out:0] and the second auxiliary corrective control encoded signal end cmp_dm is defeated
The the second auxiliary corrective control encoded signal cmp_dm [n-1 gone out:0], to offset the offset voltage of comparator itself；Wherein, institute
State the first auxiliary corrective control encoded signal cmp_dp [n-1:0] and second auxiliary corrective controls encoded signal cmp_dm
[n-1:0] be a pair of complementary n bit groups during correcting comparator, i.e., one of n bits group increase
One default value, another n bits group then reduce identical default value；The first auxiliary corrective control coding
Signal end cmp_dp and second auxiliary corrective control encoded signal end cmp_dm is n BITBUS networks, and n is integer.
Figure adjustment control circuit, which further includes the amplifier offset correction being connected with amplifier signal source selection circuit, to be made
Energy end cal_amp, the first Corrective control encoded signal end amp1 and the second Corrective control encoded signal end amp2, figure adjustment control
The logic that offset voltage of amplifier corrects is controlled in circuit processed is：After completing itself offset voltage correction of comparator, compare
Device offset correction Enable Pin cal_cmp sets low level, and amplifier offset correction Enable Pin cal_amp sets high level, and according to than
Compared with the first Corrective control encoded signal of output signal v_cmp adjustment the first Corrective control encoded signal end amp1 outputs of device
amp1[m:1] and the second Corrective control encoded signal amp2 [m of the second Corrective control encoded signal end amp2 outputs:1], with
The input stage of amplifier circuit offsets offset voltage Voffset；The wherein described first Corrective control encoded signal amp1 [m:1] and
The second Corrective control encoded signal amp2 [m:1] be during masking amplifier offset voltage a pair of complementary positions m two into
Array processed, i.e., one of m bits group increase a default value, another m bits group then reduces identical
Default value；Secondary low level in the m bits group is successively increased to highest order according to binary weights；It is described
First Corrective control encoded signal end amp1 and the second Corrective control encoded signal end amp2 is m BITBUS networks, and m is whole
Number.
Amplifier signal source selection circuit is used for during masking amplifier offset voltage, when the amplifier loses
When the enable signal of the positive Enable Pin cal_amp of adjustment is high, offset voltage of the figure adjustment control circuit control into amplifier
Correction course inputs signal to be corrected for amplifier circuit；When the enabled letter of the amplifier offset correction Enable Pin cal_amp
Number for it is low when, stop amplifier offset voltage correction.
Amplifier circuit is the amplifier with feedback control loop, and amplifier includes metal-oxide-semiconductor input stage correcting circuit, is used for
In the first Corrective control encoded signal amp1 [m of figure adjustment control circuit output:1] it is compiled with second Corrective control
Code signal amp2 [m:1] it under adjustment effect, is led by changing metal-oxide-semiconductor array in parallel in metal-oxide-semiconductor input stage correcting circuit
Understanding and considerate condition offsets the offset voltage Voffset of the amplifier to introduce offset voltage in input stage.The metal-oxide-semiconductor input stage
Correcting circuit includes the first correction metal-oxide-semiconductor array, the second correction metal-oxide-semiconductor array, the one zero metal-oxide-semiconductor, the 2nd 0 metal-oxide-semiconductor, cascade
Load circuit and current source；One zero metal-oxide-semiconductor and the 2nd 0 metal-oxide-semiconductor constitute differential pair, and the one zero metal-oxide-semiconductor
It is identical with the size of the 2nd 0 metal-oxide-semiconductor；The first correction metal-oxide-semiconductor array is in parallel with the one zero metal-oxide-semiconductor, uses
Under the control action of the first Corrective control encoded signal exported at the first Corrective control encoded signal end, conducting
Or in shutdown the first correction metal-oxide-semiconductor array corresponding metal-oxide-semiconductor to realize that the offset voltage of the amplifier corrects；It is described
Second correction metal-oxide-semiconductor array is in parallel with the 2nd 0 metal-oxide-semiconductor, for what is exported at the second Corrective control encoded signal end
It is corresponding in the second correction metal-oxide-semiconductor array described on or off under the control action of the second Corrective control encoded signal
Metal-oxide-semiconductor is to realize that the offset voltage of the amplifier corrects；The wherein described first correction metal-oxide-semiconductor array is corrected with described second
The metal-oxide-semiconductor pair of metal-oxide-semiconductor array it is equal sized.
Comparator signal source selection circuit is used for during correcting comparator itself offset voltage according to the comparison
The enable signal of device offset correction Enable Pin cal_cmp is comparator input signal to be corrected, and in the imbalance for completing comparator
The output signal that amplifier circuit is controlled after voltage correction enters comparator.
Comparator, first auxiliary corrective for being exported according to the figure adjustment control circuit control encoded signal
cmp_dp[n-1:0] and second auxiliary corrective controls encoded signal cmp_dm [n-1:0] it adjusts adjustable built in comparator
The charge discharging resisting speed of capacitance, and output comparator corrects as a result, and in masking amplifier during correcting comparator
Output amplifier corrects result in the process.
As shown in figure 4, as an embodiment of the present invention, when the metal-oxide-semiconductor input stage correcting circuit has NMOS tube
The metal-oxide-semiconductor array of formation, then the input stage correcting circuit is NMOS tube input stage correcting circuit；NMOS tube input stage school
Positive circuit includes the first correction NMOS tube array, the second correction NMOS tube array, the one zero NMOS tube, the 2nd 0 NMOS tube, grade
Join load circuit and current source isrc；The grid of the one zero NMOS tube NM10 connects the positive input terminal v+ of the amplifier,
The grid of the 2nd 0 NMOS tube NM20 connects the negative input end v- of the amplifier, the one zero NMOS tube NM10 and institute
The drain electrode for stating the 2nd 0 NMOS tube NM20 is connected with two input terminals of the cascade load circuit respectively, and the described 1st
The source electrode of NMOS tube NM10 and the 2nd 0 NMOS tube NM20 are connected with the anode of the current source so that the described 1st
NMOS tube NM10 and the 2nd 0 NMOS tube NM20 constitutes differential pair；The wherein described the first zero NMOS tube NM10 and described second
The size of zero NMOS tube NM20 is identical；The first correction NMOS tube array is in parallel with the one zero NMOS tube NM10,
The first Corrective control encoded signal end amp1 is amp_dp, the first correction control of output in embodiments of the present invention
Encoded signal amp1 [m processed:1] it is in embodiments of the present invention amp_dp [m:1], in the first Corrective control encoded signal
amp_dp[m:1] under control action, the first correction NMOS tube described on or off is to realize the imbalance electricity of the amplifier
Pressure correction；The second correction NMOS tube array is in parallel with the 2nd 0 NMOS tube NM20, the second Corrective control coding
Signal end amp2 is amp_dm, the second Corrective control encoded signal amp2 [m of output in embodiments of the present invention:1]
It is amp_dm [m in embodiments of the present invention:1], in the second Corrective control encoded signal amp_dm [m:1] control is made
Under, the second correction NMOS tube is to realize the correction of the offset voltage Voffset of the amplifier described on or off；Wherein
It is symmetrical circuit structure, their metal-oxide-semiconductor pair that the first correction NMOS tube array corrects NMOS tube array with described second
Equivalent breadth length ratio W/L it is equal.
As shown in figure 4, as an embodiment of the present invention, the first correction NMOS tube array includes and described first
The NMOS tube pair of m branch of zero NMOS tube parallel connection；The NMOS tube of the m branch is to including m breadth length ratio according to binary system
The first correction NMOS tube that weight is multiplied, respectively the one one NMOS tube NM11, the one or two NMOS tube NM12, the one or three
NMOS tube NM13 ..., the first m NMOS tubes NM1m wherein, the breadth length ratio of the one or two NMOS tube NM12 is the one one NMOS tube NM11
2 times, the breadth length ratio of the one or three NMOS tube NM13 is 2 times of the one or two NMOS tube NM12, then the width of the first m NMOS tubes NM1m
Long ratio is 2^m times of the one one NMOS tube NM11, i.e. the one one NMOS tube NM11, the one or two NMOS tube NM12, the one or three NMOS
Pipe NM13 ..., the breadth length ratio of the first m NMOS tubes NM1m be according to binary weights in the first Corrective control encoded signal
It is increased at multiple, but the one one NMOS tube NM11, the one or two NMOS tube NM12, the one or three NMOS tube NM13 ..., the first m
The sum of breadth length ratio of NMOS tube NM1m is small relative to the breadth length ratio of the one zero NMOS tube NM10, because of the mistake of the amplifier
Adjust voltage it is little, institute for offset voltage correct NMOS tube breadth length ratio be configured smaller.
The NMOS tube of the m branch is to further including that the corresponding place branch road of the first correction metal-oxide-semiconductor is in series
First switch NMOS tube, the respectively the 1st switch NMOS tube NC11, the one or two switch NMOS tube NC12, the one or three switch NMOS
Pipe NC13 ..., the first m switches NMOS tube NC1m be switch control action NMOS tube, wherein the first one switches NMOS tube
The grid control signal of NC11 is DP<1>, that is, correspond to the lowest weightings in the first Corrective control encoded signal, described
The grid control signal of one or two switch NMOS tube NC12 is DP<2>, weight is DP<1>2 times, and so on, the first m
The grid control signal for switching NMOS tube NC1m is DP<m>, weight is 2^m.Wherein, m described first correct NMOS tube
Grid is all connected with the positive input terminal v+ of the amplifier, and the grids of m first switch NMOS tubes is respectively with described the
It is connected according to the signal wire that binary weights are multiplied in one Corrective control encoded signal, for controlling width connected in series
It is long to access the NMOS tube input stage correcting circuit than the first correction NMOS tube that corresponding binary weights match.
As shown in figure 4, the second correction NMOS tube array includes the m branch in parallel with the 2nd 0 NMOS tube
NMOS tube pair；Second correction of the NMOS tube of the m branch to being multiplied according to binary weights including m breadth length ratio
NMOS tube, respectively the 2nd 1 NMOS tube NM21, the two or two NMOS tube NM22, the two or three NMOS tube NM23 ..., the 2nd m NMOS
Wherein, the breadth length ratio of the two or two NMOS tube NM22 is 2 times of the 2nd 1 NMOS tube NM21 to pipe NM2m, the two or three NMOS tube NM23's
Breadth length ratio is 2 times of the two or two NMOS tube NM22, then the breadth length ratio of the 2nd m NMOS tubes NM2m is the 2 of the 2nd 1 NMOS tube NM21
^m times, i.e. the 2nd 1 NMOS tube NM21, the two or two NMOS tube NM22, the two or three NMOS tube NM23 ..., the 2nd m NMOS tubes NM2m
Breadth length ratio be increased at multiple according to binary weights in the second Corrective control encoded signal, due to first school
It is symmetrical circuit structure that positive NMOS tube array corrects NMOS tube array with described second, so the 2nd 1 NMOS tube NM21, the
Two or two NMOS tube NM22, the two or three NMOS tube NM23 ..., the size of the 2nd m NMOS tubes NM2m and the one one NMOS tube NM11,
One or two NMOS tube NM12, the one or three NMOS tube NM13 ..., the size of the first m NMOS tubes NM1m correspond it is equal, still
2nd 1 NMOS tube NM21, the two or two NMOS tube NM22, the two or three NMOS tube NM23 ..., the width of the 2nd m NMOS tubes NM2m it is long
Than the sum of relative to the smaller of the 2nd 0 NMOS tube NM20 because the offset voltage of the amplifier is little, institute for
The wide length of NMOS tube of offset voltage correction is arranged smaller.
The NMOS tube of the m branch is to further including that the corresponding place branch road of the second correction metal-oxide-semiconductor is in series
Second switch NMOS tube, the respectively the 2nd 1 switch NMOS tube NC21, the two or two switch NMOS tube NC22, the two or three switch NMOS
Pipe NC23 ..., the 2nd m switch NMOS tube NC2m be switch control action NMOS tube, size with the 1st switch NMOS tube
NC11, the one or two switch NMOS tube NC12, the one or three switch NMOS tube NC13 ..., the first m switch NMOS tubes NC1m corresponds
It is equal.The grid control signal of the wherein described the second one switch NMOS tubes NC21 is DM<1>, that is, correspond to the second correction control
The grid control signal of lowest weightings in encoded signal processed, the two or the two switch NMOS tube NC22 is DM<2>, weight is
DM<1>2 times, and so on, the grid control signal of the 2nd m switch NMOS tube NC2m is DM<m>, weight is 2^m.
Wherein, the grid of m the second correction NMOS tubes is all connected with the negative input end v- of the amplifier, m described second
Switch the grid of NMOS tube respectively with the signal that is multiplied according to binary weights in the second Corrective control encoded signal
Line is connected, the second correction NMOS tube to match for controlling the binary weights corresponding to breadth length ratio connected in series
Access the NMOS tube input stage correcting circuit.Digital control code DP above-mentioned<m:1>With DM<m:1>It is closed in binary numeral
It is complementary relationship to fasten, when realizing that the corresponding NMOS breadth length ratios of the digital control code of one of which increase, then another set of number control
The corresponding NMOS breadth length ratios of code processed reduce the effect of identical change amount, to correct the original offset voltage of amplifier input stage.
As shown in figure 5, as an embodiment of the present invention, when the metal-oxide-semiconductor input stage correcting circuit has PMOS tube
The metal-oxide-semiconductor array of formation, then the input stage correcting circuit is PMOS tube input stage correcting circuit；PMOS tube input stage school
Positive circuit includes the first correction PMOS tube array, the second correction PMOS tube array, the one zero PMOS tube, the 2nd 0 PMOS tube, grade
Join load circuit and current source isrc；The grid of the one zero PMOS tube PM10 connects the positive input terminal v+ of the amplifier,
The grid of the 2nd 0 PMOS tube PM20 connects the negative input end v- of the amplifier, the one zero PMOS tube PM10 and institute
The drain electrode for stating the 2nd 0 PMOS tube PM20 is connected with two input terminals of the cascade load circuit respectively, and the described 1st
The source electrode of PMOS tube PM10 and the 2nd 0 PMOS tube PM20 are connected with the cathode of the current source, and the current source is just
Pole connects supply voltage end VCC so that the one zero PMOS tube PM10 and the 2nd 0 PMOS tube PM20 constitutes differential pair；
The wherein described the first zero PMOS tube PM10 is identical with the size of the 2nd 0 PMOS tube PM20；The first correction PMOS
Pipe array is in parallel with the one zero PMOS tube PM10, and the first Corrective control encoded signal end amp1 is in the embodiment of the present invention
In be amp_dp_n, output the first Corrective control encoded signal amp1 [m:1] it is in embodiments of the present invention amp_
dp_n[m:1], in the first Corrective control encoded signal amp_dp_n [m:1] under control action, described on or off
First correction PMOS tube is to realize that the offset voltage of the amplifier corrects；The second correction PMOS tube array and described second
Zero PMOS tube PM20 is in parallel, and the second Corrective control encoded signal end amp2 is amp_dm_n in embodiments of the present invention,
The second Corrective control encoded signal amp2 [m of output:1] it is in embodiments of the present invention amp_dm_n [m:1], in institute
State the second Corrective control encoded signal amp_dm_n [m:1] under control action, the second correction PMOS tube described on or off
To realize the correction of the offset voltage Voffset of the amplifier；The wherein described first correction PMOS tube array and described second
It is symmetrical circuit structure to correct PMOS tube array, and the equivalent breadth length ratio W/L of their metal-oxide-semiconductor pair is equal.
As shown in figure 4, as an embodiment of the present invention, the first correction PMOS tube array includes and described first
The PMOS tube pair of m branch of zero PMOS tube parallel connection；The PMOS tube of the m branch is to including m breadth length ratio according to binary system
The first correction PMOS tube that weight is multiplied, respectively the one one PMOS tube PM11, the one or two PMOS tube PM12, the one or three
PMOS tube PM13 ..., the first m PMOS tube PM1m wherein, the breadth length ratio of the one or two PMOS tube PM12 is the one one PMOS tube PM11
2 times, the breadth length ratio of the one or three PMOS tube PM13 is 2 times of the one or two PMOS tube PM12, then the width of the first m PMOS tube PM1m
Long ratio is 2^m times of the one one PMOS tube PM11, i.e. the one one PMOS tube PM11, the one or two PMOS tube PM12, the one or three PMOS
Pipe PM13 ..., the breadth length ratio of the first m PMOS tube PM1m be according to binary weights in the first Corrective control encoded signal
It is increased at multiple, but the one one PMOS tube PM11, the one or two PMOS tube PM12, the one or three PMOS tube PM13 ..., the first m
The sum of breadth length ratio of PMOS tube PM1m is small relative to the breadth length ratio of the one zero PMOS tube PM10, because of the mistake of the amplifier
Adjust voltage it is little, institute for offset voltage correct the wide length of PMOS tube be configured smaller.
The PMOS tube of the m branch is to further including that the corresponding place branch road of the first correction metal-oxide-semiconductor is in series
First switch PMOS tube, the respectively the 1st switch PMOS tube PC11, the one or two switch PMOS tube PC12, the one or three switch PMOS
Pipe PC13 ..., the first m switches PMOS tube PC1m be switch control action PMOS tube, wherein the first one switches PMOS tube
The grid control signal of PC11 is DP<1>, that is, correspond to the lowest weightings in the first Corrective control encoded signal, described
The grid control signal of one or two switch PMOS tube PC12 is DP<2>, weight is DP<1>2 times, and so on, the first m
The grid control signal for switching PMOS tube PC1m is DP<m>, weight is 2^m.Wherein, m described first correct PMOS tube
Grid is all connected with the positive input terminal v+ of the amplifier, and the grid of the m first switch PMOS tube is respectively with described the
It is connected according to the signal wire that binary weights are multiplied in one Corrective control encoded signal, for controlling width connected in series
It is long to access the PMOS tube input stage correcting circuit than the first correction PMOS tube that corresponding binary weights match.
As shown in figure 4, the second correction PMOS tube array includes the m branch in parallel with the 2nd 0 PMOS tube
PMOS tube pair；Second correction of the PMOS tube of the m branch to being multiplied according to binary weights including m breadth length ratio
PMOS tube, respectively the 2nd 1 PMOS tube PM21, the two or two PMOS tube PM22, the two or three PMOS tube PM23 ..., the 2nd m PMOS
Wherein, the breadth length ratio of the two or two PMOS tube PM22 is 2 times of the 2nd 1 PMOS tube PM21 to pipe PM2m, the two or three PMOS tube PM23's
Breadth length ratio is 2 times of the two or two PMOS tube PM22, then the breadth length ratio of the 2nd m PMOS tube PM2m is the 2 of the 2nd 1 PMOS tube PM21
^m times, i.e. the 2nd 1 PMOS tube PM21, the two or two PMOS tube PM22, the two or three PMOS tube PM23 ..., the 2nd m PMOS tube PM2m
Breadth length ratio be increased at multiple according to binary weights in the second Corrective control encoded signal, due to first school
It is symmetrical circuit structure that positive PMOS tube array corrects PMOS tube array with described second, so the 2nd 1 PMOS tube PM21, the
Two or two PMOS tube PM22, the two or three PMOS tube PM23 ..., the size of the 2nd m PMOS tube PM2m and the one one PMOS tube PM11,
One or two PMOS tube PM12, the one or three PMOS tube PM13 ..., the size of the first m PMOS tube PM1m correspond it is equal, still
2nd 1 PMOS tube PM21, the two or two PMOS tube PM22, the two or three PMOS tube PM23 ..., the width of the 2nd m PMOS tube PM2m it is long
Than the sum of relative to the smaller of the 2nd 0 PMOS tube PM20 because the offset voltage of the amplifier is little, institute for
The wide length of PMOS tube of offset voltage correction is arranged smaller.
The PMOS tube of the m branch is to further including that the corresponding place branch road of the second correction metal-oxide-semiconductor is in series
Second switch PMOS tube, the respectively the 2nd 1 switch PMOS tube PC21, the two or two switch PMOS tube PC22, the two or three switch PMOS
Pipe PC23 ..., the 2nd m switch PMOS tube PC2m be switch control action PMOS tube, size with the 1st switch PMOS tube
PC11, the one or two switch PMOS tube PC12, the one or three switch PMOS tube PC13 ..., the first m switch PMOS tube PC1m corresponds
It is equal.The grid control signal of the wherein described the second one switch PMOS tube PC21 is DM<1>, that is, correspond to the second correction control
The grid control signal of lowest weightings in encoded signal processed, the two or the two switch PMOS tube PC22 is DM<2>, weight is
DM<1>2 times, and so on, the grid control signal of the 2nd m switch PMOS tube PC2m is DM<m>, weight is 2^m.
Wherein, the grid of m the second correction PMOS tube is all connected with the negative input end v- of the amplifier, m described second
Switch the grid of PMOS tube respectively with the signal that is multiplied according to binary weights in the second Corrective control encoded signal
Line is connected, the second correction PMOS tube to match for controlling the binary weights corresponding to breadth length ratio connected in series
Access the PMOS tube input stage correcting circuit.Digital control code DP above-mentioned<m:1>With DM<m:1>It is closed in binary numeral
It is complementary relationship to fasten, when realizing that the corresponding PMOS breadth length ratios of the digital control code of one of which increase, then another set of number control
The corresponding PMOS breadth length ratios of code processed reduce the effect of identical change amount, to correct the original offset voltage of amplifier input stage.
As shown in figure 12, the comparator includes that pre-amplification circuit, offset cancellation circuit, latch cicuit and nor gate latch
Device；First output end ON1 of pre-amplification circuit and the first input end FP of latch cicuit are connected to first node vn2, pre-amplification
The second output terminal OP1 of circuit and the second input terminal FN of latch cicuit are connected to second node vp2.
Pre-amplification circuit has the prime amplifier for forming comparator input terminal, the load differential of subject clock signal Vlatch controls
Metal-oxide-semiconductor pair and metal-oxide-semiconductor as current mirror, for input signal is amplified to the amplitude that the comparator can be identified effectively；
Pre-amplification circuit be using the first PMOS pipes PM1 of the control break-make of subject clock signal Vlatch and the second PMOS tube PM2 pipes as
The difference amplifier of MOS pipes is loaded, the first NMOS tube NM1 is as current source, grid also incoming clock signal Vlatch.Even
It is connected on third NMOS tube NM3 between second output terminal OP1 and the source electrode of the first NMOS tube NM1 and is connected to the first output end
The second NMOS tube NM2 between ON1 and the source electrode of the first NMOS tube NM1 provides letting out for two output end charges of pre-amplification circuit
Access is put, the break-make of this access of releasing is controlled by the voltage difference of the first output end ON1 and second output terminal OP1；Prime amplifier
In the comparator correction course, positive input terminal vip1 and negative input end vin1 are accessed on a common-mode voltage, and should
Common-mode voltage is amplified by prime amplifier, respectively obtain for drive third NMOS tube NM3 positive output end signal vp1 and
For driving the negative output terminal signal vn1 of the second NMOS tube NM2.
Latch cicuit, including the phase inverter of two head and the tail interconnection accelerate multilevel iudge process with the type of attachment of positive feedback；
Described two phase inverters are respectively the first phase inverter and the 4th that third PMOS tube PM3 and the 8th NMOS tube NM8 are connected and composed
The second phase inverter that PMOS tube PM4 and the 9th NMOS tube NM9 are connected and composed, the two phase inverter interconnections, output end are logical
Cross the input terminal that buffer is connected respectively to nor gate latch.It is negative that 6th PMOS tube PM6 and the 5th NMOS tube NM5 constitutes amplifier
It carries；Earthing switches of the 7th NMOS tube NM7 and the 6th NMOS tube NM6 as the first phase inverter, grid constitute latch cicuit
Second input terminal FN；Earthing switches of the 5th NMOS tube NM5 and the 4th NMOS tube NM4 as the second phase inverter, grid are constituted
The first input end FP of latch cicuit.The grid and the 4th PMOS tube PM4 of third PMOS tube PM3 and the 8th NMOS tube NM8 and
The drain electrode of nine NMOS tube NM9 is connected to fourth node P3, the drain electrode and the 4th of third PMOS tube PM3 and the 8th NMOS tube NM8
The grid of PMOS tube PM4 and the 9th NMOS tube NM9 be connected to third node N3, fourth node P3 obtained by buffer it is described
The output end vn3 of latch cicuit, third node N3 obtain another output end vp3 of the latch cicuit by buffer.
Nor gate latch, the signal for storing latch cicuit output end vn3 and vp3 are obtained with retaining correction course
Correction number control code value.Nor gate latch is the nor gate combined logical structure of latch, therefore when latch cicuit exports
When the signal of end vn3 and vp3 is Different Logic level, low and high level occurs for the output signal v_cmp of the nor gate latch
Overturning.
Offset cancellation circuit, including the first tunable capacitor array and the second tunable capacitor array, the first tunable capacitor array
One end be connected to first node vn2, the other end ground connection of the first tunable capacitor array, one end of the second tunable capacitor array connects
It is connected to second node vp2, the other end ground connection of the second tunable capacitor array；First tunable capacitor array and the second tunable capacitor battle array
Row all include the branch of n item parallel connections, one switch of each branch series connection and a capacitance, and to simplify the description, first is adjustable
Capacitor array is C1, and the second tunable capacitor array is C2；The n switch of first tunable capacitor array C1 is assisted school by described first
Positive control encoded signal cmp_dp [n-1:N switch of control 0], the second tunable capacitor array C2 is assisted school by described second
Positive control encoded signal cmp_dm [n-1:0] control so that the figure adjustment control circuit is according to the comparison of auxiliary corrective
Judging result pair the first tunable capacitor array C1 and the second tunable capacitor array C2 are adjusted to realize the comparator itself
Offset voltage corrects.The first auxiliary corrective control encoded signal cmp_dp [n-1:0] it is controlled with second auxiliary corrective
Encoded signal cmp_dm [n-1:0] it is a pair of complementary encoded signal, when one of auxiliary corrective control encoded signal increases
Default value, then another auxiliary corrective control encoded signal reduce identical default value accordingly, so that it is determined that each
The closure situation of the n concatenated switch of capacitor in parallel in tunable capacitor array, and then change n capacitance parallel value.
It should be noted that the input stage correcting circuit inside fully-differential amplifier described in Fig. 6 is that NMOS tube is defeated
Enter a grade correcting circuit, the input stage correcting circuit inside fully-differential amplifier described in Fig. 7 corrects for PMOS tube input stage
The comparator in circuit, Fig. 6 and Fig. 7 enables circuit and the enabled circuit structure of the amplifier is identical.Described in Fig. 6
One Corrective control encoded signal is amp_dp [m:1], the second Corrective control encoded signal is amp_dm [m:1]；And in Fig. 7
The first Corrective control encoded signal is amp_dp_n [m:1], the second Corrective control encoded signal is amp_dm_n [m:
1], wherein amp_dp [m:1] adjustment correct the fully-differential amplifier during with amp_dp_n [m:1] institute is corrected in adjustment
State during difference amplifier inversion operation each other, amp_dm [m:1] and amp_dp_n [m:1] there are similar rules.
As shown in Figure 6 and Figure 7, when the input stage of the amplifier circuit is differential pair, the amplifier is fully differential
Amplifier, negative differential output von are connected by feedback resistance R2 with its positive differential input terminal, positive differential output
Vop is connected by feedback resistance R2 with its negative differential input end；Comparator signal source selection circuit includes to be corrected
Auxiliary common-mode signal source vcom1, have with the negative input end of the comparator first switch S1 and second switch S2 of common end with
And there are the third switch S3 and the 4th switch S4 of common end with the positive input terminal of the comparator, wherein second switch S2's is another
Outer one end connects the negative output terminal of the fully-differential amplifier, and the other end of the 4th switch S4 connects the fully-differential amplifier
Positive output end, the other end of first switch S1 and the other end of third switch S3 all connect auxiliary common-mode signal to be corrected
Source vcom1.First switch S1 and third switch S3 is controlled when comparator imbalance correction Enable Pin cal_cmp is high level
It is all closed, the positive-negative input end of the comparator is all accessed to auxiliary common-mode signal source vcom1 to be corrected so that the comparison
Device enters itself offset voltage auxiliary corrective process；When the comparator imbalance voltage correction Enable Pin cal_cmp is low level
When, control first switch S1 and third switch S3 is disconnected, and the comparator imbalance voltage correction Enable Pin cal_cmp passes through
The control signal cal_cmp_n that phase inverter obtains is high level, and control second switch S2 and the 4th switch S4 is closed so that institute
It states comparator and exits offset voltage auxiliary corrective process, further control described in the output signal entrance of the amplifier circuit
Comparator.
Amplifier signal source selection circuit includes common-mode signal source vcom2 to be corrected and the amplifier circuit
Positive input terminal（It is one end with the positive input resistance R1+ of the amplifier in the embodiment of the present invention）Have common end the 5th opens
Close S5 and the 6th switch S6 and the negative input end with the amplifier circuit（It is and the amplifier in the embodiment of the present invention
One end of negative input resistance R1-）The 7th switch S7 and the 8th switch S8 for having common end, wherein the other end of the 6th switch S6
The positive input terminal vip of the automatic calibration circuit is connected, the other end of the 8th switch S8 connects the automatic calibration circuit
Negative input end vin, the other end of the 5th switch S5 and the other end of the 7th switch S7 all connect common-mode signal source to be corrected
Vcom2, for controlling the fully differential amplification under the effect of the enable signal of the amplifier offset correction Enable Pin cal_amp
Device enters or exits offset voltage correction course.It is controlled when the amplifier offset correction Enable Pin cal_amp is high level
5th switch S5 and the 7th switch S7 are closed, and the positive-negative input end of the fully-differential amplifier is all accessed to common mode to be corrected
Signal source vcom2 so that the fully-differential amplifier enters offset voltage correction course；When the amplifier offset correction is enabled
When end cal_amp is low level, control the 5th switch S5 and the 7th switch S7 is disconnected, and the amplifier offset correction is enabled
End cal_amp is high level by the control signal cal_amp_n that phase inverter obtains, and controls the 6th switch S6 and the 8th switch S8
It is all closed so that the fully-differential amplifier exits offset voltage correction course, further controls the automatic calibration circuit
The signal of positive input terminal vip and negative input end vin enter the fully-differential amplifier.
It should be noted that the input stage correcting circuit inside difference amplifier described in Fig. 8 inputs for NMOS tube
Grade correcting circuit, the input stage correcting circuit inside difference amplifier described in Fig. 9 are PMOS tube input stage correcting circuit,
The comparator in Fig. 8 and Fig. 9 enables circuit and the enabled circuit structure of the amplifier is identical.First correction described in Fig. 8
It is amp_dp [m to control encoded signal:1], the second Corrective control encoded signal is amp_dm [m:1]；And described in Fig. 9
One Corrective control encoded signal is amp_dp_n [m:1], the second Corrective control encoded signal is amp_dm_n [m:1],
Middle amp_dp [m:1] adjustment correct the fully-differential amplifier during with amp_dp_n [m:1] difference is corrected in adjustment
Inversion operation each other during point amplifier, amp_dm [m:1] and amp_dp_n [m:1] there are similar rules.
As shown in Figure 8 and Figure 9, when the input stage of the amplifier circuit is single-ended, the amplifier is differential amplification
Device, output end vout are connected by feedback resistance R2 with its negative differential input end；Comparator signal source selection circuit
Include the first switch S1 for having common end with the positive input terminal of the comparator and second switch S2, wherein second switch S2's
Other end connects the output end vout of the difference amplifier, and electricity is automatically corrected described in the other end connection of first switch S1
Reference voltage end vref outside road.When comparator imbalance correction Enable Pin cal_cmp is high level, control first is opened
It closes S1 to be closed, the positive-negative input end of the comparator is all accessed into reference voltage end vref so that the comparator enters imbalance
Voltage auxiliary corrective process；When comparator imbalance correction Enable Pin cal_cmp is low level, control first switch S1 is disconnected
It opens, and the control signal cal_cmp_n that the comparator Enable Pin cal_cmp is obtained by phase inverter is high level, control the
Two switch S2 are closed so that the comparator exits offset voltage auxiliary corrective process, further controls the amplifier electricity
The output signal on road enters the comparator.
Amplifier signal source selection circuit includes and the amplifier circuit negative input end（It is in the embodiment of the present invention
One end of the negative input resistance R1- of the amplifier）There are the 5th switch S5 and the 6th switch S6 of common end, wherein the 6th switch
The other end connection that the other end of S6 connects the positive input terminal vip, the 5th switch S5 of the automatic calibration circuit is described certainly
Reference voltage end vref outside dynamic correcting circuit.When the difference amplifier offset correction Enable Pin cal_amp is high level
When the 5th switch S5 closure of control, the positive-negative input end of the difference amplifier is all accessed into reference voltage end vref so that institute
It states difference amplifier and enters offset voltage correction course；When the amplifier offset correction Enable Pin cal_amp is low level,
The 5th switch S5 is controlled to disconnect, and the amplifier Enable Pin cal_amp passes through the control signal cal_amp_n that phase inverter obtains
For high level, the 6th switch S6 of control is closed so that the difference amplifier exits offset voltage correction course, further controls
The signal for making the automatic calibration circuit positive input terminal vip and negative input end vin enters the difference amplifier.
A kind of auto-correction method of amplifier input offset voltage, the auto-correction method are automatically corrected based on described
Circuit, in conjunction with shown in Figure 10 and Figure 11, after the correction Enable Pin cal_en of the figure adjustment control circuit sets high level, first
It is high level that the figure adjustment control circuit, which controls the comparator imbalance correction Enable Pin cal_cmp, by the comparator
The output end of input terminal and the amplifier disconnects, and correcting end foregoing description comparator in the comparator does not receive described put
The output signal of big device, then under the action of the selection circuit of comparator signal source, the positive-negative input end of the comparator all connects
Enter the auxiliary source vcom1 to be corrected, while the figure adjustment control circuit controls first auxiliary corrective
Encoded signal cmp_dp [n-1:0] and second auxiliary corrective controls encoded signal cmp_dm [n-1:0] it is all disposed within centre
Scale value 1000 ... 00 starts the correction course to itself offset voltage of the comparator, i.e., the auxiliary school of the described amplifier
Positive process；The corresponding first auxiliary corrective control encoded signal cmp_dp [n-1 of wherein described mid-scale value:0] and institute
State the second auxiliary corrective control encoded signal cmp_dm [n-1:0] extreme higher position one, remaining position zero.
If there are offset voltage, the figure adjustment control circuits to be exported according to the comparator for the comparator itself
Corresponding multilevel iudge result v_cmp adjust first auxiliary corrective control encoded signal cmp_dp [n-1 in real time:0] and
The second auxiliary corrective control encoded signal cmp_dm [n-1:0], to the first tunable capacitor array C1 and described second
The capacitance of tunable capacitor array C2 is adjusted, and offset voltage existing for comparator described in voltage offset is corrected by introducing,
Until first auxiliary corrective control encoded signal cmp_dp [n-1:0] circulation change between M and M-1, the automatic school
Positive circuit terminates auxiliary corrective process；The wherein described first auxiliary corrective control encoded signal cmp_dp [n-1:0] numerical value M is used
To weigh the correction accuracy of the comparator.
After the comparator itself offset voltage correction, the figure adjustment control circuit controls the comparator and loses
The positive Enable Pin cal_cmp of adjustment is low level, and the comparator input terminal is connect with the output end of the amplifier to realize
The comparator receives the output signal of the amplifier, then controls the amplifier offset correction Enable Pin cal_amp and sets
For high level, then under the enabled effect of amplifier signal source selection circuit, the positive-negative input end of the amplifier all connects
Entering the signal source to be corrected, (when the input stage of the amplifier circuit is single-ended, the signal source to be corrected is described automatic
Reference voltage vref outside correcting circuit；The signal source to be corrected when the input stage of the amplifier circuit is differential pair
For the common-mode signal source vcom2 to be corrected), while the figure adjustment control circuit encodes first Corrective control
Signal amp1 [m:1] and the second Corrective control encoded signal amp2 [m:1] it is all disposed within reference graduation value, is started to described
The correction course of the offset voltage of comparator.
Specifically, the reference graduation value indicates the first correction metal-oxide-semiconductor array and the second correction metal-oxide-semiconductor array
Place branch is all connected in the middle maximum metal-oxide-semiconductor of corresponding binary weights, and when remaining metal-oxide-semiconductor is to being turned off, first school
Positive control encoded signal amp1 [m:1] and the second Corrective control encoded signal amp2 [m:1] binary system array；When described
All it is NMOS tube clock synchronization in the parallel branch of first correction metal-oxide-semiconductor array and the second correction metal-oxide-semiconductor array, in corresponding diagram 10
The first Corrective control encoded signal amp_dp [n-1:0] the corresponding reference graduation value be 100 ... 00, it is described number school
The state that positive control circuit exports result v_cmp according to the comparator accordingly adjusts the first Corrective control encoded signal
amp_dp [m:1] and the second Corrective control encoded signal amp_dm [m:1] numerical value, when first Corrective control is compiled
Code signal amp_dp [m:When 1] finally recycling bounce between N and N-1, the correction indication end of the figure adjustment control circuit
Cal_done exports high level, indicates that the offset voltage of amplifier correction terminates.And the first correction metal-oxide-semiconductor array and institute
It is all PMOS tube clock synchronization to state in the parallel branch of the second correction metal-oxide-semiconductor array, the coding of the first Corrective control described in corresponding diagram 11
Signal amp_dp_n [m:1] the corresponding reference graduation value be 011 ... 11, the figure adjustment control circuit is according to the ratio
State compared with device output result v_cmp accordingly adjusts the first Corrective control encoded signal amp_dp_n [m:1] and described
Two Corrective control encoded signal amp_dm_n [m:1] numerical value, as the first Corrective control encoded signal amp_dp_n [m:1]
When finally recycling bounce between N and N-1, the high electricity of correction indication end cal_done outputs of the figure adjustment control circuit
It is flat, indicate that the offset voltage of amplifier correction terminates.
If there are offset voltage Voffset for the amplifier, the figure adjustment control circuit is according to the comparator
The corresponding multilevel iudge result v_cmp of output adjusts the first Corrective control encoded signal amp1 [m in real time:1] and it is described
Second Corrective control encoded signal amp2 [m:1], the first correction metal-oxide-semiconductor battle array and the second correction metal-oxide-semiconductor battle array are led to
It is disconnected to be adjusted, it introduces and corrects voltage offset voltage existing for the input stage counteracting original of the amplifier, until described first
Corrective control encoded signal amp1 [m:1] circulation change between N and N-1.The wherein described first Corrective control encoded signal
amp1[m:1] numerical value of N weighs the correction accuracy of the amplifier；The amplifier can be that input stage is the complete poor of differential pair
It is single-ended difference amplifier to divide amplifier or input stage.
The first tunable capacitor array C1 and the second tunable capacitor array C2, includes the branch of a plurality of parallel connection, often
The series connection of branch is there are one switch and a capacitance, the first tunable capacitor array C1 and described second described in the embodiment of the present invention
Tunable capacitor array C2 includes respectively n=4 capacitance, then the first auxiliary corrective control encoded signal is cmp_dp [3:
0], the second auxiliary corrective control encoded signal is cmp_dm [3:0], the bearing calibration of the comparator includes：
When the comparator has negative offset voltage, the multilevel iudge result v_cmp of the comparator output is low level, then
The first auxiliary corrective control encoded signal cmp_dp [3:0] subtract one on the basis of the 4 ' b1000 of mid-scale value to obtain
To 4 ' b0111, the second auxiliary corrective control encoded signal cmp_dm [3:0] in the base of the 4 ' b1000 of mid-scale value
On plinth plus one obtains 4 ' b1001, the first auxiliary corrective control encoded signal cmp_dp [3:0] described the first of corresponding control
The capacitance that tunable capacitor array C1 accesses the first node vn2 reduces, and second auxiliary corrective controls encoded signal
cmp_dm[3:0] the second tunable capacitor array C2 of corresponding control accesses the capacitance increase of the second node vp2, at this time
Since the positive input terminal vip1 and negative input end vin1 of the pre-amplification circuit access auxiliary common-mode signal source vcom1 to be corrected
On, so the voltage decrease speed of the first node vn2 is faster than the voltage decrease speed of the second node vp2.Specifically,
Capacitance of the capacitance of the first node vn2 less than the second node vp2, the first PMOS tube PM1 and the second PMOS tube PM2's
Clock signal Vlatch saltus steps on grid are high level, are connected the first NMOS tube NM1, the pre-amplification circuit by its first
Output end ON1 and second output terminal OP1 provides the capacitance and described second of the first node vn2 for the offset cancellation circuit
The capacitance of node vp2 is released access so that voltage is low level at the first node vn2, voltage at the second node vp2
For high level, to introduce a positive differential voltage to reduce unborn negative offset voltage.The latch cicuit
4th NMOS tube NM4 and the 5th NMOS tube NM5 shutdowns, and the 6th NMOS tube NM6 and the 7th NMOS tube NM7 conductings, by Section four
Point P3 voltages pull down to zero, and third node N3 voltages are pulled upward to supply voltage end by third PMOS tube PM3 and the 5th PMOS tube PM5
VCC.It is high level finally to obtain the multilevel iudge result v_cmp by the output end of the nor gate latch.
As first auxiliary corrective control encoded signal cmp_dp [3:0] when being 4 ' b0110, second auxiliary corrective
Control encoded signal cmp_dm [3:0] it is 4 ' b1010, at this moment the capacitance of the first node vn2 is further less than described the
The capacitance of two node vp2, due to the positive input terminal vip1 and negative input end vin1 of the pre-amplification circuit access it is to be corrected auxiliary
It helps on the vcom1 of common-mode signal source, so the voltage decrease speed of the first node vn2 is faster in the second node vp2's
Voltage decrease speed.This is equivalent to the positive differential voltage that a bigger is introduced for the comparator.And so on, when described
One auxiliary corrective controls encoded signal cmp_dp [3:When 0] reducing since 4 ' b0111, the second auxiliary corrective control coding
Signal cmp_dm [3:0] it is to increase since 4 ' b1001, this can be that the comparator introduces ever-increasing positive differential electrical
Pressure, to balance out unborn negative offset voltage.
When there are positive offset voltages for the comparator, the multilevel iudge result v_cmp of the comparator output is high electricity
Flat, then first auxiliary corrective controls encoded signal cmp_dp [3:0] add on the basis of the 4 ' b1000 of mid-scale value
One obtains 4 ' b1001, the second auxiliary corrective control encoded signal cmp_dm [3:0] in the 4 ' b1000 of mid-scale value
On the basis of subtract one and obtain 4 ' b0111, the first auxiliary corrective control encoded signal cmp_dp [3:0] corresponding control is described
The capacitance that first tunable capacitor array C1 accesses the first node vn2 increases, and second auxiliary corrective control coding letter
Number cmp_dm [3:0] the second tunable capacitor array C2 of corresponding control accesses the capacitance reduction of the second node vp2, this
When auxiliary common-mode signal source to be corrected accessed due to the positive input terminal vip1 and negative input end vin1 of the pre-amplification circuit
On vcom1, so the voltage decrease speed of the first node vn2 is slower than the voltage decrease speed of the second node vp2.Tool
Body, the capacitance of the first node vn2 is more than the capacitance of the second node vp2, the first PMOS tube PM1 and the second PMOS tube
Clock signal Vlatch saltus steps on the grid of PM2 are high level, and the first NMOS tube NM1 is connected, and the pre-amplification circuit passes through
Its first output end ON1 and second output terminal OP1 provides capacitance and the institute of the first node vn2 for the offset cancellation circuit
The capacitance for stating second node vp2 is released access so that voltage is high level, the second node vp2 at the first node vn2
Place's voltage is low level, to introduce a negative differential voltage to reduce unborn negative offset voltage.The latch
4th NMOS tube NM4 and the 5th NMOS tube NM5 conductings in circuit, and the 6th NMOS tube NM6 and the 7th NMOS tube NM7 shutdowns, will
Third node N3 voltages pull down to zero, and fourth node P3 voltages are pulled upward to confession by third PMOS tube PM3 and the 5th PMOS tube PM5
Piezoelectric voltage end VCC.It is low electricity finally to obtain the multilevel iudge result v_cmp by the output end of the nor gate latch
It is flat.
As first auxiliary corrective control encoded signal cmp_dp [3:0] when being 4 ' b1010, second auxiliary corrective
Control encoded signal cmp_dm [3:0] it is 4 ' b0101, at this moment the capacitance of the first node vn2 is further more than described the
The capacitance of two node vp2, due to the positive input terminal vip1 and negative input end vin1 of the pre-amplification circuit access it is to be corrected auxiliary
It helps on the vcom1 of common-mode signal source, so the voltage decrease speed of the first node vn2 is more slower than the second node vp2's
Voltage decrease speed.This is equivalent to the negative differential voltage that a bigger is introduced for the comparator.And so on, when described
One auxiliary corrective controls encoded signal cmp_dp [3:When 0] increasing since 4 ' b1001, the second auxiliary corrective control coding
Signal cmp_dm [3:0] it is to reduce since 4 ' b0111, this introduces constantly increased negative sense differential voltage for the comparator,
To balance out unborn positive offset voltage.
In the NMOS tube input stage correcting circuit, the first correction NMOS tube array and the second correction NMOS
Pipe array all includes branch of the NMOS tube to composition of m item parallel connections, and there are one switch NMOS tubes and one to press for every branch series connection
The NMOS tube that breadth length ratio is reconfigured according to binary weight, the first correction NMOS tube array and described second described in the embodiment of the present invention
Correcting NMOS tube array, respectively the NMOS tube including 4 item parallel connections of m=compiles the branch of composition, then first Corrective control
Code signal is amp_dp [3:0], the second Corrective control encoded signal is amp_dm [3:0], the correction side of the amplifier
Method includes：
When the amplifier has negative offset voltage, the output signal that the comparator receives the amplifier makes output
Multilevel iudge result v_cmp is low level, the first Corrective control encoded signal amp_dp [3:0] in the reference graduation value
On the basis of 4 ' b1000 plus one obtains 4 ' b1001, the second Corrective control encoded signal amp_dm [3:0] in the benchmark
Subtract one on the basis of 4 ' b1000 of scale value and obtains 4 ' b0111, the first Corrective control encoded signal amp_dp [3:0] it controls
The break-make of 4 first switch NMOS tubes in the first correction NMOS tube array so that grid and the amplifier are just defeated
The equivalent breadth length ratio for 4 the first correction NMOS tubes for entering to hold v+ to be connected increases, and second Corrective control coding letter
Number amp_dm [3:0] grid is connected with the amplifier negative input end v- in the second correction NMOS tube array of corresponding control
The equivalent breadth length ratio of 4 the second correction NMOS tubes connect reduces so that the input stage correcting circuit exports positive difference
Voltage, to which the input stage in the amplifier corrects unborn negative offset voltage.
As the first Corrective control encoded signal amp_dp [3:0] when being 4 ' b1010, the second auxiliary corrective control
Encoded signal amp_dm [3:0] it is 4 ' b0110, then according to the relations of distribution of binary weights, grid and the amplifier are just defeated
The equivalent breadth length ratio for 4 the first correction NMOS tubes for entering to hold v+ to be connected further is being more than grid and the amplifier just
The equivalent breadth length ratio for 4 the second correction NMOS tubes that input terminal v- is connected, and so on, when first Corrective control
Encoded signal amp_dp [3:When 0] increasing since 4 ' b1001, the second Corrective control encoded signal amp_dm [3:0] it is
Reduce since 4 ' b0111, this introduces a constantly increased positive differential voltage for the amplifier, is deposited originally with balancing out
Negative offset voltage.
When there are positive offset voltages for the amplifier, the multilevel iudge result v_cmp of the comparator output is high electricity
It is flat, the first Corrective control encoded signal amp_dp [3:0] subtract one on the basis of the 4 ' b1000 of reference graduation value to obtain
4 ' b0111, the second Corrective control encoded signal amp_dm [3:0] add on the basis of the 4 ' b1000 of reference graduation value
One obtains 4 ' b1001, the first Corrective control encoded signal amp_dp [3:0] it controls in the first correction NMOS tube array
The break-make of 4 first switch NMOS tubes so that be connected with the amplifier positive input terminal v+ 4 described first of grid
The equivalent breadth length ratio for correcting NMOS tube reduces, and the second Corrective control encoded signal amp_dm [3:0] institute of corresponding control
State 4 the second correction NMOS tubes that grid is connected with the amplifier negative input end v- in the second correction NMOS tube array
Equivalent breadth length ratio increase so that the negative differential voltage of input stage correcting circuit output, in the defeated of the amplifier
Enter grade and corrects unborn positive offset voltage.
As the first Corrective control encoded signal amp_dp [3:0] when being 4 ' b0110, the second Corrective control coding
Signal amp_dm [3:0] it is 4 ' b1010, then according to the relations of distribution of binary weights, grid and the amplifier positive input terminal v
The equivalent breadth length ratio of+4 the first correction NMOS tubes being connected further is less than grid and the amplifier positive input
The equivalent breadth length ratio for 4 the second correction NMOS tubes that end v- is connected, and so on, when first Corrective control encodes
Signal amp_dp [3:When 0] reducing since 4 ' b0111, the second Corrective control encoded signal amp_dm [3:0] it is from 4 '
B1001 starts to increase, this introduces a continuous increased negative sense differential voltage for the amplifier, unborn to balance out
Positive offset voltage.The bearing calibration of the amplifier provided in this embodiment is suitable for the fully differential that input stage is differential pair and puts
Big device or input stage are single-ended difference amplifier.
In the PMOS tube input stage correcting circuit, the first correction PMOS tube array and the second correction PMOS
Pipe array all includes branch of the PMOS tube to composition of m item parallel connections, and there are one switch PMOS tube and one to press for every branch series connection
The PMOS tube that breadth length ratio is reconfigured according to binary weight, the first correction PMOS tube array and described second described in the embodiment of the present invention
Correcting PMOS tube array, respectively the PMOS tube including 4 item parallel connections of m=compiles the branch of composition, then first Corrective control
Code signal is amp_dp_n [3:0], the second Corrective control encoded signal is amp_dm_n [3:0], since PMOS tube is low
Level controls its gate turn-on, and NMOS tube is high level controls its gate turn-on, so the reference graduation of the present embodiment
Value is 4 ' b0111.
When there is negative offset voltage in the amplifier, the comparator receive the amplifier output signal make it is defeated
The multilevel iudge result v_cmp gone out is low level, the first Corrective control encoded signal amp_dp_n [3:0] in the benchmark
Subtract one on the basis of 4 ' b0111 of scale value and obtains 4 ' b0110, the second Corrective control encoded signal amp_dm_n [3:0] exist
On the basis of the 4 ' b0111 of reference graduation value plus one obtains 4 ' b1000, the first Corrective control encoded signal amp_dp_n
[3:0] it is minimum that weight maximum and weight in 4 first switch PMOS tube are controlled in the first correction PMOS tube array
Place branch conducting so that 4 the first correction PMOS tube that grid is connected with the amplifier positive input terminal v+ etc.
It imitates breadth length ratio to increase, the second Corrective control encoded signal amp_dm_n [3:0] the second correction PMOS of corresponding control
The equivalent breadth length ratio for 4 the second correction PMOS tube that grid is connected with the amplifier negative input end v- in pipe array subtracts
It is small, and since the breadth length ratio more described than remaining 3 first of the maximum first correction PMOS tube of weight corrects the total of PMOS tube
With it is big, so the equivalent wide length for 4 the first correction PMOS tube that grid is connected with the amplifier positive input terminal v+
More than the equivalent breadth length ratio for 4 the second correction PMOS tube that grid is connected with the amplifier negative input end v- so that
The input stage correcting circuit exports positive differential voltage, unborn negative to be corrected in the input stage of the amplifier
Offset voltage.
As the first Corrective control encoded signal amp_dp_n [3:0] when being 4 ' b0101, second Corrective control is compiled
Code signal amp_dm_n [3:0] be 4 ' b1001, then according to the PMOS tube of conducting to corresponding binary weights, grid with it is described
The equivalent breadth length ratio for 4 the first correction PMOS tube that amplifier positive input terminal v+ is connected further is more than grid and institute
The equivalent breadth length ratios of 4 that amplifier positive input terminal v- is connected the second correction PMOS tube are stated, and so on, when described the
One Corrective control encoded signal amp_dp_n [3:When 0] reducing since 4 ' b0101, the second Corrective control encoded signal
amp_dm_n[3:0] it is to increase since 4 ' b1001, this introduces a constantly increased positive differential electrical for the amplifier
Pressure, to balance out unborn negative offset voltage.
When the amplifier is there are positive offset voltage, the comparator receive the amplifier output signal make it is defeated
The multilevel iudge result v_cmp gone out is high level, the first Corrective control encoded signal amp_dp_n [3:0] in the benchmark
On the basis of 4 ' b0111 of scale value plus one obtains 4 ' b1000, the second Corrective control encoded signal amp_dm_n [3:0] exist
Subtract one on the basis of the 4 ' b0111 of reference graduation value and obtains 4 ' b0110, the second Corrective control encoded signal amp_dm_n
[3:0] it is minimum that weight maximum and weight in 4 second switch PMOS tube are controlled in the second correction PMOS tube array
Place branch conducting so that 4 the second correction PMOS tube that grid is connected with the amplifier positive input terminal v- etc.
It imitates breadth length ratio to increase, the first Corrective control encoded signal amp_dp_n [3:0] the first correction PMOS of corresponding control
The equivalent breadth length ratio for 4 the first correction PMOS tube that grid is connected with the amplifier negative input end v+ in pipe array subtracts
It is small, and since the breadth length ratio more described than remaining 3 second of the maximum second correction PMOS tube of weight corrects the total of PMOS tube
With it is big, so the equivalent wide length for 4 the first correction PMOS tube that grid is connected with the amplifier positive input terminal v+
Less than the equivalent breadth length ratio for 4 the second correction PMOS tube that grid is connected with the amplifier negative input end v- so that
The negative differential voltage of the input stage correcting circuit output, it is unborn positive to be corrected in the input stage of the amplifier
Offset voltage.
As the first Corrective control encoded signal amp_dp_n [3:0] when being 4 ' b1001, second Corrective control is compiled
Code signal amp_dm_n [3:0] be 4 ' b0101, then according to the PMOS tube of conducting to corresponding binary weights, grid with it is described
The equivalent breadth length ratio for 4 the first correction PMOS tube that amplifier positive input terminal v+ is connected further is less than grid and institute
The equivalent breadth length ratios of 4 that amplifier positive input terminal v- is connected the second correction PMOS tube are stated, and so on, when described the
One Corrective control encoded signal amp_dp_n [3:When 0] increasing since 4 ' b1000, the second Corrective control encoded signal
amp_dm_n[3:0] it is to reduce since 4 ' b0110, this introduces a continuous increased negative sense differential electrical for the amplifier
Pressure, to balance out unborn positive offset voltage.The bearing calibration of the amplifier provided in this embodiment is suitable for defeated
Enter fully-differential amplifier that grade is differential pair or input stage is single-ended difference amplifier.
Specifically, all it is in the parallel branch of the first correction metal-oxide-semiconductor array and the second correction metal-oxide-semiconductor array
NMOS tube clock synchronization, the corresponding reference graduation value are the first correction MOS by the corresponding binary system array of inversion operation
All it is PMOS tube to the corresponding reference graduation value in the parallel branch of pipe array and the second correction metal-oxide-semiconductor array；
For the PMOS tube input stage correcting circuit, in the correction course of the offset voltage of amplifier, the first correction control
Encoded signal amp_dp_n [3 processed:0] variable quantity and grid and the amplifier in first PMOS tube correction array are just defeated
The equivalent wide long variable quantity of enter to hold v+ to be connected 4 the first correction PMOS tube is there are negative correlativing relation, and described second
Corrective control encoded signal amp_dm_n [3:0] to second PMOS tube correction array, there is also identical control plannings；And
The NMOS tube input stage correcting circuit relevant variation relation in the correction course of the offset voltage of amplifier is then opposite.
Proposed offset voltage of amplifier automatic calibration circuit technology is the differential input stage to amplifier first
Modification appropriate is carried out, so that the equivalent breadth length ratio of input difference metal-oxide-semiconductor pair is controlled by digital control code value, by entire
The digital control code value for automatically correcting acquisition input stage of amplifier and comparator composition, to realize in full-differential circuits application
In, under zero differential input voltage situation, zero differential output voltage is obtained, in single-end circuit application, electricity is inputted in zero differential
It presses under situation, obtains desired single ended output voltage.Compared with the existing technology, the embodiment of the present invention is amplified by compensating
The output voltage numerical approach of device corrects the offset voltage of the input stage of amplifier, and the offset voltage of amplifier proposed is automatic
Correcting circuit technology has correction thorough, and correction course is to carry out in a digital manner, has low in energy consumption, realizes simple, imbalance
The calibration step and range of voltage are easy extension.Notice that entire offset voltage correction course is all by monitoring comparator simultaneously
Result is exported to adjust respective digital control code, the analog voltage that one constantly adjusts is not needed to and just completes to amplify fully differential
The correction of device offset voltage, that is to say, that the entire process that automatically corrects is digital form operation, after correction, it is only necessary to protect
Obtained respective digital is stayed to control code value, correction auxiliary circuit originally can be closed to save power consumption.
Device embodiments described above are only schematical, wherein the unit illustrated as separating component
It may or may not be physically separated, the component shown as unit may or may not be physics list
Member, you can be located at a place, or may be distributed over multiple network units.It can be selected according to the actual needs
In some or all of module realize the purpose of present embodiment scheme.Those of ordinary skill in the art are not paying creation
Property labour in the case of, you can to understand and implement.
Claims (12)
1. a kind of automatic calibration circuit of amplifier input offset voltage, which is characterized in that the automatic calibration circuit includes putting
Big device signal source selection circuit, amplifier circuit, comparator signal source selection circuit, comparator and digital correction control circuit；
Figure adjustment control circuit includes the comparator Enable Pin being connect with comparator signal source selection circuit, the first auxiliary school
Positive control encoded signal end and the second auxiliary corrective control encoded signal end, under correcting enabled effect in comparator imbalance,
The first auxiliary corrective that the end output of the first auxiliary corrective control encoded signal is adjusted according to the output signal of comparator controls coding
Signal and the second auxiliary corrective of the second auxiliary corrective control encoded signal end output control encoded signal, to offset comparator certainly
The offset voltage of body；Figure adjustment control circuit further includes the amplifier imbalance school being connected with amplifier signal source selection circuit
Positive Enable Pin, the first Corrective control encoded signal end and the second Corrective control encoded signal end, in the mistake for completing comparator
Adjust voltage correction after, in conjunction with comparator signal source selection circuit and amplifier signal source selection circuit collective effect, and according to than
Compared with the first Corrective control encoded signal and the second correction that the output signal of device adjusts the output of the first Corrective control encoded signal end
The the second Corrective control encoded signal for controlling the output of encoded signal end, to realize that the input stage in amplifier circuit offsets amplifier
Offset voltage；
Amplifier signal source selection circuit is used for during masking amplifier according to the amplifier offset correction Enable Pin
Correction enable signal be that amplifier circuit inputs signal to be corrected；
Amplifier circuit is the amplifier with feedback control loop, and amplifier includes metal-oxide-semiconductor input stage correcting circuit, is used for
The tune of the first Corrective control encoded signal and the second Corrective control encoded signal of the output of figure adjustment control circuit
Under section effect, by changing the conducting situation of metal-oxide-semiconductor array in parallel in metal-oxide-semiconductor input stage correcting circuit, to draw in input stage
Enter the offset voltage that offset voltage offsets the amplifier；
Comparator signal source selection circuit, for correcting Enable Pin according to the comparator imbalance during correcting comparator
Correction enable signal be that comparator inputs signal to be corrected, and controls amplifier after the offset voltage correction for completing comparator
The output signal of circuit enters comparator；
Comparator, first auxiliary corrective control encoded signal for being exported according to the figure adjustment control circuit and institute
It states the second auxiliary corrective control encoded signal and adjusts the charge discharging resisting speed of the tunable capacitor built in comparator, and generate to compare and sentence
Disconnected result；
Wherein, the first auxiliary corrective control encoded signal and second auxiliary corrective control encoded signal are that correction is compared
The n bit groups of a pair of the complementation generated during device offset voltage itself, i.e., one of n bits group increase
One default value, another n bits group then reduce identical default value；The first auxiliary corrective control coding
Signal end and second auxiliary corrective control encoded signal end are all n BITBUS networks, and n is integer；
The first Corrective control encoded signal and the second Corrective control encoded signal are masking amplifier offset voltage mistakes
The m bit groups of a pair of the complementation generated in journey, i.e., one of m bits group increase a default value, separately
One m bits group then reduces identical default value；The m bits group is increased successively according to binary weights
Add；The first Corrective control encoded signal end and the second Corrective control encoded signal end are all m BITBUS networks, and m is whole
Number.
2. automatic calibration circuit according to claim 1, which is characterized in that the metal-oxide-semiconductor input stage correcting circuit includes the
One correction metal-oxide-semiconductor array, the second correction metal-oxide-semiconductor array, the one zero metal-oxide-semiconductor, the 2nd 0 metal-oxide-semiconductor, cascade load circuit and electric current
Source；
The grid of one zero metal-oxide-semiconductor connects the positive input terminal of the amplifier, and the grid of the 2nd 0 metal-oxide-semiconductor connects institute
The negative input end of amplifier is stated, the drain electrode of the one zero metal-oxide-semiconductor and the 2nd 0 metal-oxide-semiconductor loads electricity with the cascade respectively
Two input terminals on road are connected, and the source electrode of the one zero metal-oxide-semiconductor and the 2nd 0 metal-oxide-semiconductor is connected with the current source
It connects so that the one zero metal-oxide-semiconductor and the 2nd 0 metal-oxide-semiconductor constitute differential pair；Wherein described the first zero metal-oxide-semiconductor and described
The size of 20 metal-oxide-semiconductors is identical；
The first correction metal-oxide-semiconductor array is in parallel with the one zero metal-oxide-semiconductor, in the first Corrective control encoded signal
Under the control action for holding the first Corrective control encoded signal of output, the first correction metal-oxide-semiconductor array described on or off
In corresponding metal-oxide-semiconductor to realize that the offset voltage of the amplifier corrects；The second correction metal-oxide-semiconductor array and described second
Zero metal-oxide-semiconductor is in parallel, the second Corrective control encoded signal for being exported at the second Corrective control encoded signal end
Under control action, corresponding metal-oxide-semiconductor is to realize the mistake of the amplifier in the second correction metal-oxide-semiconductor array described on or off
Adjust voltage correction；The size phase of wherein described first correction metal-oxide-semiconductor array and the metal-oxide-semiconductor pair of the second correction metal-oxide-semiconductor array
Deng.
3. automatic calibration circuit according to claim 2, which is characterized in that described first, which corrects metal-oxide-semiconductor array, includes and institute
State the metal-oxide-semiconductor pair of m branch of the one zero metal-oxide-semiconductor parallel connection；The metal-oxide-semiconductor of the m branch to include m breadth length ratio according to two into
The first switch metal-oxide-semiconductor that the first correction metal-oxide-semiconductor and its corresponding place branch road that weight processed is multiplied are in series；Wherein, m
The source electrode of a first correction metal-oxide-semiconductor is connected with the source electrode of the one zero metal-oxide-semiconductor, and m described first correct metal-oxide-semiconductor
Grid is all connected with the positive input terminal of the amplifier, drain electrode and the one zero MOS of the m first switch metal-oxide-semiconductors
The drain electrode of pipe is connected, the grids of m first switch metal-oxide-semiconductors respectively in the first Corrective control encoded signal according to
The signal wire that binary weights are multiplied is connected, for controlling the binary weight heavy phase corresponding to breadth length ratio connected in series
The matched first correction metal-oxide-semiconductor accesses the metal-oxide-semiconductor input stage correcting circuit；
The second correction metal-oxide-semiconductor array includes the metal-oxide-semiconductor pair of the m branch in parallel with the 2nd 0 metal-oxide-semiconductor；The m
The metal-oxide-semiconductor of branch is to including that m breadth length ratio corrects metal-oxide-semiconductor and its corresponding institute according to binary weights at multiple increased second
The second switch metal-oxide-semiconductor being in series on branch road；Wherein, the grids of the described second correction metal-oxide-semiconductors of m all with the amplifier
Negative input end is connected, and the source electrode of m the second correction metal-oxide-semiconductors is connected with the source electrode of the 2nd 0 metal-oxide-semiconductor, m institute
The grid for stating the second correction metal-oxide-semiconductor is all connected with the negative input end of the amplifier, the grid of the m second switch metal-oxide-semiconductors
Pole is connected with the second Corrective control encoded signal according to the signal wire that binary weights are multiplied respectively, for controlling
It is defeated to make the second correction metal-oxide-semiconductor access metal-oxide-semiconductor that the binary weights corresponding to breadth length ratio connected in series match
Enter a grade correcting circuit；
Wherein, the first correction metal-oxide-semiconductor array and the institute that identical binary weights are corresponded in the second correction metal-oxide-semiconductor array
It is identical with the breadth length ratio of the second correction metal-oxide-semiconductor to state the first correction metal-oxide-semiconductor；The binary weights are two exponential relationships；m
It is the breadth length ratio of a first correction metal-oxide-semiconductor and smaller than the breadth length ratio of the one zero metal-oxide-semiconductor, m the second correction MOS
It is the breadth length ratio of pipe and smaller than the breadth length ratio of the 2nd 0 metal-oxide-semiconductor.
4. automatic calibration circuit according to claim 3, which is characterized in that the one zero metal-oxide-semiconductor and the 2nd 0 MOS
When Guan Douwei NMOS tubes, the m first correction metal-oxide-semiconductors and the m first switch metal-oxide-semiconductors are all NMOS tube；Described first
When zero metal-oxide-semiconductor and the 2nd 0 metal-oxide-semiconductor are all PMOS tube, the m first correction metal-oxide-semiconductors and the m first switch MOS
Guan Douwei PMOS tube.
5. automatic calibration circuit according to claim 4, which is characterized in that the comparator includes pre-amplification circuit, imbalance
Eliminate circuit, latch cicuit and nor gate latch；First output end of pre-amplification circuit and the first input end of latch cicuit
It is connected to first node, the second output terminal of pre-amplification circuit and the second input terminal of latch cicuit are connected to second node；
Pre-amplification circuit has the prime amplifier for forming comparator input terminal, the load differential metal-oxide-semiconductor pair of subject clock signal control
With the metal-oxide-semiconductor as current mirror, for input signal is amplified to the amplitude that the comparator can be identified effectively；
Latch cicuit, including the phase inverter of two head and the tail interconnection accelerate multilevel iudge process with the type of attachment of positive feedback；
Nor gate latch, for storing the signal of latch cicuit output end to retain the correction number control that correction course is obtained
Code value processed, and export the multilevel iudge result to the figure adjustment control circuit as auxiliary corrective；
Offset cancellation circuit, including the first tunable capacitor array and the second tunable capacitor array, the one of the first tunable capacitor array
End is connected to first node, the other end ground connection of the first tunable capacitor array, and one end of the second tunable capacitor array is connected to the
Two nodes, the other end ground connection of the second tunable capacitor array；Wherein, the first tunable capacitor array and the second tunable capacitor array be all
Include the branch of n item parallel connections, each branch, which is connected one, to be switched and a capacitance, n switch of the first tunable capacitor array
The first auxiliary corrective by the end output of first auxiliary corrective control encoded signal controls controlling for encoded signal, and second is adjustable
Second auxiliary corrective control coding letter of the n switch of capacitor array by the end output of second auxiliary corrective control encoded signal
Number control so that the figure adjustment control circuit is according to multilevel iudge result pair the first tunable capacitor array of auxiliary corrective
It is adjusted with the second tunable capacitor array to realize the comparator itself offset voltage correction.
6. according to any one of claim 1 to claim 5 automatic calibration circuit, which is characterized in that when the amplifier
When the input stage of circuit is differential pair, the amplifier is fully-differential amplifier, two difference output end passes through feedback resistance
It is connected with its opposite polarity differential input end；
Comparator signal source selection circuit includes the negative input end in auxiliary common-mode signal source and the comparator to be corrected
There is the first switch and the second switch of common end and there is the third of common end to switch and the with the positive input terminal of the comparator
Four switches, wherein the other end of second switch connects the negative output terminal of the fully-differential amplifier, and other the one of the 4th switch
End connects the positive output end of the fully-differential amplifier, and the other end of other end and the third switch of first switch, which all connects, to be waited for
The auxiliary common-mode signal source of correction, for controlling institute under correcting the correction enable signal effect of Enable Pin in the comparator imbalance
It states comparator and enters or exit offset voltage auxiliary corrective process；
Amplifier signal source selection circuit includes the positive input terminal in common-mode signal source and the amplifier circuit to be corrected
Have common end the 5th switchs and the 6th switchs and have with the negative input end of the amplifier circuit the 7th switch of common end
With the 8th switch, wherein the other end of the 6th switch connects the positive input terminal of the automatic calibration circuit, the 8th switch it is another
Outer one end connects the negative input end of the automatic calibration circuit, and the other end that the other end of the 5th switch and the 7th switch all connects
Common-mode signal source is received, for controlling the amplification under the effect of the correction enable signal of the amplifier offset correction Enable Pin
Device enters or exits offset voltage correction course.
7. according to any one of claim 1 to claim 5 automatic calibration circuit, which is characterized in that when the amplifier
When the input stage of circuit is single-ended, the amplifier is difference amplifier, and output end passes through feedback resistance and its negative input end
It is connected；
Comparator signal source selection circuit includes the first switch for having common end with the positive input terminal of the comparator and
Two switches, wherein the other end of second switch connects the output end of the difference amplifier, and the other end of first switch connects
The reference voltage end outside the automatic calibration circuit is connect, the enabled letter of the correction for correcting Enable Pin in the comparator imbalance
Number lower control comparator of effect enters or exits imbalance auxiliary corrective process；
Amplifier signal source selection circuit include with the amplifier circuit negative input end have common end the 5th switch and
6th switch, wherein the other end of the 6th switch connects the positive input terminal of the automatic calibration circuit, the 5th switch it is another
Outer one end connects the reference voltage end outside the automatic calibration circuit, in the school of the amplifier offset correction Enable Pin
The positive enable signal effect lower control amplifier enters or exits offset correction process.
8. a kind of auto-correction method of amplifier input offset voltage, which is based on claim 1 to power
Profit requires any one of 7 automatic calibration circuits, which is characterized in that including：
After the correction Enable Pin of the figure adjustment control circuit sets high level, the figure adjustment control circuit described first controls institute
It is high level to state comparator imbalance correction Enable Pin, and the output end of the comparator input terminal and the amplifier is disconnected,
The comparator imbalance correction terminates the output signal that foregoing description comparator does not receive the amplifier, then in the comparison
Under the action of device signal source selection circuit, the positive-negative input end of the comparator all accesses the auxiliary source to be corrected,
First auxiliary corrective is controlled encoded signal by the figure adjustment control circuit simultaneously and second auxiliary corrective controls
Encoded signal is all disposed within mid-scale value, starts the correction course to itself offset voltage of the comparator, i.e., described to put
The auxiliary corrective process of big device；The corresponding first auxiliary corrective control encoded signal of wherein described mid-scale value and described
Second auxiliary corrective controls the extreme higher position one of encoded signal, remaining position zero；
If there are the phases that itself offset voltage, the figure adjustment control circuit are exported according to the comparator for the comparator
The first auxiliary corrective control encoded signal is adjusted when the multilevel iudge fructufy answered and second auxiliary corrective control is compiled
Code signal is adjusted the capacitance of the first tunable capacitor array and the second tunable capacitor array, passes through introducing
Offset voltage existing for comparator itself described in voltage offset is corrected, until first auxiliary corrective controls encoded signal in M
The correction of itself offset voltage of the comparator terminates when circulation change between M-1, i.e., the described automatic calibration circuit terminates to assist
Correction course；The numerical value M of the wherein described first auxiliary corrective control encoded signal is used for weighing the correction accuracy of the comparator；
After the comparator itself offset voltage correction, the figure adjustment control circuit controls the comparator imbalance school
Positive Enable Pin is low level, and the comparator input terminal is connect with the output end of the amplifier to realize that the comparator connects
The output signal of the amplifier is received, it is high level then to control the amplifier Enable Pin, then in the amplifier signal source
Under the action of selection circuit, the positive-negative input end of the amplifier all accesses the signal source to be corrected, while the digital school
The first Corrective control encoded signal and the second Corrective control encoded signal are all disposed within benchmark and carved by positive control circuit
Angle value starts the correction course of the offset voltage to the amplifier；Wherein, the reference graduation value indicates first correction
The maximum metal-oxide-semiconductor of binary weights is corresponded in metal-oxide-semiconductor array and the second correction metal-oxide-semiconductor array place branch is all connected,
And remaining metal-oxide-semiconductor is when being turned off place branch, corresponding the first Corrective control encoded signal and second correction
Control the binary system array of encoded signal；
If there are offset voltage, the figure adjustment control circuits to be exported according to the comparator corresponding for the amplifier
The first Corrective control encoded signal and the second Corrective control encoded signal are adjusted when multilevel iudge fructufy, to described
The break-make of first correction metal-oxide-semiconductor array and the second correction metal-oxide-semiconductor array is adjusted, and introduces and corrects voltage in the amplification
The input stage of device offsets offset voltage existing for original, until the first Corrective control encoded signal recycles change between N and N-1
The offset voltage of amplifier correction terminates when change；The numerical value of N of the wherein described first Corrective control encoded signal is used for weighing institute
State the correction accuracy of amplifier.
9. auto-correction method according to claim 8, which is characterized in that the bearing calibration of the comparator includes：
When the comparator has negative offset voltage, the multilevel iudge result of the comparator output is low level, then described
First auxiliary corrective control encoded signal subtracts one on the basis of the mid-scale value, the second auxiliary corrective control coding
Signal adds one on the basis of the mid-scale value, and the first auxiliary corrective control encoded signal control described first is adjustable
The capacitance that capacitor array accesses the first node reduces, and second auxiliary corrective control encoded signal control described second
The capacitance that tunable capacitor array accesses the second node increases so that the voltage decrease speed of the first node is faster than described
The voltage decrease speed of second node is equivalent to and introduces a positive differential voltage to balance out unborn negative imbalance electricity
Pressure；
When there are positive offset voltages for the comparator, then the multilevel iudge result of the comparator output is high level, then institute
It states the first auxiliary corrective control encoded signal and adds one on the basis of the mid-scale value, the second auxiliary corrective control is compiled
Code signal subtracts one on the basis of the mid-scale value, and the first auxiliary corrective control encoded signal control described first can
The capacitance that capacitor array accesses the first node is adjusted to increase, and second auxiliary corrective control encoded signal control described the
The capacitance that two tunable capacitor arrays access the second node reduces so that the voltage decrease speed of the first node is slower than institute
The voltage decrease speed for stating second node is equivalent to and introduces a negative differential voltage to balance out unborn positive imbalance
Voltage.
10. auto-correction method according to claim 9, which is characterized in that the first correction metal-oxide-semiconductor array and described the
All it is NMOS tube clock synchronization in the parallel branch of two correction metal-oxide-semiconductor arrays, the first correction metal-oxide-semiconductor array is the first correction NMOS
Pipe array, the first correction metal-oxide-semiconductor are the first correction NMOS tube, and the second correction metal-oxide-semiconductor array is the second correction NMOS
Pipe array, the second correction metal-oxide-semiconductor are the second correction NMOS tube；The bearing calibration of the amplifier includes：
When the amplifier has negative offset voltage, the multilevel iudge result of the comparator output is low level, described the
One Corrective control encoded signal adds one on the basis of the reference graduation value, and the second Corrective control encoded signal is described
Subtract one on the basis of reference graduation value, the first Corrective control encoded signal corresponds in the first correction NMOS tube array of control
The equivalent breadth length ratio for the first correction NMOS tube that grid is connected with the amplifier positive input terminal increases, the second correction control
Encoded signal processed corresponds to grid is connected with the amplifier negative input end in the second correction NMOS tube array controlled second
The equivalent breadth length ratio for correcting NMOS tube reduces so that the input stage correcting circuit exports positive differential voltage, to described
The input stage of amplifier corrects unborn negative offset voltage；
When the amplifier is there are positive offset voltage, the multilevel iudge result of the comparator output is high level, described the
One Corrective control encoded signal subtracts one on the basis of the reference graduation value, and the second control correction signal is in the benchmark
Add one on the basis of scale value, the first Corrective control encoded signal corresponds to grid in the first correction NMOS tube array controlled
The equivalent breadth length ratio for the first correction NMOS tube being connected with the amplifier positive input terminal reduces, and second Corrective control is compiled
Code signal corresponds to the second of control and corrects the second correction that grid in NMOS tube array is connected with the amplifier negative input end
The equivalent breadth length ratio of NMOS tube increases so that the negative differential voltage of the input stage correcting circuit output, in the amplification
The input stage of device corrects unborn positive offset voltage.
11. auto-correction method according to claim 9, which is characterized in that the first correction metal-oxide-semiconductor array and described the
All it is PMOS tube clock synchronization in the parallel branch of two correction metal-oxide-semiconductor arrays, the first correction metal-oxide-semiconductor array is the first correction PMOS
Pipe array, the first correction metal-oxide-semiconductor are the first correction PMOS tube, and the second correction metal-oxide-semiconductor array is the second correction PMOS
Pipe array, the second correction metal-oxide-semiconductor are the second correction PMOS tube；The bearing calibration of the amplifier includes：
When the amplifier has negative offset voltage, the multilevel iudge result of the comparator output is low level, described the
One Corrective control encoded signal subtracts one on the basis of the reference graduation value, and the second Corrective control encoded signal is described
Add one on the basis of reference graduation value, the first Corrective control encoded signal corresponds in the first correction PMOS tube array of control
The equivalent breadth length ratio for the first correction PMOS tube that grid is connected with the amplifier positive input terminal increases, the second correction control
Encoded signal processed corresponds to grid is connected with the amplifier negative input end in the second correction PMOS tube array controlled second
The equivalent breadth length ratio for correcting PMOS tube reduces so that the input stage correcting circuit exports positive differential voltage, to described
The input stage of amplifier corrects unborn negative offset voltage；
When the amplifier is there are positive offset voltage, the multilevel iudge result of the comparator output is high level, described the
One Corrective control encoded signal adds one on the basis of the reference graduation value, and the second control correction signal is in the benchmark
Subtract one on the basis of scale value, the first Corrective control encoded signal corresponds to grid in the first correction PMOS tube array controlled
The equivalent breadth length ratio for the first correction PMOS tube being connected with the amplifier positive input terminal reduces, and second Corrective control is compiled
Code signal corresponds to the second of control and corrects the second correction that grid in PMOS tube array is connected with the amplifier negative input end
The equivalent breadth length ratio of PMOS tube increases so that the negative differential voltage of the input stage correcting circuit output, in the amplification
The input stage of device corrects unborn positive offset voltage.
12. according to auto-correction method described in claim 10 or claim 11, which is characterized in that the first correction MOS
All it is NMOS tube clock synchronization in the parallel branch of pipe array and the second correction metal-oxide-semiconductor array, the corresponding reference graduation value
It is that the first correction metal-oxide-semiconductor array and described second corrects metal-oxide-semiconductor array by the corresponding binary system array of inversion operation
All it is PMOS tube in parallel branch to the corresponding reference graduation value；
Wherein, the amplifier can be fully-differential amplifier that input stage is differential pair or input stage is single-ended differential amplification
Device.
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