CN104639071A - Operational amplifier - Google Patents
Operational amplifier Download PDFInfo
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- CN104639071A CN104639071A CN201310548747.6A CN201310548747A CN104639071A CN 104639071 A CN104639071 A CN 104639071A CN 201310548747 A CN201310548747 A CN 201310548747A CN 104639071 A CN104639071 A CN 104639071A
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Abstract
The invention discloses an operational amplifier. The operational amplifier comprises a two-stage amplifying circuit and a biasing circuit, wherein a first-stage folded cascade amplifying circuit can provide a high gain being over 90dB for the circuit; and a second-stage push-pull output has a good driving capability. The bias voltage of the amplifying circuit is provided by the biasing circuit in which a band-gap reference circuit is adopted, so that the bias voltage of the circuit can be stabilized, and the circuit with the characteristics of high gain and bias stability can be applied to a high-accuracy closed loop feedback system.
Description
Technical field
The present invention relates to a kind of semiconductor integrated circuit, particularly relate to a kind of operational amplifier.
Background technology
Operational amplifier is one of parts that in analog circuit, purposes is the widest, is generally used in closed loop feedback system.The open-loop gain of amplifier is higher, and the accuracy of closed-loop system is higher, and high-precision closed-loop system usually requires that amplifier possesses the high-gain of more than 90dB.In deep submicron process, the gain of single-stage amplifier is difficult to more than 70dB, and the change of traditional biasing circuit to supply voltage and technique, temperature is very responsive, causes amplifier to be difficult to keep stable performance.
Summary of the invention
Technical problem to be solved by this invention is to provide a kind of operational amplifier, has high-gain and stable biasing circuit, can be used for high-precision closed loop feedback system.
For solving the problems of the technologies described above, operational amplifier provided by the invention comprises two-stage amplifying circuit and biasing circuit.
The first order of described two-stage amplifying circuit is Foldable cascade amplifying circuit, and the second level is push-pull output circuit.
Described Foldable cascade amplifying circuit comprises Differential input circuit and is total to grid amplifying circuit.
Described Differential input circuit comprises the differential pair tube of the first PMOS and the second PMOS composition, the source electrode of described first PMOS and described second PMOS links together, the grid of described first PMOS and described second PMOS is the input of differential voltage input signal, and the drain electrode of described first PMOS and described second PMOS exports two-pass DINSAR current signal respectively.
Described grid amplifying circuit altogether comprises the first NMOS tube and the second NMOS tube, form the first Foldable cascade structure branch road by described first PMOS and described first NMOS tube, form the second Foldable cascade structure branch road by described second PMOS and described second NMOS tube; The source electrode of described first NMOS tube is connected with the drain electrode of described first PMOS, the source electrode of described second NMOS tube is connected with the drain electrode of described second PMOS, the grid of described first NMOS tube and described second NMOS tube is all connected to bias voltage one, the source electrode of described first NMOS tube receives the described differential current signal exported by the drain electrode of described first PMOS, and the source electrode of described second NMOS tube receives the described differential current signal exported by the drain electrode of described second PMOS.
The drain electrode of described first NMOS tube connects the drain electrode of the 3rd PMOS, and the source electrode of described 3rd PMOS connects the drain electrode of the 4th PMOS, and the source electrode of described 4th PMOS connects positive supply.
The source electrode of the 5th PMOS connects the drain electrode of the 6th PMOS, and the source electrode of described 6th PMOS connects positive supply; Described 3rd PMOS is all connected the second bias voltage with the grid of described 5th PMOS, and described 4th PMOS is all connected the drain electrode of described first NMOS tube with the grid of described 6th PMOS; The drain electrode of described second NMOS tube and the drain electrode of described 5th PMOS are connected to described push-pull output circuit as two outputs.
Described push-pull output circuit comprises: the 7th PMOS, the 8th PMOS, the 3rd NMOS tube and the 4th NMOS tube, the source electrode of described 3rd NMOS tube, the drain electrode of described 7th PMOS and the grid of described 4th NMOS tube are all connected the drain electrode of described second NMOS tube, and the drain electrode of described 3rd NMOS tube, the source electrode of described 7th PMOS and the grid of described 8th PMOS are all connected the drain electrode of described 5th PMOS; The source ground of described 4th NMOS tube or negative supply, the source electrode of described 8th PMOS connects positive supply, and the drain electrode of described 4th NMOS tube and described 8th PMOS links together and exports the voltage output signal of amplifying as output; The grid of described 3rd NMOS tube connects the 3rd bias voltage, and the grid of described 7th PMOS connects the 4th bias voltage.
Described biasing circuit is used for providing bias voltage for described two-stage amplifying circuit, and bias voltage comprises described first bias voltage, described second bias voltage, described 3rd bias voltage and described 4th bias voltage.
Further improvement is, described first PMOS and the source electrode of described second PMOS of described Differential input circuit are all connected the drain electrode of the 9th PMOS, and the source electrode of described 9th PMOS connects positive supply, and the grid of described 9th PMOS connects the 5th bias voltage.
The drain electrode of described first PMOS connects the drain electrode of the 5th NMOS tube, the drain electrode of described second PMOS connects the drain electrode of the 6th NMOS tube, described 5th NMOS tube and the source electrode of described 6th NMOS tube are all connected ground or negative supply, and described 5th NMOS tube is all connected the 6th bias voltage with the grid of described 6th NMOS tube.
Described 5th bias voltage and described 6th bias voltage are all provided by described biasing circuit.
Further improvement is, described push-pull output circuit also comprises the first resistance, the second resistance, the first electric capacity and the second electric capacity; Described first resistance and described first capacitances in series are between the grid and drain electrode of described 8th PMOS, and described second resistance and described second capacitances in series are between the grid and drain electrode of described 4th NMOS tube.
Further improvement is, described biasing circuit comprises self-start circuit, band-gap reference circuit and multiple current mirror circuit;
Described self-start circuit is for realizing the self-starting of band-gap reference circuit.
Described band-gap reference circuit comprises: the 7th NMOS tube, the 8th NMOS tube, the tenth PMOS, the 11 PMOS, the first PNP transistor, the second PNP transistor and the 3rd resistance.
Described tenth PMOS is all connected positive supply with the source electrode of described 11 PMOS, and the grid of described tenth PMOS and described 11 PMOS links together and exports the second bias voltage.
The grid of described 7th NMOS tube and drain electrode, the grid of described 8th NMOS tube and the drain electrode of described tenth PMOS link together, and the drain electrode of described 8th NMOS tube and the drain electrode of described 11 PMOS link together.
The emitter of described first PNP transistor connects the source electrode of described 7th NMOS tube, the emitter of described second PNP transistor connects the source electrode of described 8th NMOS tube by described 3rd resistance, the base stage of the base stage of described first PNP transistor and collector electrode, described second PNP transistor and collector electrode all ground connection or negative supplies.
Described tenth PMOS, first bias current path of described 7th NMOS tube and described first PNP transistor composition and described 11 PMOS, bias current equal and opposite in direction in second bias current path of described 8th NMOS tube and described second PNP transistor composition, the emitter area that the emitter area of described second PNP transistor is greater than described first PNP transistor makes the second base radio pressure of described second PNP transistor be greater than the first base radio pressure of described first PNP transistor, the size of described bias current is described second base radio pressure and the difference of described first base radio pressure and the resistance ratio of described 3rd resistance.
Further improvement is, described current mirror circuit comprises:
The the first current mirror path be made up of with the 9th NMOS tube connecting into diode form the 12 PMOS, the the second current mirror path be made up of with the tenth NMOS tube connecting into diode form the 13 PMOS, the 3rd current mirror path be made up of with the 14 PMOS connecting into diode form the 11 NMOS tube, by the 12 NMOS tube, the 4th current mirror path that the 15 PMOS connecting into diode form and the 16 PMOS connecting into diode form form, by the 17 PMOS, the 5th current mirror path that the 13 NMOS tube connecting into diode form and the 14 NMOS tube connecting into diode form form.
Described 12 PMOS, described 13 PMOS, described 14 PMOS, described 15 PMOS are all connected positive supply with the source electrode of described 17 PMOS.
Described 12 PMOS, described 13 PMOS and the grid of described 17 PMOS are all connected the grid of described tenth PMOS, make described first current mirror path, image current that the electric current in described second current mirror path and described 5th current mirror path is all described bias current.
The drain and gate of described 9th NMOS tube all connects the drain electrode of described 12 PMOS and exports described first bias voltage, the source ground of described 9th NMOS tube or negative supply.
The drain and gate of described tenth NMOS tube all connects the drain electrode of described 13 PMOS and exports described 6th bias voltage, the source ground of described tenth NMOS tube or negative supply.
Source electrode all ground connection or negative supplies of described 11 NMOS tube and described 12 NMOS tube, described 11 NMOS tube and the grid of described 12 NMOS tube are all connected the grid of described tenth NMOS tube and produce the electric current in described 3rd current mirror path and described 4th current mirror path respectively.
The source electrode of described 14 PMOS connects positive supply, and the drain and gate of described 14 PMOS links together and exports described 5th bias voltage.
The source electrode of described 15 PMOS connects positive supply, grid and the drain electrode of described 15 PMOS are all connected the source electrode of described 16 PMOS, and the grid of described 16 PMOS is all connected the drain electrode of described 12 NMOS tube with drain electrode and exports described 4th bias voltage.
The source ground of described 14 NMOS tube or negative supply, grid and the drain electrode of described 14 NMOS tube are all connected the source electrode of described 13 NMOS tube, and the grid of described 13 NMOS tube is all connected the drain electrode of described 17 PMOS with drain electrode and exports described 3rd bias voltage.
Further improvement is, described self-start circuit comprises:
The inverter be made up of the 15 NMOS tube and the 18 PMOS, the source ground of described 15 NMOS tube or negative supply, the source electrode of described 18 PMOS connects positive supply, the grid of described 15 NMOS tube and described 18 PMOS all connects sleep signal, described sleep signal is additional low level signal, and the drain electrode of described 15 NMOS tube and described 18 PMOS links together and exports the inversion signal of described sleep signal.
16 NMOS tube and the 19 PMOS, described 16 NMOS tube and the grid of described 19 PMOS are all connected the drain electrode of described 15 NMOS tube, the drain electrode of described 16 NMOS tube and described 19 PMOS links together, the source ground of described 16 NMOS tube or negative supply, the source electrode of described 19 PMOS connects positive supply.
17 NMOS tube, the 20 PMOS and the 21 PMOS, the 22 PMOS and the 23 PMOS, the source ground of described 17 NMOS tube or negative supply, the grid of described 17 NMOS tube, the grid of described 23 PMOS and the drain electrode of described 15 NMOS tube link together, and the drain electrode of described 17 NMOS tube, the grid of described 21 PMOS and the drain electrode of described 22 PMOS link together.
The drain electrode of described 21 PMOS connects the drain electrode of described 7th NMOS tube, and the drain and gate of described 20 PMOS all connects the source electrode of described 21 PMOS, and the source electrode of described 20 PMOS connects positive supply.
The source electrode of described 22 PMOS and described 23 PMOS all connects positive supply, and grid and the drain electrode of described 23 PMOS of described 22 PMOS are all connected the grid of described tenth PMOS.
The present invention adopts the structure of two-stage amplifying circuit, the Foldable cascade amplifying circuit of the first order can provide the high-gain of more than 90dB for circuit, the push-pull output circuit of the second level has good driving force, the bias voltage of amplifying circuit is provided by the biasing circuit that have employed band-gap reference circuit, the bias voltage of circuit can be made highly stable, and the characteristic of high-gain and bias stabilization can make circuit application of the present invention in high-precision closed loop feedback system.
Accompanying drawing explanation
Below in conjunction with the drawings and specific embodiments, the present invention is further detailed explanation:
Fig. 1 is the circuit diagram of the two-stage amplifying circuit of the embodiment of the present invention;
Fig. 2 is the circuit diagram of the biasing circuit of the embodiment of the present invention;
Fig. 3 is the circuit diagram of the integrated circuit of the embodiment of the present invention;
Fig. 4 is DC current gain and the frequency response simulation curve of the embodiment of the present invention.
Embodiment
As shown in Figure 3, be the circuit diagram of integrated circuit of the embodiment of the present invention; Embodiment of the present invention operational amplifier comprises two-stage amplifying circuit and biasing circuit; As shown in Figure 1, being the circuit diagram of the two-stage amplifying circuit of the embodiment of the present invention, is the enlarged drawing of the two-stage amplifying circuit in Fig. 3; As shown in Figure 2, being the circuit diagram of the biasing circuit of the embodiment of the present invention, is the enlarged drawing of the biasing circuit in Fig. 3.
The first order of described two-stage amplifying circuit is Foldable cascade amplifying circuit, and the second level is push-pull output circuit.
Described Foldable cascade amplifying circuit comprises Differential input circuit and is total to grid amplifying circuit.Described Foldable cascade amplifying circuit can provide high-gain.
Described Differential input circuit comprises the differential pair tube that the first PMOS M1 and the second PMOS M2 forms, the source electrode of described first PMOS M1 and described second PMOS M2 links together, the grid of described first PMOS M1 and described second PMOS M2 is the input of differential voltage input signal vin and vip, and the drain electrode of described first PMOS M1 and described second PMOS M2 exports two-pass DINSAR current signal respectively.
Described first PMOS M1 and the source electrode of described second PMOS M2 of described Differential input circuit are all connected the drain electrode of the 9th PMOS M3, and the source electrode of described 9th PMOS M3 meets positive supply AVDD, and the grid of described 9th PMOS M3 meets the 5th bias voltage Vb5.
The drain electrode of described first PMOS M1 connects the drain electrode of the 5th NMOS tube M4, the drain electrode of described second PMOS M2 connects the drain electrode of the 6th NMOS tube M5, described 5th NMOS tube M4 and the source electrode of described 6th NMOS tube M5 are all connected ground or negative supply AVSS, and described 5th NMOS tube M4 is connected the 6th bias voltage Vb6 with the grid of described 6th NMOS tube M5.
Described grid amplifying circuit altogether comprises the first NMOS tube M6 and the second NMOS tube M7, form the first Foldable cascade structure branch road by described first PMOS M1 and described first NMOS tube M6, form the second Foldable cascade structure branch road by described second PMOS M2 and described second NMOS tube M7; The source electrode of described first NMOS tube M6 is connected with the drain electrode of described first PMOS M1, the source electrode of described second NMOS tube M7 is connected with the drain electrode of described second PMOS M2, the grid of described first NMOS tube M6 and described second NMOS tube M7 is all connected to bias voltage one Vb1, the source electrode of described first NMOS tube M6 receives the described differential current signal exported by the drain electrode of described first PMOS M1, and the source electrode of described second NMOS tube M7 receives the described differential current signal exported by the drain electrode of described second PMOS M2.
The drain electrode of described first NMOS tube M6 connects the drain electrode of the 3rd PMOS M8, and the source electrode of described 3rd PMOS M8 connects the drain electrode of the 4th PMOS M10, and the source electrode of described 4th PMOS M10 connects positive supply AVDD.
The source electrode of the 5th PMOS M9 connects the drain electrode of the 6th PMOS M11, and the source electrode of described 6th PMOS M11 connects positive supply AVDD; Described 3rd PMOS M8 is connected the second bias voltage Vb2 with the grid of described 5th PMOS M9, and described 4th PMOS M10 is connected the drain electrode of described first NMOS tube M6 with the grid of described 6th PMOS M11; The drain electrode of described second NMOS tube M7 and the drain electrode of described 5th PMOS M9 are connected to described push-pull output circuit as two outputs.
Described push-pull output circuit comprises: the 7th PMOS M12, the 8th PMOS M14, the 3rd NMOS tube M13 and the 4th NMOS tube M15, the source electrode of described 3rd NMOS tube M13, the drain electrode of described 7th PMOS M12 and the grid of described 4th NMOS tube M15 are all connected the drain electrode of described second NMOS tube M7, and the drain electrode of described 3rd NMOS tube M13, the source electrode of described 7th PMOS M12 and the grid of described 8th PMOS M14 are all connected the drain electrode of described 5th PMOS M9; The source ground of described 4th NMOS tube M15 or negative supply AVSS, the source electrode of described 8th PMOS M14 meets positive supply AVDD, and the drain electrode of described 4th NMOS tube M15 and described 8th PMOS M14 links together and exports the voltage output signal vout amplified as output; The grid of described 3rd NMOS tube M13 connects grid connection the 4th bias voltage Vb4 of the 3rd bias voltage Vb3, described 7th PMOS M12.
As from the foregoing, described push-pull output circuit comprises two loops: the loop that the 7th PMOS M12 and the 8th PMOS M14 forms and the loop that the 3rd NMOS tube M13 and the 4th NMOS tube M15 forms, fixing pressure drop can be defined like this between described 8th PMOS M14 and the grid of described 4th NMOS tube M15, thus can effectively raise the efficiency, and there is good driving force.
Described push-pull output circuit also comprises the first resistance R1, the second resistance R2, the first electric capacity C1 and the second electric capacity C2; Described first resistance R1 and described first electric capacity C1 is connected between the grid of described 8th PMOS M14 and drain electrode, and described second resistance R2 and described second electric capacity C2 is connected between the grid of described 4th NMOS tube M15 and drain electrode.Described first resistance R1, described second resistance R2 and described first electric capacity C1 are zero-regulator resistor and building-out capacitor, for improving the frequency response of amplifier respectively.
As shown in Figure 2, described biasing circuit is used for providing bias voltage for described two-stage amplifying circuit, bias voltage comprises described first bias voltage Vb1, described second bias voltage Vb2, described 3rd bias voltage Vb3, described 4th bias voltage Vb4, described 5th bias voltage Vb5 and described 6th bias voltage Vb6, and described biasing circuit comprises self-start circuit, band-gap reference circuit and multiple current mirror circuit;
Described band-gap reference circuit comprises: the 7th NMOS tube M30, the 8th NMOS tube M31, the tenth PMOS M28, the 11 PMOS M29, the first PNP transistor Q1, the second PNP transistor Q2 and the 3rd resistance R3.
Described tenth PMOS M28 is connected positive supply AVDD with the source electrode of described 11 PMOS M29, and the grid of described tenth PMOS M28 and described 11 PMOS M29 links together and exports the second bias voltage Vb2.
The grid of described 7th NMOS tube M30 and drain electrode, the grid of described 8th NMOS tube M31 and the drain electrode of described tenth PMOS M28 link together, and the drain electrode of described 8th NMOS tube M31 and the drain electrode of described 11 PMOS M29 link together.
The emitter of described first PNP transistor Q1 connects the source electrode of described 7th NMOS tube M30, the emitter of described second PNP transistor Q2 connects the source electrode of described 8th NMOS tube M31 by described 3rd resistance R3, the base stage of the base stage of described first PNP transistor Q1 and collector electrode, described second PNP transistor Q2 and collector electrode all ground connection or negative supply AVSS.
Described tenth PMOS M28, first bias current path of described 7th NMOS tube M30 and described first PNP transistor Q1 composition and described 11 PMOS M29, bias current equal and opposite in direction in second bias current path of described 8th NMOS tube M31 and described second PNP transistor Q2 composition, the emitter area that the emitter area of described second PNP transistor Q2 is greater than described first PNP transistor Q1 makes the second base radio pressure of described second PNP transistor Q2 be greater than the first base radio pressure of described first PNP transistor Q1, the size of described bias current is described second base radio pressure and the difference of described first base radio pressure and the resistance ratio of described 3rd resistance R3.
Described current mirror circuit comprises:
The the first current mirror path be made up of with the 9th NMOS tube M27 connecting into diode form the 12 PMOS M26, the the second current mirror path be made up of with the tenth NMOS tube M25 connecting into diode form the 13 PMOS M24, the 3rd current mirror path be made up of with the 14 PMOS M22 connecting into diode form the 11 NMOS tube M23, by the 12 NMOS tube M21, the 4th current mirror path that the 15 PMOS M19 connecting into diode form and the 16 PMOS M20 connecting into diode form forms, by the 17 PMOS M16, the 5th current mirror path that the 13 NMOS tube M17 connecting into diode form and the 14 NMOS tube M18 connecting into diode form forms.
Described 12 PMOS M26, described 13 PMOS M24, described 14 PMOS M22, described 15 PMOS M19 are connected positive supply AVDD with the source electrode of described 17 PMOS M16.
Described 12 PMOS M26, described 13 PMOS M24 and the grid of described 17 PMOS M16 are all connected the grid of described tenth PMOS M28, make described first current mirror path, image current that the electric current in described second current mirror path and described 5th current mirror path is all described bias current.
The drain and gate of described 9th NMOS tube M27 all connects the drain electrode of described 12 PMOS M26 and exports described first bias voltage Vb1, the source ground of described 9th NMOS tube M27 or negative supply AVSS.
The drain and gate of described tenth NMOS tube M25 all connects the drain electrode of described 13 PMOS M24 and exports described 6th bias voltage Vb6, the source ground of described tenth NMOS tube M25 or negative supply AVSS.
Source electrode ground connection or negative supply AVSS of described 11 NMOS tube M23 and described 12 NMOS tube M21, described 11 NMOS tube M23 and the grid of described 12 NMOS tube M21 are all connected the grid of described tenth NMOS tube M25 and produce the electric current in described 3rd current mirror path and described 4th current mirror path respectively.
The source electrode of described 14 PMOS M22 connects positive supply AVDD, and the drain and gate of described 14 PMOS M22 links together and exports described 5th bias voltage Vb5.
The source electrode of described 15 PMOS M19 meets positive supply AVDD, grid and the drain electrode of described 15 PMOS M19 are all connected the source electrode of described 16 PMOS M20, and the grid of described 16 PMOS M20 is all connected the drain electrode of described 12 NMOS tube M21 with drain electrode and exports described 4th bias voltage Vb4.
The source ground of described 14 NMOS tube M18 or negative supply AVSS, grid and the drain electrode of described 14 NMOS tube M18 are all connected the source electrode of described 13 NMOS tube M17, and the grid of described 13 NMOS tube M17 is all connected the drain electrode of described 17 PMOS M16 with drain electrode and exports described 3rd bias voltage Vb3.
Described self-start circuit, for realizing the self-starting of band-gap reference circuit, comprising:
The inverter be made up of the 15 NMOS tube M40 and the 18 PMOS M39, the source ground of described 15 NMOS tube M40 or negative supply AVSS, the source electrode of described 18 PMOS M39 meets positive supply AVDD, the grid of described 15 NMOS tube M40 and described 18 PMOS M39 all meets sleep signal sleep, described sleep signal sleep is additional low level signal, and the drain electrode of described 15 NMOS tube M40 and described 18 PMOS M39 links together and exports the inversion signal of described sleep signal sleep.
16 NMOS tube M36 and the 19 PMOS M35, described 16 NMOS tube M36 and the grid of described 19 PMOS M35 are all connected the drain electrode of described 15 NMOS tube M40, the drain electrode of described 16 NMOS tube M36 and described 19 PMOS M35 links together, the source ground of described 16 NMOS tube M36 or negative supply AVSS, the source electrode of described 19 PMOS M35 meets positive supply AVDD.
17 NMOS tube M34, the 20 PMOS M37 and the 21 PMOS M38, the 22 PMOS M33 and the 23 PMOS M32, the source ground of described 17 NMOS tube M34 or negative supply AVSS, the grid of described 17 NMOS tube M34, the grid of described 23 PMOS M32 and the drain electrode of described 15 NMOS tube M40 link together, and the drain electrode of described 17 NMOS tube M34, the grid of described 21 PMOS M38 and the drain electrode of described 22 PMOS M33 link together.
The drain electrode of described 21 PMOS M38 connects the drain electrode of described 7th NMOS tube M30, and the drain and gate of described 20 PMOS M37 all connects the source electrode of described 21 PMOS M38, and the source electrode of described 20 PMOS M37 meets positive supply AVDD.
The source electrode of described 22 PMOS M33 and described 23 PMOS M32 all meets positive supply AVDD, and grid and the drain electrode of described 23 PMOS M32 of described 22 PMOS M33 are all connected the grid of described tenth PMOS M28.
In the band-gap reference circuit of the embodiment of the present invention, by arranging (W/L)
28=(W/L)
29, (W/L)
30=(W/L)
31, wherein (W/L)
28for width and the length ratio of the raceway groove of described tenth PMOS M28, (W/L)
29for width and the length ratio of the raceway groove of described 11 PMOS M29, (W/L)
30for width and the length ratio of the raceway groove of described 7th NMOS tube M30, (W/L)
31for width and the length ratio of the raceway groove of described 8th NMOS tube M31, above-mentioned setting can make the electric current on described tenth PMOS M28 and described 11 PMOS M29 Liang Tiaozhi road equal, the bias current equal and opposite in direction namely in described first bias current path and described second bias current path; And can V be made
gS28=V
gS29, V
gS28corresponding to the gate source voltage V of described tenth PMOS M28
gS29corresponding to the gate source voltage of described 11 PMOS M29.
And the emitter area of described second PNP transistor Q2 is greater than the emitter area of described first PNP transistor Q1, order, the emitter area of described second PNP transistor Q2 is m times of the emitter area of described first PNP transistor Q1, if m can be 8, the pressure drop so on the 3rd resistance R3 is V
bE (Q1)the i.e. base emitter voltage of described first PNP transistor Q1 and V
bE (Q2)the i.e. difference Δ V of the base emitter voltage of described second PNP transistor Q2
bE:
ΔV
BE＝V
BE(Q1)-V
BE(Q2)
Due to collector current
Wherein I
sbipolar transistor saturation current, V
t=kT/q, k are Boltzmann constant, and q is electron charge, I
biasfor the bias current of collector current also namely in described first bias current path and described second bias current path of described second PNP transistor Q2 or described first PNP transistor Q1.
Δ V can be obtained
bE=V
tlnm
Voltage Δ V
bEgeneration current on the 3rd resistance R3:
can find out that this bias current and supply voltage have nothing to do, therefore can not be subject to the impact of power-supply fluctuation.
12 PMOS M26 described in described current mirror circuit, described 13 PMOS M24 and described 17 PMOS M16 are by bias current I
biascopy to the branch road at place in certain proportion, flow through load and described 13 NMOS tube M17, the described 14 NMOS tube M18 of diode connection, described tenth NMOS tube M25 and described 9th NMOS tube M27, produces the bias voltage V irrelevant with supply voltage
b3, V
b6and V
b1.The pressure drop had nothing to do with power supply on the described tenth NMOS tube M25 that diode connects, as the pressure drop of described 11 NMOS tube M23 and described 12 NMOS tube M21, produces stable bias voltage V
b5and V
b4, V
b1then the direct grid voltage by M28 and M29 provides.
Bias current I is in order to prevent band-gap reference circuit
biasthe inactive state of=0, the embodiment of the present invention have employed described self-start circuit, the inverter that low level sleep signal sleep process is made up of described 15 NMOS tube M40 and the 18 PMOS M39 is as the grid voltage of described 17 NMOS tube M34, and therefore described 17 NMOS tube M34 is conducting.Work as I
biaswhen=0, described 22 PMOS M33 place branch current is 0, the grid voltage of described 21 PMOS M38 is also 0, then described 20 PMOS M37 and described 21 PMOS M38 place branch road conducting, there is electric current to pass through and flow into described band-gap reference circuit, described band-gap reference circuit is started; Work as I
bias≠ 0, when described band-gap reference circuit normally works, described 22 PMOS M33 place branch road conducting, the grid voltage of described 21 PMOS M38 is high level, described 20 PMOS M37 and described 21 PMOS M38 place branch road not conducting, do not have electric current to pass through.
As shown in Figure 4, be DC current gain and the frequency response simulation curve of the embodiment of the present invention.Can find out, DC current gain can reach 97.9dB, and bandwidth is 6.508MHz, and phase margin is 61degs, and amplifier is stable.
Above by specific embodiment to invention has been detailed description, but these are not construed as limiting the invention.Without departing from the principles of the present invention, those skilled in the art also can make many distortion and improvement, and these also should be considered as protection scope of the present invention.
Claims (6)
1. an operational amplifier, is characterized in that, comprises two-stage amplifying circuit and biasing circuit;
The first order of described two-stage amplifying circuit is Foldable cascade amplifying circuit, and the second level is push-pull output circuit;
Described Foldable cascade amplifying circuit comprises Differential input circuit and is total to grid amplifying circuit;
Described Differential input circuit comprises the differential pair tube of the first PMOS and the second PMOS composition, the source electrode of described first PMOS and described second PMOS links together, the grid of described first PMOS and described second PMOS is the input of differential voltage input signal, and the drain electrode of described first PMOS and described second PMOS exports two-pass DINSAR current signal respectively;
Described grid amplifying circuit altogether comprises the first NMOS tube and the second NMOS tube, form the first Foldable cascade structure branch road by described first PMOS and described first NMOS tube, form the second Foldable cascade structure branch road by described second PMOS and described second NMOS tube; The source electrode of described first NMOS tube is connected with the drain electrode of described first PMOS, the source electrode of described second NMOS tube is connected with the drain electrode of described second PMOS, the grid of described first NMOS tube and described second NMOS tube is all connected to bias voltage one, the source electrode of described first NMOS tube receives the described differential current signal exported by the drain electrode of described first PMOS, and the source electrode of described second NMOS tube receives the described differential current signal exported by the drain electrode of described second PMOS;
The drain electrode of described first NMOS tube connects the drain electrode of the 3rd PMOS, and the source electrode of described 3rd PMOS connects the drain electrode of the 4th PMOS, and the source electrode of described 4th PMOS connects positive supply;
The source electrode of the 5th PMOS connects the drain electrode of the 6th PMOS, and the source electrode of described 6th PMOS connects positive supply; Described 3rd PMOS is all connected the second bias voltage with the grid of described 5th PMOS, and described 4th PMOS is all connected the drain electrode of described first NMOS tube with the grid of described 6th PMOS; The drain electrode of described second NMOS tube and the drain electrode of described 5th PMOS are connected to described push-pull output circuit as two outputs;
Described push-pull output circuit comprises: the 7th PMOS, the 8th PMOS, the 3rd NMOS tube and the 4th NMOS tube, the source electrode of described 3rd NMOS tube, the drain electrode of described 7th PMOS and the grid of described 4th NMOS tube are all connected the drain electrode of described second NMOS tube, and the drain electrode of described 3rd NMOS tube, the source electrode of described 7th PMOS and the grid of described 8th PMOS are all connected the drain electrode of described 5th PMOS; The source ground of described 4th NMOS tube or negative supply, the source electrode of described 8th PMOS connects positive supply, and the drain electrode of described 4th NMOS tube and described 8th PMOS links together and exports the voltage output signal of amplifying as output; The grid of described 3rd NMOS tube connects the 3rd bias voltage, and the grid of described 7th PMOS connects the 4th bias voltage;
Described biasing circuit is used for providing bias voltage for described two-stage amplifying circuit, and bias voltage comprises described first bias voltage, described second bias voltage, described 3rd bias voltage and described 4th bias voltage.
2. operational amplifier as claimed in claim 1, it is characterized in that: described first PMOS and the source electrode of described second PMOS of described Differential input circuit are all connected the drain electrode of the 9th PMOS, the source electrode of described 9th PMOS connects positive supply, and the grid of described 9th PMOS connects the 5th bias voltage;
The drain electrode of described first PMOS connects the drain electrode of the 5th NMOS tube, the drain electrode of described second PMOS connects the drain electrode of the 6th NMOS tube, described 5th NMOS tube and the source electrode of described 6th NMOS tube are all connected ground or negative supply, and described 5th NMOS tube is all connected the 6th bias voltage with the grid of described 6th NMOS tube;
Described 5th bias voltage and described 6th bias voltage are all provided by described biasing circuit.
3. operational amplifier as claimed in claim 1, is characterized in that: described push-pull output circuit also comprises the first resistance, the second resistance, the first electric capacity and the second electric capacity; Described first resistance and described first capacitances in series are between the grid and drain electrode of described 8th PMOS, and described second resistance and described second capacitances in series are between the grid and drain electrode of described 4th NMOS tube.
4. operational amplifier as described in claim 1 or 2 or 3, is characterized in that: described biasing circuit comprises self-start circuit, band-gap reference circuit and multiple current mirror circuit;
Described self-start circuit is for realizing the self-starting of band-gap reference circuit;
Described band-gap reference circuit comprises: the 7th NMOS tube, the 8th NMOS tube, the tenth PMOS, the 11 PMOS, the first PNP transistor, the second PNP transistor and the 3rd resistance;
Described tenth PMOS is all connected positive supply with the source electrode of described 11 PMOS, and the grid of described tenth PMOS and described 11 PMOS links together and exports the second bias voltage;
The grid of described 7th NMOS tube and drain electrode, the grid of described 8th NMOS tube and the drain electrode of described tenth PMOS link together, and the drain electrode of described 8th NMOS tube and the drain electrode of described 11 PMOS link together;
The emitter of described first PNP transistor connects the source electrode of described 7th NMOS tube, the emitter of described second PNP transistor connects the source electrode of described 8th NMOS tube by described 3rd resistance, the base stage of the base stage of described first PNP transistor and collector electrode, described second PNP transistor and collector electrode all ground connection or negative supplies;
Described tenth PMOS, first bias current path of described 7th NMOS tube and described first PNP transistor composition and described 11 PMOS, bias current equal and opposite in direction in second bias current path of described 8th NMOS tube and described second PNP transistor composition, the emitter area that the emitter area of described second PNP transistor is greater than described first PNP transistor makes the second base radio pressure of described second PNP transistor be greater than the first base radio pressure of described first PNP transistor, the size of described bias current is described second base radio pressure and the difference of described first base radio pressure and the resistance ratio of described 3rd resistance.
5. operational amplifier as claimed in claim 4, is characterized in that: described current mirror circuit comprises:
The the first current mirror path be made up of with the 9th NMOS tube connecting into diode form the 12 PMOS, the the second current mirror path be made up of with the tenth NMOS tube connecting into diode form the 13 PMOS, the 3rd current mirror path be made up of with the 14 PMOS connecting into diode form the 11 NMOS tube, by the 12 NMOS tube, the 4th current mirror path that the 15 PMOS connecting into diode form and the 16 PMOS connecting into diode form form, by the 17 PMOS, the 5th current mirror path that the 13 NMOS tube connecting into diode form and the 14 NMOS tube connecting into diode form form,
Described 12 PMOS, described 13 PMOS, described 14 PMOS, described 15 PMOS are all connected positive supply with the source electrode of described 17 PMOS;
Described 12 PMOS, described 13 PMOS and the grid of described 17 PMOS are all connected the grid of described tenth PMOS, make described first current mirror path, image current that the electric current in described second current mirror path and described 5th current mirror path is all described bias current;
The drain and gate of described 9th NMOS tube all connects the drain electrode of described 12 PMOS and exports described first bias voltage, the source ground of described 9th NMOS tube or negative supply;
The drain and gate of described tenth NMOS tube all connects the drain electrode of described 13 PMOS and exports described 6th bias voltage, the source ground of described tenth NMOS tube or negative supply;
Source electrode all ground connection or negative supplies of described 11 NMOS tube and described 12 NMOS tube, described 11 NMOS tube and the grid of described 12 NMOS tube are all connected the grid of described tenth NMOS tube and produce the electric current in described 3rd current mirror path and described 4th current mirror path respectively;
The source electrode of described 14 PMOS connects positive supply, and the drain and gate of described 14 PMOS links together and exports described 5th bias voltage;
The source electrode of described 15 PMOS connects positive supply, grid and the drain electrode of described 15 PMOS are all connected the source electrode of described 16 PMOS, and the grid of described 16 PMOS is all connected the drain electrode of described 12 NMOS tube with drain electrode and exports described 4th bias voltage;
The source ground of described 14 NMOS tube or negative supply, grid and the drain electrode of described 14 NMOS tube are all connected the source electrode of described 13 NMOS tube, and the grid of described 13 NMOS tube is all connected the drain electrode of described 17 PMOS with drain electrode and exports described 3rd bias voltage.
6. operational amplifier as claimed in claim 4, is characterized in that: described self-start circuit comprises:
The inverter be made up of the 15 NMOS tube and the 18 PMOS, the source ground of described 15 NMOS tube or negative supply, the source electrode of described 18 PMOS connects positive supply, the grid of described 15 NMOS tube and described 18 PMOS all connects sleep signal, described sleep signal is additional low level signal, and the drain electrode of described 15 NMOS tube and described 18 PMOS links together and exports the inversion signal of described sleep signal;
16 NMOS tube and the 19 PMOS, described 16 NMOS tube and the grid of described 19 PMOS are all connected the drain electrode of described 15 NMOS tube, the drain electrode of described 16 NMOS tube and described 19 PMOS links together, the source ground of described 16 NMOS tube or negative supply, the source electrode of described 19 PMOS connects positive supply;
17 NMOS tube, the 20 PMOS and the 21 PMOS, the 22 PMOS and the 23 PMOS, the source ground of described 17 NMOS tube or negative supply, the grid of described 17 NMOS tube, the grid of described 23 PMOS and the drain electrode of described 15 NMOS tube link together, and the drain electrode of described 17 NMOS tube, the grid of described 21 PMOS and the drain electrode of described 22 PMOS link together;
The drain electrode of described 21 PMOS connects the drain electrode of described 7th NMOS tube, and the drain and gate of described 20 PMOS all connects the source electrode of described 21 PMOS, and the source electrode of described 20 PMOS connects positive supply;
The source electrode of described 22 PMOS and described 23 PMOS all connects positive supply, and grid and the drain electrode of described 23 PMOS of described 22 PMOS are all connected the grid of described tenth PMOS.
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| CN105743343A (en) * | 2016-03-24 | 2016-07-06 | 西安电子科技大学昆山创新研究院 | High-efficiency DC-DC boost converter |
| CN107168432A (en) * | 2017-05-31 | 2017-09-15 | 成都锐成芯微科技股份有限公司 | Low-power dissipation power supply power supply circuit |
| CN109450382A (en) * | 2018-10-10 | 2019-03-08 | 湖南国科微电子股份有限公司 | A kind of operational amplifier and signal amplifying apparatus |
| CN115173817A (en) * | 2022-09-05 | 2022-10-11 | 深圳市单源半导体有限公司 | Differential amplification circuit, error amplification circuit and trimming method thereof |
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| US5880637A (en) * | 1997-05-05 | 1999-03-09 | Motorola, Inc. | Low-power operational amplifier having fast setting time and high voltage gain suitable for use in sampled data systems |
| CN101958692A (en) * | 2010-10-19 | 2011-01-26 | 杭州电子科技大学 | Low-pressure rail-to-rail calculation magnification circuit |
| CN103066933A (en) * | 2011-08-26 | 2013-04-24 | 联发科技股份有限公司 | Amplifier, fully differential amplifier and delta-sigma modulator |
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| US5880637A (en) * | 1997-05-05 | 1999-03-09 | Motorola, Inc. | Low-power operational amplifier having fast setting time and high voltage gain suitable for use in sampled data systems |
| CN101958692A (en) * | 2010-10-19 | 2011-01-26 | 杭州电子科技大学 | Low-pressure rail-to-rail calculation magnification circuit |
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Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN105743343A (en) * | 2016-03-24 | 2016-07-06 | 西安电子科技大学昆山创新研究院 | High-efficiency DC-DC boost converter |
| CN105743343B (en) * | 2016-03-24 | 2018-06-22 | 西安电子科技大学昆山创新研究院 | A kind of high efficiency dc-to-dc type boost converter |
| CN107168432A (en) * | 2017-05-31 | 2017-09-15 | 成都锐成芯微科技股份有限公司 | Low-power dissipation power supply power supply circuit |
| CN107168432B (en) * | 2017-05-31 | 2019-06-25 | 成都锐成芯微科技股份有限公司 | Low-power dissipation power supply power supply circuit |
| CN109450382A (en) * | 2018-10-10 | 2019-03-08 | 湖南国科微电子股份有限公司 | A kind of operational amplifier and signal amplifying apparatus |
| CN109450382B (en) * | 2018-10-10 | 2023-03-14 | 湖南国科微电子股份有限公司 | Operational amplifier and signal amplification device |
| CN115173817A (en) * | 2022-09-05 | 2022-10-11 | 深圳市单源半导体有限公司 | Differential amplification circuit, error amplification circuit and trimming method thereof |
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|---|---|
| CN104639071B (en) | 2017-08-08 |
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