CN106405212A - Double-edge-triggered differential-method-based peak detector and peak detection method - Google Patents
Double-edge-triggered differential-method-based peak detector and peak detection method Download PDFInfo
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- CN106405212A CN106405212A CN201611139197.2A CN201611139197A CN106405212A CN 106405212 A CN106405212 A CN 106405212A CN 201611139197 A CN201611139197 A CN 201611139197A CN 106405212 A CN106405212 A CN 106405212A
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Abstract
The invention discloses a double-edge-triggered differential-method-based peak detector and peak detection method. The peak detector comprising a differentiating circuit, a double-edge-triggered comparator circuit and a sampling holding circuit is characterized in that the differentiating circuit is used for carrying out differential transform processing on an input signal to obtain a differential transform result of the input signal, wherein an obtained differential transform output signal is at a zero-point or reference voltage when the input signal is at a peak or valley value; and the double-edge-triggered comparator circuit receives an output signal from the differentiating circuit, comparing the zero-point or reference voltage with the output signal, and outputting a double-edge-triggered digital control signal based on the comparison result, thereby controlling the sampling holding circuit to carry out a sampling or holding operation. According to the invention, the provided detector has advantages of high operating frequency, high detection precision, and self resetting; and high-frequency and high-precision peak value is realized. The peak detector and the peak detection method can be applied to various complicated signal sampling systems widely.
Description
Technical field
The present invention relates to peakvalue's checking is and in particular to differential method peak detector and peak-value detection method are triggered in double edge.
Background technology
The effect of peakvalue's checking is that the peak value to input signal extracts, and produces output voltage and is equal to input signal peak value
Voltage.Peak detection circuit is worth most in automatic growth control (AGC) circuit, sensor to be asked for circuit, extensively should in AD/DA circuit
With foundation, the accuracy of detection of peak detection circuit and the operating frequency selecting generally as gain-programmed amplifier multiple at ordinary times
Directly determine the performance of parameter acquisition system etc. index.With the continuous improvement of current demand signal frequency, signal kinds various
Change development, the operating frequency to peak detector and accuracy of detection etc. it is also proposed higher requirement.
The instruction that conventional peak testing circuit is kept by the use of the positively biased characteristic of diode as sampling judges, has detection essence
Degree is high, the simple advantage of structure, but the frequency response characteristic due to diode, its input signal operating frequency is by the very day of one's doom
System, and when being applied to complicated sampling system that input signal amplitude is continually changing, need to introduce extra reset circuit and
Corresponding logical algorithm is it is more difficult to meet the demand of complex parameters sampling system.
Content of the invention
The technical problem to be solved is to provide double edges triggering differential method peak detector and peakvalue's checking inspection
Survey method, realizes the peak values in real time detection to high-frequency input signal.
In order to solve above-mentioned technical problem, first technical scheme of the present invention is：A kind of double edge triggering differential method signal
Peak detector, including differential circuit, double along trigger comparator circuit and sampling hold circuit；It is characterized in：
Described differential circuit is used for carrying out differential transform process to input signal, obtains the differential transform knot of input signal
Really, and when input signal is in peak value or valley, the differential transform output signal obtaining is exactly in zero point or reference voltage；
It is easy to comparator and be compared process；
Described double output signal receiving differential circuit along trigger comparator circuit, by itself and zero-point voltage or reference voltage
It is compared, and according to the double digital controlled signal along triggering of comparative result output, to control sampling hold circuit to be sampled
Or keep operation；
Described sampling hold circuit includes two-stage emitter follower, high-speed switching circuit and holding capacitor；First order emitter-base bandgap grading
Follower and differential circuit receives input signal simultaneously, input signal is followed in its output, and the output of second level emitter follower is
For final peakvalue's checking result output；High-speed switching circuit is connected to output and the second level emitter-base bandgap grading of first order emitter follower
Between the input of follower, and the input of second level emitter follower is grounded by holding capacitor, high-speed switching circuit
Break-make is controlled along triggering digital controlled signal along the double of trigger comparator circuit output by double；When high-speed switching circuit turns on,
The output signal of first order emitter follower charges to holding capacitor, and when high-speed switching circuit disconnects, holding capacitor is by the
Two grades of emitter follower electric discharges；The control signal of speed-sensitive switch is provided along trigger comparator circuit by double.
The present invention to realize the differential transform of input signal using differential circuit, when input signal is in peak value or valley
When, the differential transform output signal obtaining is exactly in zero point or reference voltage level it is achieved that high-precision to input signal peak value
Degree judges；To be obtained along trigger comparator circuit for controlling double edges of sampling hold circuit to trigger digital control letter using double
Number.I.e. by being compared with zero-point voltage or reference voltage level to differential transform output signal along trigger comparator circuit using double
Relatively, when input signal is also not up to peak value, differential transform output signal is higher than zero-point voltage or reference voltage level, then double edges are touched
Send out comparator circuit output high level.When input signal reaches peak value, differential transform output signal is equal to zero-point voltage or ginseng
Examine magnitude of voltage, then double along trigger comparator circuit output by high level saltus step to low level.In next cycle, when input letter
When number being in rising edge, differential transform output signal is higher than zero-point voltage or reference voltage level, then output is again by low transition
To high level.Thus obtaining in double along triggering digital controlled signals, realize the real-time control of the speed-sensitive switch to sampling hold circuit.
The present invention input signal to be sampled and is kept two kinds of operations using sampling hold circuit, when double along trigger comparator circuit
When double edge triggering digital controlled signals of output are high level, speed-sensitive switch turns on, and output signal follows input signal change, is
Sample states.When double double edge triggering digital controlled signals along trigger comparator circuit output are low level, speed-sensitive switch closes
Disconnected, output voltage values when output signal is held off within a certain period of time, are hold mode.Turn when the present invention is applied to A/D
When changing circuit, you can carry out corresponding Analog-digital Converter within the retention time.
According to double preferred versions along triggering differential method peak detector of the present invention, described pair along trigger comparator
Comprise comparator core circuit in circuit and digital controlled signal produces circuit；Described comparator core circuit is to be in open loop shape
The operational amplifier of state, when the output signal of differential circuit reaches zero-point voltage or reference voltage, operational amplifier output electricity
Press as high level, when the output signal of differential circuit is less than zero-point voltage or reference voltage, op-amp output voltage is
Low level；Digital controlled signal produces circuit and the output signal of operational amplifier is converted into digital level.
Because, in practical work process, op-amp output voltage is limited by operational amplifier open-loop gain, no
Supply voltage or ground level can be reached it is therefore desirable to digital controlled signal generation circuit is changed, output signal is amplified to
Mains voltage level, thus obtaining the square wave control signal of standard, the switch for controlling sampling hold circuit switches.
According to double preferred versions along triggering differential method peak detector of the present invention, comparator core circuit includes
PMOS MP1～MP13 and NMOS tube MN1～MN10；PMOS MP1 grid and drain electrode connect, and are current input terminal, the source of MP1
Pole connects power supply；PMOS MP1, MP2, the grid of MP3 are connected with each other, and the source electrode of MP2, MP3 connects power supply；PMOS MP4, MP5
Grid level is connected with each other, and the grid of PMOS MP5 is connected with drain electrode, and the source class of PMOS MP4, MP5 connects power supply；PMOS MP6,
MP7 constitutes input stage, and the grid of MP6 connects input positive terminal, and the grid of MP7 connects input negative terminal, and the source class of PMOS MP6, MP7 connects
The drain electrode of MP3；The drain of MP7 connects the drain electrode of MN13；The grid of PMOS MP8 and drain electrode are connected with each other, and the source electrode of MP8 meets MP9
Drain electrode, the grid of PMOS MP8, MP9 is connected with each other, and the source electrode of MP9 connects power supply；The grid of PMOS MP10, MP11 is mutual
Connect, the source electrode of MP10 connects the drain electrode of MP11, and the source electrode of MP11 connects power supply；The grid of PMOS MP12, MP13 is connected with each other,
The source electrode of MP12 connects the drain electrode of MP13, and the source electrode of MP13 connects power supply, and the drain electrode of MP12 connects the source electrode of MP10；The grid of NMOS tube MN1
Pole is connected with drain electrode, and is connected to the drain electrode of PMOS MP2, and the grid of NMOS tube MN1, MN2 is connected with each other, NMOS tube MN2
Drain electrode is connected to the source electrode of NMOS tube MN7, MN8, the source ground of NMOS tube MN1, MN2；The grid of NMOS tube MN3, MN4 is mutual
Connect, the grid level of NMOS tube MN3 and drain electrode are connected with each other, and are connected to PMOS MP4 and the drain electrode of MP6, the source of NMOS tube MN4
Pole is grounded；The grid of NMOS tube MN5, MN6 is connected with each other, and the drain electrode of NMOS tube MN5 is connected to the drain electrode of PMOS MP10, NMOS
The source ground of pipe MN6；The grid of NMOS tube MN13, MN14 is connected with each other, and the grid of NMOS tube MN13 and drain electrode are connected with each other,
And it is connected to the drain electrode of PMOS MP7, the source ground of NMOS tube MN6；NMOS tube MN7, MN8 constitutes input stage, the grid of MN7
Connect input negative terminal, the grid of MN8 connects input positive terminal, and the drain electrode of MN7 connects the drain electrode of PMOS MP5, and the drain electrode of MN8 connects PMOS
The drain electrode of MP8 and the drain electrode of NMOS tube MN14；The source ground of NMOS tube MN13, MN14；The grid phase of NMOS tube MN9, MN10
Connect, and be connected to the grid of PMOS MP12 and MP13, the source electrode of NMOS tube MN9 is connected to the drain electrode of MN10, MN10's
Source ground.
According to double preferred versions along triggering differential method peak detector of the present invention, described digital controlled signal produces
Raw circuit includes sign-changing amplifier and output buffer；Sign-changing amplifier is by PMOS MP14, NMOS tube MN11 and resistance R1 structure
Become, output buffer is made up of NMOS tube MN12 and PMOS MP15；PMOS MP14 mutually interconnects with the grid of NMOS tube MN11
Connect, and be connected to comparator core circuit；The drain electrode of PMOS MP14 is connected with the drain electrode of NMOS tube MN11, and is connected to resistance
R1 one end, the source electrode of PMOS MP14 connects power supply, the source ground of NMOS tube MN11, resistance R1 another termination PMOS MP14 and
The grid of NMOS tube MN11；The drain electrode of PMOS MP15 is connected with the drain electrode of NMOS tube MN12, and the source electrode of PMOS MP15 connects electricity
Source, the source ground of NMOS tube MN12, the drain electrode of PMOS MP15 is connected with the grid of NMOS tube MN12, and is connected to PMOS
The drain electrode of MP14 and the drain electrode of NMOS tube MN11.
Second technical scheme of the present invention be, a kind of using the differential method with double sides carrying out signal peak detection along triggering
Method, is characterized in：
Setting differential method signal peak detector, includes differential circuit, double keeps electric along trigger comparator circuit and sampling
Road；
Described differential circuit is used for carrying out differential transform process to input signal, obtains the differential transform knot of input signal
Really, and when input signal is in peak value or valley, the differential transform output signal obtaining is exactly in zero point or reference voltage；
It is easy to comparator and be compared process；
Described double output signal receiving differential circuit along trigger comparator circuit, by itself and zero-point voltage or reference voltage
It is compared, when the output signal of differential circuit reaches zero-point voltage or reference voltage, described pair along trigger comparator circuit
Output high level digital signal, makes speed-sensitive switch turn on, when the output signal of differential circuit is less than zero-point voltage or reference voltage
When, described pair, along trigger comparator circuit output low level digital signal, makes speed-sensitive switch disconnect；
Described sampling hold circuit is used for input signal being sampled and is kept to operate；When speed-sensitive switch turns on, institute
The output signal stating sampling hold circuit follows input signal change, is sample states；When speed-sensitive switch turns off, described sampling
The output voltage values when output signal of holding circuit is held off, are hold mode.
According to the preferred version using the differential method and double method carrying out signal peak detection along triggering of the present invention,
Described sampling hold circuit includes two-stage emitter follower, speed-sensitive switch and holding capacitor；
First order emitter follower and differential circuit accept input signal simultaneously, and input signal, the second level are followed in its output
The output of emitter follower is final peakvalue's checking result output；Speed-sensitive switch is connected to the defeated of first order emitter follower
Go out and the input of second level emitter follower between, and the input of second level emitter follower is grounded by holding capacitor；
When speed-sensitive switch turns on, the output signal of first order emitter follower charges to holding capacitor, when speed-sensitive switch disconnects, protects
Hold electric capacity to discharge by second level emitter follower, the break-make of high-speed switching circuit is by double double along trigger comparator circuit output
Control along triggering digital controlled signal.
Differential method peak detector is triggered on double edge of the present invention and the beneficial effect of peak-value detection method is：The present invention
By differential transform being carried out to input signal using differential circuit it is achieved that judging to the high accuracy of input signal peak value, and lead to
Cross double edge triggering digital controlled signals and control sampling hold circuits, introduce Self-resetting mechanism, be not required to additional reset unit and answer
Position logic；The present invention and traditional diode-type latch compared with peak detector, have that operating frequency is high, accuracy of detection is high, from
The advantages of reset, it is achieved that the high-precision peakvalue's checking of high-frequency, can be widely used in various sophisticated signal sampling systems.
Brief description
Fig. 1 is double along triggering differential method signal peak detector concept block diagram.
Fig. 2 is the circuit diagram of high-speed switching circuit 5.
Fig. 3 is double circuit diagram along trigger comparator circuit 2.
Fig. 4 is the implementation result figure of differential circuit 1.
Fig. 5 is that double edge triggering differential method peak detectors realize design sketch.
Specific embodiment
Referring to Fig. 1, a kind of double along triggering differential method signal peak detectors, including differential circuit 1, double along trigger comparator
Circuit 2 and sampling hold circuit 3；Wherein：
Described differential circuit 1 is used for carrying out differential transform process to input signal, obtains the differential transform knot of input signal
Really, and when input signal is in peak value or valley, the differential transform output signal obtaining is exactly in zero point or reference voltage；
Described double output signal receiving differential circuit 1 along trigger comparator circuit 2, by itself and zero-point voltage or reference electricity
Pressure is compared, and according to the double digital controlled signal along triggering of comparative result output, controls sampling hold circuit 3 to be sampled
Or keep operation；
Described sampling hold circuit 3 includes two-stage emitter follower, high-speed switching circuit 5 and holding capacitor C4；The first order
Emitter follower 4 and differential circuit 1 accept input signal simultaneously, and input signal is followed in its output, second level emitter follower
Output is final peakvalue's checking result output；High-speed switching circuit 5 is connected to the output of first order emitter follower 4 and the
Between the input of two grades of emitter followers 6, and the input of second level emitter follower is grounded by holding capacitor, opens at a high speed
The break-make closing circuit 5 is controlled along trigger comparator circuit 2 by double；When high-speed switching circuit 5 turns on, first order emitter follower
4 output signal to holding capacitor C4 charge, when high-speed switching circuit 5 disconnects, holding capacitor C4 by second level emitter-base bandgap grading with
Discharge with device 6；The control signal of speed-sensitive switch 5 is provided along trigger comparator circuit 2 by double；Two-stage emitter follower is all using phase
The unit gain follow-up amplifier that output end and negative input end are connected to form is constituted by same operational amplifier.
In a particular embodiment, described differential circuit 1 includes operational amplifier 10, electric capacity C1, C2 and resistance R1；Electric capacity C1
For ac coupling capacitor, a termination input signal, the input negative terminal of another termination operational amplifier 10；Resistance R1 is bridging electricity
Resistance, the input negative terminal of a termination operational amplifier 10, the output end of another termination operational amplifier 10；Electric capacity C2 is bridging electricity
Hold, the input negative terminal of a termination operational amplifier, the output end of another termination operational amplifier.The just termination of operational amplifier 10
Receive the reference voltage connecing reference circuit 7 generation.This differential circuit 1 can carry out differential transform to input signal, works as input signal
When being in peak value or valley, the differential transform output signal obtaining is exactly in reference voltage level.
The operation principle of differential circuit is：When input signal is in rising edge, level is height by low saltus step, is equivalent to
Suddenly switched on high level in R1C1 loop, the voltage due to electric capacity C1 two ends can not be mutated, and that is, the voltage on capacitor needs
Just it is gradually increasing through a charging process, then now electric capacity C1 both end voltage is 0, input voltage fully falls in bridging resistance R1
On, now output voltage reaches highest.Hereafter input signal starts to charge to electric capacity C1, and electric capacity C1 both end voltage is exponentially
Rise, and resistance R1 both end voltage exponentially declines, when input signal reaches peak value, output voltage drop is as low as zero.When
When input signal is in trailing edge, level is low by high saltus step, is equivalent to and has removed suddenly high level in R1C1 loop, equally
Voltage due to electric capacity C1 two ends can not be mutated, and it needs to be discharged by bridging resistance R1, therefore electric capacity C1 both end voltage
Fall at resistance R1 two ends, and due to discharge current and charging current reversely, so output voltage reach minimum.When input signal reaches
During to valley, electric capacity C1 electric discharge closes to an end, so that output voltage gos up to zero.In sum, when input signal reaches
When peak value or valley, output voltage is null value, it is achieved thereby that input signal is carried out with the effect of differential transform.In actual electricity
In the application of road, in order to not adopt negative supply, the input positive terminal of operational amplifier adds reference voltage level, so that differential becomes
Null value in changing is converted to reference voltage level, is easy to comparator and is compared.
As shown in Figure 4, transverse axis is the time to differential circuit implementation result, and the longitudinal axis is voltage.In figure comprises two curves, input
Signal curve and differential transform curve of output, as seen from Figure 4, when input signal reaches peak value, differential transform output letter
Number reach reference voltage level；When input signal reaches valley, differential transform output signal reaches reference voltage level.Fig. 4 shows：
This differential circuit can realize differential transform output.
The present invention adopt high-gain operational amplifier constitute differential circuit, double along trigger comparator and sampling keep electricity
Road, simultaneously utilize NMOS tube constitute speed-sensitive switch, as long as design forming high frequency high-bandwidth high-gain operational amplifier so that it may
Realize high-frequency work characteristic, the operating frequency breaching conventional diode structure limits.
Described sampling hold circuit is by two-stage emitter follower 4,6, high-speed switching circuit 5 and holding capacitor C4, exchange coupling
Close electric capacity C3 to constitute, high-speed switching circuit 5 is connected to output and the second level emitter follower 6 of first order emitter follower 4
Between input, two-stage emitter follower is by identical operational amplifier, and the list that output end and negative input end are connected to form
Position gain follow-up amplifier is constituted；One end receives input signal of electric capacity C3, the input of another termination first order emitter follower 4
Anode；The input of second level emitter follower is grounded also by holding capacitor C4, and the control signal of high-speed switching circuit 5 is by double
There is provided along trigger comparator circuit 2；The output end of second level emitter follower is final peakvalue's checking result output.
The operation principle of sampling hold circuit is：When being in sample states, the output signal of sampling hold circuit is followed
Input signal changes and changes, and when being in hold mode, the output signal of sampling hold circuit remains and is connected to holding order
Moment input signal level values.When circuit is in sample states, high-speed switching circuit 5 turns on, and at this moment holding capacitor charges
C4, if capacitance very little, electric capacity C4 can complete discharge and recharge in a short period of time, at this moment output end output signal follow defeated
Enter signal intensity and change；When circuit is in hold mode, high-speed switching circuit 5 disconnects, at this moment due to second level emitter-base bandgap grading with
Input with device is in high-impedance state, and electric capacity C4 electric discharge is slow, so output signal remains essentially as disconnecting the signal electricity of moment
Level values.
In a particular embodiment, the operational amplifier of the operational amplifier and emitter follower that constitute differential circuit all can wrap
Structure for amplifying containing two-stage, the open-loop gain effectively increasing operational amplifier is amplified at the two poles of the earth, is easy to form the differential of high-frequency work
Circuit and emitter follower circuit, adopt cascode structure simultaneously, circuit can be made to be operated under relatively low operating voltage.
Referring to Fig. 2, high-speed switching circuit 5 is mainly made up of NMOS tube 5MN1 and resistance 5R1,5R2, the leakage of NMOS tube 5MN1
As input, as output end, the grid of NMOS tube 5MN1 connects one end of resistance 5R1 to the source electrode of NMOS tube 5MN1, electricity for pole
The other end of resistance 5R1 is as control signal input；One end of resistance 5R2 is connected to the substrate of NMOS tube 5MN1, and the other end is even
It is connected to ground.
The operation principle of high-speed switching circuit 5 is that, when control signal is for high level, the gate source voltage of NMOS tube 5MN1 is poor
Value is more than its threshold voltage, and NMOS tube 5MN1 turns on, that is, switch in the conduction state.When control signal is for low level, NMOS
The gate source voltage difference of pipe 5MN1 is less than its threshold voltage, and NMOS tube 5MN1 is ended, and that is, switch is off.Resistance 5R1,
5R2 can effectively reduce the grid of NMOS tube 5MN1 and source-drain electrode to the parasitic capacitance on ground, reduces signal during high-frequency operation
Loss, thus improve Peak detection accuracy.
Referring to Fig. 3, double comprise comparator core circuit 8 and digital controlled signal along trigger comparator circuit and produce circuit 9；
Described comparator core circuit 8 is the operational amplifier being in open loop situations, when the output signal of differential circuit 1 reaches zero point electricity
Pressure or during reference voltage, op-amp output voltage is high level, when the output signal of differential circuit 1 be less than zero-point voltage or
During reference voltage, op-amp output voltage is low level；Digital controlled signal produces circuit 9 by the output of operational amplifier
Signal is converted into digital level.
In a particular embodiment, described comparator core circuit 8 include PMOS MP1～MP13 and NMOS tube MN1～
MN10；PMOS MP1 grid and drain electrode connect, and are current input terminal, the source electrode of MP1 connects power supply；PMOS MP1, MP2, MP3
Grid is connected with each other, and the source electrode of MP2, MP3 connects power supply；The grid level of PMOS MP4, MP5 is connected with each other, the grid of PMOS MP5
It is connected with drain electrode, the source class of PMOS MP4, MP5 connects power supply；PMOS MP6, MP7 constitutes input stage, and the grid of MP6 connects input
Anode, the grid of MP7 connects input negative terminal, and the source class of PMOS MP6, MP7 connects the drain electrode of MP3；The drain of MP7 connects the leakage of MN13
Pole；The grid of PMOS MP8 and drain electrode are connected with each other, and the source electrode of MP8 connects the drain electrode of MP9, and the grid of PMOS MP8, MP9 is mutual
Connect, the source electrode of MP9 connects power supply；The grid of PMOS MP10, MP11 is connected with each other, and the source electrode of MP10 connects the drain electrode of MP11,
The source electrode of MP11 connects power supply；The grid of PMOS MP12, MP13 is connected with each other, and the source electrode of MP12 connects the drain electrode of MP13, MP13's
Source electrode connects power supply, and the drain electrode of MP12 connects the source electrode of MP10；The grid of NMOS tube MN1 is connected with drain electrode, and is connected to PMOS MP2
Drain electrode, the grid of NMOS tube MN1, MN2 is connected with each other, and the drain electrode of NMOS tube MN2 is connected to the source electrode of NMOS tube MN7, MN8,
The source ground of NMOS tube MN1, MN2；The grid of NMOS tube MN3, MN4 is connected with each other, and the grid level of NMOS tube MN3 and drain electrode are mutually
Connect, and be connected to PMOS MP4 and the drain electrode of MP6, the source ground of NMOS tube MN4；The grid of NMOS tube MN5, MN6 is mutual
Connect, the drain electrode of NMOS tube MN5 is connected to the drain electrode of PMOS MP10, the source ground of NMOS tube MN6；NMOS tube MN13,
The grid of MN14 is connected with each other, and the grid of NMOS tube MN13 and drain electrode are connected with each other, and is connected to the drain electrode of PMOS MP7,
The source ground of NMOS tube MN6；NMOS tube MN7, MN8 constitutes input stage, and the grid of MN7 connects input negative terminal, and the grid of MN8 connects defeated
Enter anode, the drain electrode of MN7 connects the drain electrode of PMOS MP5, and the drain electrode of MN8 connects the drain electrode of PMOS MP8 and the leakage of NMOS tube MN14
Pole；The source ground of NMOS tube MN13, MN14；The grid of NMOS tube MN9, MN10 is connected with each other, and is connected to PMOS MP12
And the grid of MP13, the source electrode of NMOS tube MN9 is connected to the drain electrode of MN10, the source ground of MN10.
Described digital controlled signal produces circuit 9 and includes sign-changing amplifier and output buffer；Sign-changing amplifier is by PMOS
Pipe MP14, NMOS tube MN11 and resistance R1 are constituted, and output buffer is made up of NMOS tube MN12 and PMOS MP15；PMOS
The grid of MP14 and NMOS tube MN11 is connected with each other, and is connected to comparator core circuit 8, that is, PMOS MP12, MP13 and
The grid of NMOS tube MN9, MN10；The drain electrode of PMOS MP14 is connected with the drain electrode of NMOS tube MN11, and is connected to resistance R1 mono-
End, the source electrode of PMOS MP14 meets power supply, the source ground of NMOS tube MN11, resistance R1 another termination PMOS MP14 and NMOS
The grid of pipe MN11；The drain electrode of PMOS MP15 is connected with the drain electrode of NMOS tube MN12, and the source electrode of PMOS MP15 connects power supply,
The source ground of NMOS tube MN12, the drain electrode of PMOS MP15 is connected with the grid of NMOS tube MN12, and is connected to PMOS
The drain electrode of MP14 and the drain electrode of NMOS tube MN11.
Because inverting amplifier has higher gain and voltage margin, output signal can be amplified to supply voltage electricity
Flat, thus obtaining the square wave control signal of standard, the switch for controlling sampling hold circuit switches.
Described double operation principle along trigger comparator circuit 2 is：Double comprise one along trigger comparator circuit and be in out
The operational amplifier of ring status and a digital controlled signal being used for for comparative result being converted to digital level produce circuit, when
When the output signal of differential circuit 1 reaches reference voltage level, output voltage is height, when the output signal of differential circuit 1 is less than ginseng
When examining magnitude of voltage, output voltage is low,
. a kind of using the differential method and double along triggering the method carrying out signal peak detection, including setting differential method signal peak
Value detector, including differential circuit 1, double along trigger comparator circuit 2 and sampling hold circuit 3；
Described differential circuit 1 is used for carrying out differential transform process to input signal, obtains the differential transform knot of input signal
Really, and when input signal is in peak value or valley, the differential transform output signal obtaining is exactly in zero point or reference voltage；
It is easy to comparator and be compared process；
Described double output signal receiving differential circuit 1 along trigger comparator circuit 2, by itself and zero-point voltage or reference electricity
Pressure is compared, when the output signal of differential circuit 1 reaches zero-point voltage or reference voltage, described double electric along trigger comparator
Road 2 exports high level digital signal, so that speed-sensitive switch 5 is turned on, when the output signal of differential circuit 1 is less than zero-point voltage or reference
During voltage, described pair exports low level digital signal along trigger comparator circuit 2, so that high-speed switching circuit 5 is disconnected；
Described sampling hold circuit 3 is used for input signal being sampled and is kept to operate；When speed-sensitive switch turns on, institute
The output signal stating sampling hold circuit 3 follows input signal change, is sample states；When speed-sensitive switch turns off, described adopt
The output voltage values when output signal of sample holding circuit 3 is held off, are hold mode.
In a particular embodiment, described sampling hold circuit 3 includes two-stage emitter follower, speed-sensitive switch 5 and keeps electricity
Hold C4；
First order emitter follower 4 and differential circuit 1 accept input signal simultaneously, and input signal is followed in its output, and second
The output of level emitter follower is final peakvalue's checking result output；High-speed switching circuit 5 be connected to first order emitter-base bandgap grading with
With between the output of device 4 and the input of second level emitter follower 6, and the input of second level emitter follower passes through to keep
Electric capacity C4 is grounded；When high-speed switching circuit 5 turns on, the output signal of first order emitter follower 4 charges to holding capacitor C4,
When high-speed switching circuit 5 disconnects, holding capacitor C4 is discharged by second level emitter follower 6, the break-make of high-speed switching circuit 5
Controlled along double edge triggering digital controlled signals that trigger comparator circuit 2 exports by double.
Method differential method peak detection circuit implementation result is touched as shown in Figure 5 in double edges, and transverse axis is the time, and the longitudinal axis is voltage.Figure
In comprise three curves, input signal curve, double along triggering digital controlled signal curve, output signal curve, can be seen by Fig. 5
Go out, when input signal is not up to peak value, double is high level along triggering digital controlled signal, and output signal follows input signal；
When input signal reaches peak value, double is low level along triggering digital controlled signal by high level saltus step, and output signal keeps peak
Threshold voltage is constant, the retention time >=0.5* input signal cycle, now can carry out data conversion to output signal；Subsequently double edges
Triggering digital controlled signal is high level by low transition, completes to automatically reset, and output signal continues to follow input signal straight
Peak value to next cycle arrives.Fig. 5 shows：Double edge proposed by the present invention is touched method differential method peak detection circuit and can be realized peak
Value detection output.
Result of implementation above shows：The present invention a kind of double along touch method differential method peak detector have high-frequency work,
The features such as high precision test.The technology of the present invention may apply to the fields such as high-speed AD/DA, complex parameters acquisition system.
Claims (6)
1. a kind of double along triggering differential method signal peak detector, including differential circuit (1), double along trigger comparator circuit (2)
And sampling hold circuit (3)；It is characterized in that：
Described differential circuit (1) is used for carrying out differential transform process to input signal, obtains the differential transform result of input signal,
And when input signal is in peak value or valley, the differential transform output signal obtaining is exactly in zero point or reference voltage；
Described double output signal receiving differential circuit (1) along trigger comparator circuit (2), by itself and zero-point voltage or reference electricity
Pressure is compared, and according to comparative result output double edge triggering digital controlled signal, controls sampling hold circuit (3) to be sampled
Or keep operation；
Described sampling hold circuit (3) includes two-stage emitter follower, high-speed switching circuit (5) and holding capacitor (C4)；First
Level emitter follower (4) and differential circuit (1) accept input signal simultaneously；High-speed switching circuit (5) is connected to first order emitter-base bandgap grading
Between the input of the output of follower (4) and second level emitter follower (6), and the input of second level emitter follower leads to
Cross holding capacitor ground connection, the break-make of high-speed switching circuit (5) is by double double edge triggering numerals exporting along trigger comparator circuit (2)
Control signal controls.
2. according to claim 1 double along triggering differential method signal peak detector it is characterised in that：Described double edges triggering
Comprise comparator core circuit (8) in comparator circuit (2) and digital controlled signal produces circuit (9)；Described comparator core
Circuit (8) is the operational amplifier being in open loop situations, when the output signal of differential circuit (1) reaches zero-point voltage or with reference to electricity
During pressure, op-amp output voltage is high level, when the output signal of differential circuit (1) is less than zero-point voltage or reference voltage
When, op-amp output voltage is low level；Digital controlled signal produces circuit and changes the output signal of operational amplifier
Become digital level.
3. according to claim 2 double along triggering differential method signal peak detector it is characterised in that：Comparator core electricity
Road (8) includes PMOS MP1～MP13 and NMOS tube MN1～MN10；PMOS MP1 grid and drain electrode connect, and are electric current input
End, the source electrode of MP1 connects power supply；PMOS MP1, MP2, the grid of MP3 are connected with each other, and the source electrode of MP2, MP3 connects power supply；PMOS
The grid level of MP4, MP5 is connected with each other, and the grid of PMOS MP5 is connected with drain electrode, and the source class of PMOS MP4, MP5 connects power supply；
PMOS MP6, MP7 constitutes input stage, and the grid of MP6 connects input positive terminal, and the grid of MP7 connects input negative terminal, PMOS MP6, MP7
Source class connect the drain electrode of MP3；The drain of MP7 connects the drain electrode of MN13；The grid of PMOS MP8 and drain electrode are connected with each other, the source of MP8
Pole connects the drain electrode of MP9, and the grid of PMOS MP8, MP9 is connected with each other, and the source electrode of MP9 connects power supply；The grid of PMOS MP10, MP11
Pole is connected with each other, and the source electrode of MP10 connects the drain electrode of MP11, and the source electrode of MP11 connects power supply；The grid of PMOS MP12, MP13 is mutual
Connect, the source electrode of MP12 connects the drain electrode of MP13, and the source electrode of MP13 connects power supply, and the drain electrode of MP12 connects the source electrode of MP10；NMOS tube MN1
Grid be connected with drain electrode, and be connected to the drain electrode of PMOS MP2, the grid of NMOS tube MN1, MN2 is connected with each other, NMOS tube
The drain electrode of MN2 is connected to the source electrode of NMOS tube MN7, MN8, the source ground of NMOS tube MN1, MN2；The grid of NMOS tube MN3, MN4
Pole is connected with each other, and the grid level of NMOS tube MN3 and drain electrode are connected with each other, and is connected to PMOS MP4 and the drain electrode of MP6, NMOS tube
The source ground of MN4；The grid of NMOS tube MN5, MN6 is connected with each other, and the drain electrode of NMOS tube MN5 is connected to the leakage of PMOS MP10
Pole, the source ground of NMOS tube MN6；The grid of NMOS tube MN13, MN14 is connected with each other, the grid of NMOS tube MN13 and drain electrode phase
Connect, and be connected to the drain electrode of PMOS MP7, the source ground of NMOS tube MN6；NMOS tube MN7, MN8 constitutes input stage,
The grid of MN7 connects input negative terminal, and the grid of MN8 connects input positive terminal, and the drain electrode of MN7 connects the drain electrode of PMOS MP5, the drain electrode of MN8
Connect the drain electrode of PMOS MP8 and the drain electrode of NMOS tube MN14；The source ground of NMOS tube MN13, MN14；NMOS tube MN9, MN10
Grid be connected with each other, and be connected to the grid of PMOS MP12 and MP13, the source electrode of NMOS tube MN9 is connected to the leakage of MN10
Pole, the source ground of MN10.
4. double according to Claims 2 or 3 along triggering differential method signal peak detector it is characterised in that：Described numeral
Control signal produces circuit (9) and includes sign-changing amplifier and output buffer；Sign-changing amplifier is by PMOS MP14, NMOS tube
MN11 and resistance R1 is constituted, and output buffer is made up of NMOS tube MN12 and PMOS MP15；PMOS MP14 and NMOS tube
The grid of MN11 is connected with each other, and is connected to comparator core circuit (8)；The drain electrode of PMOS MP14 and the leakage of NMOS tube MN11
Extremely connected, and it is connected to resistance R1 one end, the source electrode of PMOS MP14 meets power supply, the source ground of NMOS tube MN11, resistance R1
Another termination PMOS MP14 and the grid of NMOS tube MN11；The drain electrode of PMOS MP15 is connected with the drain electrode of NMOS tube MN12,
The source electrode of PMOS MP15 connects power supply, the source ground of NMOS tube MN12, the drain electrode of PMOS MP15 and the grid of NMOS tube MN12
Extremely connected, and it is connected to the drain electrode of PMOS MP14 and the drain electrode of NMOS tube MN11.
5. a kind of using the differential method and double along triggering carry out signal peak detection method it is characterised in that：
Setting differential method signal peak detector, include differential circuit (1), double along trigger comparator circuit (2) and sampling holding
Circuit (3)；
Described differential circuit (1) is used for carrying out differential transform process to input signal, obtains the differential transform result of input signal,
And when input signal is in peak value or valley, the differential transform output signal obtaining is exactly in zero point or reference voltage；
Described double output signal receiving differential circuit (1) along trigger comparator circuit (2), by itself and zero-point voltage or reference electricity
Pressure is compared, and when the output signal of differential circuit (1) reaches zero-point voltage or reference voltage, described pair along trigger comparator
Circuit (2) exports high level digital signal, so that high-speed switching circuit (5) is turned on, when the output signal of differential circuit (1) is less than zero
When point voltage or reference voltage, described pair exports low level digital signal along trigger comparator circuit (2), makes high-speed switching circuit
(5) disconnect；
Described sampling hold circuit (3) is used for input signal being sampled and is kept to operate；When speed-sensitive switch turns on, described
The output signal of sampling hold circuit (3) follows input signal change, is sample states；When speed-sensitive switch turns off, described adopt
The output voltage values when output signal of sample holding circuit (3) is held off, are hold mode.
6. according to claim 5 using the differential method and double along triggering the method carrying out signal peak detection, its feature exists
In：
Described sampling hold circuit (3) includes two-stage emitter follower, speed-sensitive switch (5) and holding capacitor (C4)；
First order emitter follower (4) and differential circuit (1) accept input signal simultaneously, and high-speed switching circuit (5) is connected to the
Between the input of the output of one-level emitter follower (4) and second level emitter follower (6), and second level emitter follower
Input passes through holding capacitor (C4) and is grounded；When high-speed switching circuit (5) turns on, the output of first order emitter follower (4)
Signal charges to holding capacitor (C4), and when high-speed switching circuit (5) disconnects, holding capacitor (C4) passes through second level emitter following
Device (6) discharges；The break-make of high-speed switching circuit (5) by double along trigger comparator circuit (2) export double digital control along triggering
Signal controls.
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| CN111024761A (en) * | 2019-12-31 | 2020-04-17 | 中国计量大学 | Ignition energy measurement method based on high voltage discharge peak detection |
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