CN102571045A - Current comparator - Google Patents
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- CN102571045A CN102571045A CN2010106057749A CN201010605774A CN102571045A CN 102571045 A CN102571045 A CN 102571045A CN 2010106057749 A CN2010106057749 A CN 2010106057749A CN 201010605774 A CN201010605774 A CN 201010605774A CN 102571045 A CN102571045 A CN 102571045A
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Abstract
The invention provides a current comparator, which comprises a complementary metal-oxide-semiconductor transistor (CMOS) inverted amplifier with resistor negative feedback, a push pull amplifier in a second type work mode and a push pull amplifier in a first and second type work mode in sequential cascade connection, wherein the current comparator adopts the input level with the resistor negative feedback, and the input and output impedance of the input level is reduced, so higher response speed is realized. In addition, the current comparator does not need the additionally added bias voltage and current, so the influence caused by process deviation is not easy to occur, and higher precision is realized.
Description
Technical field
The present invention relates to the IC design technical field, particularly the designing technique of current comparator.
Background technology
In recent years, the current type circuit has received the many attention of People more and more because its area is little, speed is fast, advantage such as low in energy consumption.It is exactly current comparator that a very important elementary cell is arranged in the current type circuit, and it has been widely used in various linearities and the nonlinear integrated circuit at present, like analog to digital converter (A/D converter), trigger, voltage controlled oscillator etc.
From the generation of first generation current comparator till now, people have proposed a large amount of implementation methods.The simplest a kind of current comparator structure is as shown in Figure 1, for for simplicity, has saved inverter at the back.In the said current comparator, PMOS pipe M1 and M3, PMOS pipe M5 and M7, NMOS pipe M6 and M8, NMOS pipe M2 and M4 constitute current-mirror structure separately.Said current comparator is that the difference of the output current of two common-source common-gate current mirrors is relatively amplified through the CMOS inverter, gets voltage comparison signal to the end.
Said current comparator is the basis with the current mirror, then will inevitably introduce the input current imbalance that produces because of the current mirror mismatch, thereby reduces the precision of comparator.
To the input imbalance; The traditional solution has following several kinds: 1. adopt compensating circuit to suppress imbalance; Though this method has reduced the input imbalance to a certain extent; But, make the circuit form of comparator become complicated, and introduced the time-delay that produces because of zeroing because need add compensating circuit in addition; 2. adopt the current comparator structure of dual input structure, further reduced time-delay on the basis of said structure to a certain extent, improved precision.
Fig. 2 a, Fig. 2 b, Fig. 3 show a kind of current comparator of dual input structure, and it comprises: P branch input circuit, N branch input circuit and output circuit.
Shown in Fig. 2 a, in the N branch input circuit of the current comparator of said dual input structure, supply voltage Vdd is+3V that Vss is 0V.When static state, each metal-oxide-semiconductor M10, M11 and M12 all work in the saturation region.Their operating current is the bias current of input stage.When signal was imported, along with the rising of i1, the electric current of the metal-oxide-semiconductor M10 that flows through rose, and its gate source voltage Vgs10 is constant.So its drain voltage Vd10 rises.The gate voltage Vg11 that is metal-oxide-semiconductor M11 rises.Because M10 works in the saturation region, so be that a less fluctuation takes place convenient i1, the gate voltage Vg11 of metal-oxide-semiconductor M11 can have greatly changed.Otherwise if reduce or i2 when rising as i1, Vg11 descends.The breadth length ratio of suitable adjusting metal-oxide-semiconductor M10, M11, M12 makes when i1=i2, and the value of Vg11 is roughly about 0.9V (threshold voltage of NMOSFET).Like this, add fashionablely as input signal, Vg11 fluctuates up and down at 0.9V.When i1＞i2, Vg11 rises, greater than 0.9V; When i1＜i2, Vg11 descends, less than 0.9V.
Shown in Fig. 2 b, the P branch input circuit of the current comparator of said dual input structure, the circuit structure of its structure and the input of N branch is similar.When static, metal-oxide-semiconductor M13, M14 and M15 are operated in the saturation region.When signal was imported, if i1 rises or i2 descends, the gate voltage Vg14 of metal-oxide-semiconductor M14 rose.Otherwise if i1 descends or i2 rises, Vg14 descends.The breadth length ratio of suitable adjusting metal-oxide-semiconductor M13, M14, M15, when making i1=i2, Vg14 is about 2.3V.Like this, on the basis of i1 at i2, when fluctuating up and down, wave-wave is moving up and down at 2.3V for Vg14.If i1＞i2, Vg14 is greater than 2.3V; If i1＜i2, Vg14 is less than 2.3V.
In conjunction with Fig. 2 a, Fig. 2 b and shown in Figure 3; In the output-stage circuit of the current comparator of said dual input structure; Through after the processing of above-mentioned input stage, PMOS pipe M17 and NMOS that the Vg11 of the Vg14 of P branch input circuit and N branch input circuit is added to respectively in the output-stage circuit manage on the grid of M16.When Vg14 rises, make that Vg11 also rose simultaneously when PMOS pipe M17 got into sub-threshold region, make NMOS pipe M16 leave sub-threshold region.On the contrary, if Vg14 descends, make PMOS pipe M17 leave sub-threshold region, Vg11 also descends simultaneously, makes NMOS pipe M16 get into sub-threshold region.Like this, at any time, in the output-stage circuit, always have a metal-oxide-semiconductor (M16 or 17) and be in sub-threshold region.The output circuit of whole current comparator is very stable, thereby has greatly reduced the response time (instability of output-stage circuit state is the main factor of restriction comparator response time) of comparator.Steeper and output amplitude is reached to add an inverter (PMOS pipe M19 and NMOS pipe M18 formation) for the edge that makes output waveform to improve output waveform.
Can know based on the foregoing circuit analysis,, improve precision though the current comparator of said dual input structure has reduced time-delay to a certain extent.Yet the biasing circuit of said comparator is complicated and asymmetric, influenced by process deviation, causes bigger input imbalance.In addition, the input impedance of said comparator is bigger, changes hour can produce time-delay greatly at input current.
Summary of the invention
The present invention provides a kind of current comparator, so that response speed and degree of precision faster to be provided.
For addressing the above problem, the present invention provides a kind of comparator, comprising: the push-pull amplifier of the push-pull amplifier of the cmos inverter amplifier with resistive degeneration of cascade, Class B working method and class AB working method successively.
Compared with prior art, above-mentioned current comparator has the following advantages: said current comparator has used the degenerative input stage of strip resistance, has reduced the input and output impedance of input stage, thereby has response speed faster.And, bias voltage that said current comparator need not add and electric current, thereby be not vulnerable to the influence of process deviation, have higher precision.
Description of drawings
Fig. 1 is the simplification circuit structure diagram of existing a kind of current comparator;
Fig. 2 a is the N branch input circuit structure chart of existing another kind of dual input level current comparator;
Fig. 2 b is the P branch input circuit structure chart of the said current comparator of Fig. 2 a;
Fig. 3 is the output-stage circuit structure chart of the said current comparator of Fig. 2 a;
Fig. 4 is a kind of embodiment circuit structure diagram of current comparator of the present invention;
Fig. 5 is the transient response simulation waveform figure that current comparator output voltage shown in Figure 4 changes with input current;
The output voltage of Fig. 6 current comparator shown in Figure 4 is with the simulation waveform figure of input current size variation.
Embodiment
Based on the shortcoming of the current comparator of the current comparator of the existing current-mirror structure of aforementioned analysis and dual input structure, the inventor finds through analyzing the back, can use the cmos inverter amplifier of resistive degeneration to realize less input and output impedance.
Based on above-mentioned design philosophy, a kind of execution mode of current comparator of the present invention comprises: the push-pull amplifier of the push-pull amplifier of the cmos inverter amplifier with resistive degeneration of cascade, Class B working method and class AB working method successively.
Wherein, said current comparator has reduced the input and output impedance of input stage, thereby has had response speed faster owing to used the degenerative input stage of strip resistance.And said current comparator need not as existing dual input structure current comparator, to adopt bias voltage and the electric current that adds, thereby is not vulnerable to the influence of process deviation, has higher precision.
Below realize that through concrete circuit instance further illustrates current comparator of the present invention.
Fig. 4 is a kind of embodiment circuit structure diagram of current comparator of the present invention.With reference to shown in Figure 4, said current comparator comprises: the push-pull amplifier 300 of the push-pull amplifier 200 of the cmos inverter amplifier with resistive degeneration 100 of cascade, Class B working method and class AB working method successively.
Specifically, the cmos inverter amplifier 100 that has a resistive degeneration comprises: PMOS pipe MP1, NMOS pipe MN2 and the 2nd NMOS pipe MN3.Wherein, PMOS pipe MP1 links to each other with the grid of NMOS pipe MN2, receives input current I
In(the input current I here
InTwo input currents poor that promptly is equivalent to existing dual input structure), source electrode links to each other with power vd D, and drain electrode links to each other with the drain electrode of NMOS pipe MN2; The source ground of the one NMOS pipe MN2; The grid of the 2nd NMOS pipe MN3 links to each other with power vd D, and drain electrode links to each other with the grid of NMOS pipe MN2, and source electrode links to each other with the drain electrode of NMOS pipe MN2.
The push-pull amplifier 200 of Class B working method comprises: the 2nd PMOS pipe MP4 and the 3rd NMOS pipe MN5.Wherein, the source electrode of the 2nd PMOS pipe MP4 links to each other with power vd D, and grid links to each other with the grid of the 3rd NMOS pipe MN5, and links to each other with the drain electrode of NMOS pipe MN2, and drain electrode links to each other with the drain electrode of the 3rd NMOS pipe MN5; The source ground of the 3rd NMOS pipe MN5.
The push-pull amplifier 300 of class AB working method comprises: the 4th NMOS pipe MN6, the 5th NMOS pipe MN9, the 6th NMOS pipe MN11, the 7th NMOS pipe MN13, the 3rd PMOS pipe MP7, the 4th PMOS pipe MP8, the 5th PMOS pipe MP10, the 6th PMOS manage MP12.Wherein, the grid of the 4th NMOS pipe MN6 links to each other with the grid of the 3rd PMOS pipe MP7, and links to each other with the drain electrode of the 3rd NMOS pipe MN5, and drain electrode links to each other with power vd D, and source electrode links to each other with the source electrode of the 5th PMOS pipe MP0; The grounded drain of the 3rd PMOS pipe MP7, source electrode links to each other with the source electrode of the 5th NMOS pipe MN9; The 4th PMOS pipe MP8 and the 6th PMOS pipe MP12 constitute current mirror, and the source electrode of the 4th PMOS pipe MP8 and the 6th PMOS pipe MP12 all links to each other with power vd D; The drain electrode of the 5th NMOS pipe MN9 links to each other with the drain electrode of the 4th PMOS pipe MP8, and grid links to each other with power vd D; The drain electrode of the 5th PMOS pipe MP10 links to each other grounded-grid with the drain electrode of the 6th NMOS pipe MN11; The 6th NMOS pipe MN11 and the 7th NMOS pipe MN13 constitute current mirror, the source grounding of the 6th NMOS pipe MN11 and the 7th NMOS pipe MN13; The drain electrode of the 7th NMOS pipe MN13 links to each other with the drain electrode of the 6th PMOS pipe MP12, output comparative result V
Out
Analyze current comparator shown in Figure 4; For the cmos inverter amplifier with resistive degeneration 100; The PMOS pipe MP1 and the NMOS pipe MN2 that are operated in the saturation region are the input stages of entire circuit, and are operated in the resistive degeneration of the 2nd NMOS pipe MN3 of linear zone as cmos inverter amplifier.Utilize small-signal analysis, input, the output resistance that can obtain this inverting amplifier are following:
Wherein, g
M1And g
M2Be respectively the mutual conductance of PMOS pipe MP1 and NMOS pipe MN2, R
3Be the conducting equivalent resistance of the 2nd NMOS pipe MN3, R
SBe the equivalent output impedance of input signal source, r
0=1/ (g
Ds1+ g
Ds2), g
Ds1, g
Ds2Be respectively the leakage conductance of PMOS pipe MP1 and NMOS pipe MN2.
R is arranged generally speaking
3" r
0, R
3" R
S(g
M1+ g
M2) r
0" 1 establishment, so can obtain:
If the difference of input current to be compared is Δ I, i.e. I
In, the voltage swing amplitude of No. 1 and No. 2 node is respectively so:
ΔV
1＝I
inR
in (4)
ΔV
2＝I
inR
inA
v1?(5)
Wherein, A
V1Voltage gain for said cmos inverter amplifier 100.
So, the time constant of said cmos inverter amplifier 100 input points is:
τ
in＝R
inC
in (6)
Wherein, C
InEquivalent input capacitance for input point.The response time of said cmos inverter amplifier 100 output points is:
t
d＝R
outC
out1(7)
Wherein, C
Out1Equivalent capacity for said cmos inverter amplifier 100 output points.
Can be found out that by formula (3) cmos inverter amplifier 100 that has resistive degeneration has less input and output impedance, this can reduce No. 1 and the voltage swing amplitude of No. 2 nodes when input current changes, and this point can be known by formula (4) and formula (5).
Can find out by formula (6) and formula (7) that again less input and output impedance can reduce the response time of said cmos inverter amplifier 100 inputs, output point, thereby makes comparator have response speed faster.
For the CMOS complementary amplifier that is made up of the 2nd PMOS pipe MP4 and the 3rd NMOS pipe MN5, the two is conducting in turn in the course of the work, recommends output with the Class B working method.This amplifier is used for little voltage swing amplitude on No. 2 nodes is further amplified, and the time-delay of its introducing is very little, can ignore.
And in the push-pull amplifier 300 of class AB working method, the 4th NMOS pipe MN6 and the 3rd PMOS pipe MP7 constitute a source class follower respectively, and the 5th NMOS pipe MN9 and the 5th PMOS pipe MP10 are that circuit provides little bias current.Make that when the voltage of No. 3 nodes is 0 the 6th PMOS pipe MP12 and the 7th NMOS pipe MN13 are in critical conduction mode, and then guarantee that this grade circuit is the class AB working method.This push-pull amplifier not only can improve amplitude of output voltage, can also improve circuit provides electric current and ability from absorption current to load.
When the voltage of No. 3 nodes higher (near supply voltage VDD), the electric current among the 4th NMOS pipe MN6 increases, and the electric current among the 3rd PMOS pipe MP7 reduces.Along with the increase of electric current among the 4th NMOS pipe MN6, the electric current among the 6th NMOS pipe MN11 also increases, and the mirror image effect makes the electric current among the 7th NMOS pipe MN13 also increase, and whole electric currents that last circuit provides flow into load through the 7th NMOS pipe MN13.
When the voltage lower (near 0) of No. 3 nodes, the electric current among the 3rd PMOS pipe MP7 increases, and the electric current among the 4th NMOS pipe MN6 reduces.Along with the increase of electric current among the 3rd PMOS pipe MP7, the electric current among the 4th PMOS pipe MP8 also increases, and the mirror image effect makes the electric current among the 6th PMOS pipe MP12 also increase, and whole electric currents that last circuit provides flow into load through the 6th PMOS pipe MP12.Like this, entire circuit does not almost have electric current to slattern, and circuit provides the ability of electric current and absorption current to be improved to load, and the revolution rate increases, and time-delay reduces.
For further verifying the performance of current comparator shown in Figure 4, adopt CMOS technology HSPICE model parameter that the performance of said current comparator has been carried out emulation, the supply voltage of setting emulation is 3V.When simulation output responds the time of delay that changes for input current, with input current I
InBe set to the square-wave signal of positive and negative symmetry, analog result shows as input square wave current I
InAmplitude (shown in the curve 1) when being respectively 0.3 μ A, 1 μ A, 2 μ A, output voltage (shown in the curve 2) from 0 rise to maximum output voltage the needed time of 90% (2.7V) be respectively 5.2ns, 3.2ns, 2.5ns.Shown in Figure 5 for importing square wave current I
InInput current when amplitude is 0.3 μ A and output response wave shape.
And the dual input level structure current comparator of being mentioned in the prior art (for example Fig. 2 a, Fig. 2 b, current comparator shown in Figure 3) at input current i1 respectively than the big 0.3 μ A of i2; 1 μ A; During 2 μ A; Output voltage from 0 rise to maximum output voltage the needed time of 90% (2.7V) be respectively 21.8ns, 12.3ns and 8.5ns.It is thus clear that the response speed of current comparator shown in Figure 4 obviously is superior to dual input level structure current comparator.This mainly is because current comparator shown in Figure 4 has used the degenerative input stage of strip resistance, has reduced the input and output impedance of input stage, thereby has reduced No. 1 and the voltage swing amplitude of No. 2 nodes when input current changes.
For the precision to comparator shown in Figure 4 is simulated, with input current I
InBe set to a slow triangular wave that changes, its waveform is shown in the curve among Fig. 61.Utilize HSPICE emulation can obtain the waveform of output voltage, shown in the curve among Fig. 62 with the input current size variation.Analog result shows, when output voltage when 0 rises to its peaked 90% (2.7V), the corresponding with it input current 0.8nA that descended approximately; And dual input level structure current comparator rises to its peaked 90% o'clock at output voltage, and the variation of output current is near 9.3nA.This shows that current comparator shown in Figure 4 also is higher than prior art dual input level structure current comparator (for example Fig. 2 a, Fig. 2 b, current comparator shown in Figure 3) on precision.This mainly is because bias voltage and the electric current that current comparator shown in Figure 4 need not add is not vulnerable to the influence of process deviation.
In sum, current comparator of the present invention have that speed is fast, precision is high, characteristics such as simple in structure and easy realization.Adopt CMOS technology HSPICE model parameter that the performance of said current comparator is simulated; The result shows that the fastest known current comparator time-delay of said current comparator and prior art is almost equal, and precision is higher than existing several kinds of high-precision current comparators.
More than disclose many aspects of the present invention and execution mode, it will be understood by those skilled in the art that others of the present invention and execution mode.Disclosed many aspects and execution mode just are used to illustrate among the present invention, are not to be to qualification of the present invention, and real protection range of the present invention and spirit should be as the criterion with claims.
Claims (4)
1. a current comparator is characterized in that, comprising: the push-pull amplifier of the push-pull amplifier of the cmos inverter amplifier with resistive degeneration of cascade, Class B working method and class AB working method successively.
2. current comparator as claimed in claim 1 is characterized in that, said cmos inverter amplifier with resistive degeneration comprises: PMOS pipe, NMOS pipe and the 2nd NMOS pipe, wherein,
The one PMOS pipe links to each other with the grid of NMOS pipe, receives input current, and source electrode links to each other with power supply, and drain electrode links to each other with the drain electrode of NMOS pipe;
The source ground of the one NMOS pipe;
The grid of the 2nd NMOS pipe links to each other with power supply, and drain electrode links to each other with the grid of NMOS pipe, and source electrode links to each other with the drain electrode of NMOS pipe.
3. current comparator as claimed in claim 2 is characterized in that, the push-pull amplifier of said Class B working method comprises: the 2nd PMOS pipe and the 3rd NMOS pipe, wherein,
The source electrode of the 2nd PMOS pipe links to each other with power supply, and grid links to each other with the grid of the 3rd NMOS pipe, and links to each other with the drain electrode of NMOS pipe, and drain electrode links to each other with the drain electrode of the 3rd NMOS pipe;
The source ground of the 3rd NMOS pipe.
4. current comparator as claimed in claim 3; It is characterized in that; The push-pull amplifier of said class AB working method comprises: the 4th NMOS pipe, the 5th NMOS pipe, the 6th NMOS pipe, the 7th NMOS pipe, the 3rd PMOS pipe, the 4th PMOS pipe, the 5th PMOS pipe, the 6th PMOS pipe, wherein
The grid of the 4th NMOS pipe links to each other with the grid of the 3rd PMOS pipe, and links to each other with the drain electrode of the 3rd NMOS pipe, and drain electrode links to each other with power supply, and source electrode links to each other with the source electrode of the 5th PMOS pipe;
The grounded drain of the 3rd PMOS pipe, source electrode links to each other with the source electrode of the 5th NMOS pipe;
The 4th PMOS pipe constitutes current mirror with the 6th PMOS pipe, and the source electrode of the 4th PMOS pipe and the 6th PMOS pipe all links to each other with power supply;
The drain electrode of the 5th NMOS pipe links to each other with the drain electrode of the 4th PMOS pipe, and grid links to each other with power supply;
The drain electrode of the 5th PMOS pipe links to each other grounded-grid with the drain electrode of the 6th NMOS pipe;
The 6th NMOS pipe constitutes current mirror with the 7th NMOS pipe, and the 6th NMOS manages the source grounding with the 7th NMOS pipe;
The drain electrode of the 7th NMOS pipe links to each other with the drain electrode of the 6th PMOS pipe, the output comparative result.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2010106057749A CN102571045A (en) | 2010-12-23 | 2010-12-23 | Current comparator |
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|---|---|---|---|
| CN2010106057749A CN102571045A (en) | 2010-12-23 | 2010-12-23 | Current comparator |
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Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103066965A (en) * | 2012-12-19 | 2013-04-24 | 中国科学院深圳先进技术研究院 | Current comparator |
| CN104242923A (en) * | 2013-06-13 | 2014-12-24 | 上海华虹宏力半导体制造有限公司 | Voltage-controlled oscillator |
| CN109175556A (en) * | 2018-11-15 | 2019-01-11 | 扬州万泰电子科技有限公司 | A kind of wire cutting machine tool control device |
| CN109379064A (en) * | 2018-11-21 | 2019-02-22 | 广州金升阳科技有限公司 | A kind of current comparator |
| CN109861673A (en) * | 2019-03-14 | 2019-06-07 | 广州金升阳科技有限公司 | A kind of current comparator |
| CN110794907A (en) * | 2019-08-20 | 2020-02-14 | 上海禾赛光电科技有限公司 | Transient enhanced LDO (low dropout regulator) circuit, CMOS (complementary metal oxide semiconductor) driver power supply circuit and laser system |
| CN111969983A (en) * | 2020-07-20 | 2020-11-20 | 南京大学 | Current subtraction circuit |
| TWI724471B (en) * | 2018-08-10 | 2021-04-11 | 美商高通公司 | Apparatus for comparing input current to set of current thresholds |
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Cited By (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103066965A (en) * | 2012-12-19 | 2013-04-24 | 中国科学院深圳先进技术研究院 | Current comparator |
| CN103066965B (en) * | 2012-12-19 | 2015-09-23 | 中国科学院深圳先进技术研究院 | Current comparator |
| CN104242923A (en) * | 2013-06-13 | 2014-12-24 | 上海华虹宏力半导体制造有限公司 | Voltage-controlled oscillator |
| CN104242923B (en) * | 2013-06-13 | 2017-06-06 | 上海华虹宏力半导体制造有限公司 | Voltage controlled oscillator |
| TWI724471B (en) * | 2018-08-10 | 2021-04-11 | 美商高通公司 | Apparatus for comparing input current to set of current thresholds |
| CN109175556A (en) * | 2018-11-15 | 2019-01-11 | 扬州万泰电子科技有限公司 | A kind of wire cutting machine tool control device |
| CN109175556B (en) * | 2018-11-15 | 2023-09-26 | 扬州万泰电子科技有限公司 | Linear cutting machine control device |
| CN109379064A (en) * | 2018-11-21 | 2019-02-22 | 广州金升阳科技有限公司 | A kind of current comparator |
| CN109379064B (en) * | 2018-11-21 | 2022-08-19 | 广州金升阳科技有限公司 | Current comparator |
| CN109861673A (en) * | 2019-03-14 | 2019-06-07 | 广州金升阳科技有限公司 | A kind of current comparator |
| CN109861673B (en) * | 2019-03-14 | 2024-04-12 | 广州金升阳科技有限公司 | Current comparator |
| CN110794907A (en) * | 2019-08-20 | 2020-02-14 | 上海禾赛光电科技有限公司 | Transient enhanced LDO (low dropout regulator) circuit, CMOS (complementary metal oxide semiconductor) driver power supply circuit and laser system |
| CN111969983A (en) * | 2020-07-20 | 2020-11-20 | 南京大学 | Current subtraction circuit |
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Application publication date: 20120711 |