CN104242923B - Voltage controlled oscillator - Google Patents
Voltage controlled oscillator Download PDFInfo
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- CN104242923B CN104242923B CN201310233941.5A CN201310233941A CN104242923B CN 104242923 B CN104242923 B CN 104242923B CN 201310233941 A CN201310233941 A CN 201310233941A CN 104242923 B CN104242923 B CN 104242923B
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Abstract
Include control voltage gain circuitry and annular oscillation circuit the invention discloses a kind of voltage controlled oscillator；Control voltage gain circuitry includes connecting the first NMOS tube and common-source common-gate current mirror circuit by common source, and the source electrode of the first NMOS tube is grounded by first resistor and realizes source negative feedback.Common-source common-gate current mirror circuit output control voltage is amplified signal and is input to the control end and the output frequency for controlling annular oscillation circuit of annular oscillation circuit.The present invention can improve the linearity of circuit and reduce the power consumption of circuit, can improve the quality of clock signal and for system stabilization provides safeguard.
Description
Technical field
The present invention relates to a kind of semiconductor integrated circuit, more particularly to a kind of voltage controlled oscillator（VCO）.
Background technology
Although VCO has pointed out nearly 100 years with PHASE-LOCKED LOOP PLL TECHNIQUE, is widely used in electronic system, while being wanted to performance
Seek also more and more higher.Present PLL chips are towards frequency is high, bandwidth, integrated level are big, low in energy consumption, cheap, powerful
Develop Deng direction, the design of wherein core cell VCO is most important, current VCO designs faced subject matter regulation model
The limitation enclosed：The centre frequency of some CMOS oscillators may change to twice under extreme flow-route and temperature change, adjust
The limitation of scope may lose its function.Tuning linearity：It is non-linear to cause the stable sexual involution of phaselocked loop but with work
Working frequency more and more higher.Power consumption is excessive to be had a strong impact on it and uses scope.So ensureing system when how to design high-performance VCO circuits
System stabilization needs the subject matter for solving.
Phaselocked loop is with nonlinear reponse system.However, by linear analysis can be basic to its operation make
It is approximate well.In such analysis, Laplace conversion is a very useful instrument.The related notion of transfer function, i.e.,
The input and output end of one linear circuit of description be used to analyze open loop and the closed loop characteristic of PLL in the relation in S domains.Such as
It is a S domains schematic diagram for simplified phaselocked loop shown in Fig. 1.Module 101 is phase frequency detector (phase-frequency
Detectors, PFD) and charge pump merging module, by configured transmission KPFDRepresent, configured transmission KPFDEqual to ICP/ 2 π, Icp namely
It is the Iout in Fig. 1（s）.The impedance of the low pass filter that second-order loop filter is formed is by ZLPF(S)Represent.Module 103 is represented
Voltage controlled oscillator（VCO）, its conversion gain KVCORepresent for VT Vcont（s）The susceptibility of frequency.Pre- frequency dividing circuit
104 and low frequency frequency divider 105 be respectively used to frequency dividing, pre- frequency dividing circuit 104 and the divider ratios of low frequency frequency divider 105 are respectively by P and N
Represent, the output frequency signal Fout of module 103, the output frequency signal Fout/P of pre- frequency dividing circuit 104, low frequency frequency divider 105 is defeated
Go out frequency signal Fbck.Above-mentioned synthesizer is that the open-loop transmission function of phaselocked loop can be defined as：
Show a limit for the at the origin caused by VCO.The dynamic characteristic of whole loop is by loop filter
Transfer function determines that it is an impedance function in this example, and charge pump current is converted into the VT of VCO for it.
ZLPFS () is expressed as
Equation（2）Show first limit of loop filter in ωp1At=0, zero point exists
ωz=1/R1C1（3）
Two limits of at the origin（First is produced due to VCO, and second is ωp1）Can compensate when phase margin is
Loop is unstable when 0.Add ωzLoop is stabilized, suitable position can provide enough phase margins, to ensure loop
Stabilization.In order to obtain one for second significant expression formula of limit, i.e., and ωzIt is related.By in formula（2）Middle introducing
Variable m=(C1+C2)/C2, obtain：
It shows that the limit of second loop filter exists
By ZLPF(s) abbreviation into
Use formula（6）, open-loop transmission function can be re-written as：
Wherein A is
The amplitude and phase of open-loop transmission function can be drawn in Bode diagram, for check the position of pole and zero with
And the condition of loop stability.As shown in Fig. 2 in zero point ωz, slope drops to 20dB/dec by 40, it is often more important that, make phase
Increase since -180 degree.Amplitude be 1 or 0-dB at phase value referred to as phase margin（PM）.The crosspoint of frequency is PLL
Loop bandwidth, by ωcRepresent.The calculating of the latter is by making formula（7）HOLS the amplitude of () is 1, so as to obtain：
Wherein, φz=tan-1(ωc/ωz), φp2=tan-1(ωc/ωp2).Phase margin is expressed as：
It is desirable that to make the maximum stabilization to ensure loop of phase margin, decision pole and zero position is also met certainly
The change of the resistance and capacitance put.Possible maximum phase nargin can be by formula（10）Differentiated and obtained
Arrive：
By ωcSubstitute into formula（10）, obtain maximum phase nargin：
Formula（11）,（12）Show, for best stabilized（Maximum PM）, unit gain crosspoint should be zero point and the
The geometrical mean of two limits, because this is the phase position farthest from 180 degree.Maximum phase nargin is by capacitance ratio（m）Only
One determines that it is also second limit（ωp2）And zero point（ωz）Ratio.Make
It may be noted that sin (φz)=cos (φp2), by formula（9）It is reduced to
The closed loop transmission function of three rank PLL is：
Understand that voltage controlled oscillator determines the height of phase-locked loop performance to a certain extent by above theory analysis, so VCO
The design of module is most important.The important performance characteristic of wherein VCO designs is such as：Adjustable range, tuning linearity, output amplitude,
Power consumption and noise inhibiting ability intuitively reflect the quality of VCO performances.In addition, USB2.0 interface circuits are for various cores
The general module design of piece, using extensive；When work is in high speed mode, it is necessary to will be to USB2.0 interface circuits using phaselocked loop
The clock of 480MHz is provided, so the wherein performance parameter of VCO such as adjustable range, tuning linearity, output amplitude, power consumption, phase
Position noise etc. is improved with needed for optimizing USB2.0 interface circuits all to whole system important to VCO
The clock signal of 480MHz is a critically important problem.
The content of the invention
The technical problems to be solved by the invention are to provide a kind of voltage controlled oscillator, can improve the linearity of circuit and reduce
The power consumption of circuit, can improve the quality of clock signal and for system stabilization provides safeguard.
In order to solve the above technical problems, the voltage controlled oscillator that the present invention is provided includes that control voltage gain circuitry and annular are shaken
Swing circuit.
Control voltage gain circuitry includes：
First NMOS tube, the control voltage of the grid connection input of first NMOS tube, the source of first NMOS tube
Pole is grounded by first resistor, the drain electrode connection common-source common-gate current mirror circuit of first NMOS tube.
The common-source common-gate current mirror circuit includes the first PMOS, the second PMOS, the 3rd PMOS and the 4th PMOS
Pipe, the drain electrode of first NMOS tube, the drain electrode of first PMOS, the 3rd PMOS and the 4th PMOS
Grid links together, and the grid of first PMOS and second PMOS all connects same bias voltage, described first
The drain electrode connection of the source electrode of PMOS and the 3rd PMOS, the source electrode of second PMOS and the 4th PMOS
The source electrode of drain electrode connection, the 3rd PMOS and the 4th PMOS all connects supply voltage, the leakage of second PMOS
Pole output control voltage amplification signal.
The control voltage amplifies signal input to the control end of the annular oscillation circuit and for controlling the annular
The output frequency of oscillating circuit.
Further improvement is that the bias voltage is provided by the first biasing circuit, and first biasing circuit includes：The
Two NMOS tubes, the 3rd NMOS tube, the 5th PMOS and the 6th PMOS, the source ground of second NMOS tube, the described 3rd
The source electrode of NMOS tube connects the drain and gate of second NMOS tube, the grid of the 5th PMOS and drain electrode and described
The grid of the 7th PMOS and drain electrode link together and as the output end of the bias voltage, the source of the 5th PMOS
Pole connects the drain and gate of the 6th PMOS, and the source electrode of the 6th PMOS connects supply voltage.
Further improvement be, the annular oscillation circuit is joined end to end shape by three-level fully differential phase inverter delay unit
Into.
The fully differential phase inverter delay units at different levels include normal phase input end, inverting input, positive output end, anti-phase
Output end and control end, fully differential described in the normal phase input end connection upper level of the fully differential phase inverter delay units at different levels are anti-
The positive output end of phase device delay unit, the inverting input connection upper level institute of the fully differential phase inverter delay units at different levels
The reversed-phase output of fully differential phase inverter delay unit is stated, the positive output end of the fully differential phase inverter delay units at different levels connects
The positive output end of fully differential phase inverter delay unit described in next stage is connected to, the fully differential phase inverter delay units at different levels
Reversed-phase output is connected to the reversed-phase output of fully differential phase inverter delay unit described in next stage.
The control end of the fully differential phase inverter delay units at different levels all connects the control voltage and amplifies signal.
Further improvement is that the annular oscillation circuit also includes six phase inverters, the fully differential phase inverters at different levels
The positive output end and reversed-phase output of delay unit export a clock signal by a phase inverter respectively.
Further improvement is that the fully differential phase inverter delay units at different levels all include respectively：
The first negative circuit being made up of the 4th NMOS tube and the 7th PMOS, the 4th NMOS tube and the described 7th
The grid of PMOS is connected together as inverting input, the drain electrode connection of the 4th NMOS tube and the 7th PMOS
Together as reversed-phase output.
The second negative circuit being made up of the 5th NMOS tube and the 8th PMOS, the 5th NMOS tube and the described 7th
The grid of PMOS is connected together as normal phase input end, the drain electrode connection of the 5th NMOS tube and the 8th PMOS
Together as positive output end.
The source electrode of the 7th PMOS and the 8th PMOS all connects the control voltage and amplifies signal, the described 4th
The source electrode of NMOS tube and the 5th NMOS tube is all grounded.
The source ground of the 6th NMOS tube and the 7th NMOS tube, the 6th NMOS tube and the 7th NMOS tube, it is described
The drain electrode of the 6th NMOS tube, the grid of the 7th NMOS tube are all connected with the reversed-phase output, the 7th NMOS tube
Drain electrode, the grid of the 6th NMOS tube are all connected with the positive output end.
Further improvement is that the fully differential phase inverter delay units at different levels are respectively further comprised：
8th NMOS tube, the source electrode of the 8th NMOS tube connects the source electrode of the 4th NMOS tube, the 8th NMOS
The grid of pipe, drain electrode and source electrode link together.
9th NMOS tube, the source electrode of the 9th NMOS tube connects the source electrode of the 5th NMOS tube, the 9th NMOS
The grid of pipe, drain electrode and source electrode link together.
9th PMOS, the source electrode of the 9th PMOS connects the source of the 7th PMOS and the 8th PMOS
Pole, the grid of the 9th PMOS, drain electrode and source electrode link together.
Further improvement be, in the clock signal input of the output of the voltage controlled oscillator to USB2.0 interface circuits simultaneously
For the USB2.0 interface circuits provide clock signal.
Further improvement is that the voltage controlled oscillator is for the frequency that the USB2.0 interface circuits provide clock signal
480MHz。
The present invention has the advantages that：
1st, first resistor of the invention can realize source negative feedback, and common-source common-gate current mirror circuit can improve power supply suppression
Than with reference to source negative feedback and the linearity for being designed to improve circuit of common-source common-gate current mirror circuit, so as to expand control
The adjustable range of voltage and can expand circuit output clock signal frequency-tuning range.
2nd, the present invention can realize relatively low integrated circuit average current, so as to reduce the power consumption of circuit.
3rd, the present invention can improve the quality of clock signal and for system stabilization provides safeguard：
Control voltage of the invention amplifies signal by the 3rd PMOS of common-source common-gate current mirror circuit and the 4th PMOS
It is input in annular oscillation circuit after pipe, because the 3rd PMOS and the 4th PMOS can consume certain voltage, it is possible to
So that the amplitude of oscillation of the fully differential phase inverter delay units at different levels of annular oscillation circuit is effectively controlled so that the speed of clock signal
Degree and noise suppressed obtain perfect compromise.
Each clock signal of the present invention is exported by a phase inverter, can realize rail-to-rail output respectively.
The present invention, can by setting the 7th PMOS and the 8th PMOS in fully differential phase inverter delay units at different levels
Positive feedback is realized, accelerates the output end upset of fully differential phase inverter delay units at different levels.
The present invention can be anti-phase for fully differentials at different levels by the setting of the 8th NMOS tube, the 9th NMOS tube and the 9th PMOS
Device delay unit provides shunt capacitance, so as to suppress power supply and Earth noise.
Brief description of the drawings
The present invention is further detailed explanation with reference to the accompanying drawings and detailed description：
Fig. 1 is the S domains schematic diagram of phaselocked loop；
Fig. 2 is the Bode diagram of phaselocked loop；
Fig. 3 is embodiment of the present invention voltage-controlled oscillator circuit figure；
Fig. 4 is the fully differential phase inverter time-delay unit circuit figure employed in the embodiment of the present invention；
Fig. 5 is the output clock signal frequency of the embodiment of the present invention with the variation relation figure of control voltage；
Fig. 6 is that embodiment of the present invention circuit power consumption also exports simulation result；
Fig. 7 is embodiment of the present invention current phase noise simulation result.
Specific embodiment
As shown in figure 3, being embodiment of the present invention voltage-controlled oscillator circuit figure；Embodiment of the present invention voltage controlled oscillator includes control
Voltage Vcontr gain circuitries processed and annular oscillation circuit.
Control voltage Vcontr gain circuitries include：
The control voltage Vcontr of the grid connection input of the first NMOS tube MN1, the first NMOS tube MN1, described the
The source electrode of one NMOS tube MN1 is grounded by first resistor R1, the drain electrode connection common-source common-gate current mirror of the first NMOS tube MN1
Circuit.
The common-source common-gate current mirror circuit include the first PMOS MP1, the second PMOS MP2, the 3rd PMOS MP3 and
4th PMOS MP4, the drain electrode of the first NMOS tube MN1, the drain electrode of the first PMOS MP1, the 3rd PMOS
The grid of MP3 and the 4th PMOS MP4 links together, the first PMOS MP1's and the second PMOS MP2
Grid all connects same bias voltage, the drain electrode connection of the source electrode and the 3rd PMOS MP3 of the first PMOS MP1, institute
State the drain electrode connection of the source electrode and the 4th PMOS MP4 of the second PMOS MP2, the 3rd PMOS MP3 and described the
The source electrode of four PMOS MP4 all connects supply voltage, the drain electrode output control voltage amplification signal of the second PMOS MP2.By
Fig. 3 can be seen that the branch road and second PMOS connected by the first PMOS MP1 and the 3rd PMOS MP3
The branch road composition current mirroring circuit of MP2 and the 4th PMOS MP4 connections, by the second PMOS MP2 and the described 4th
PMOS MP4 constitutes cascade amplifying circuit.
The bias voltage is provided by the first biasing circuit, and first biasing circuit includes：Second NMOS tube MN2,
Three NMOS tube MN3, the 5th PMOS MP5 and the 6th PMOS MP6, the source ground of the second NMOS tube MN2, the described 3rd
The source electrode of NMOS tube MN3 connects the drain and gate of the second NMOS tube MN2, the grid of the 5th PMOS MP5 and leakage
The grid of pole and the 7th PMOS MP7 and drain electrode link together and as the output end of the bias voltage, described
The source electrode of the 5th PMOS MP5 connects the drain and gate of the 6th PMOS MP6, the source electrode of the 6th PMOS MP6
Connect supply voltage.
The control voltage amplifies signal input to the control end of the annular oscillation circuit and for controlling the annular
The output frequency of oscillating circuit.
The annular oscillation circuit is joined end to end by three-level fully differential phase inverter delay unit 1 and is formed.It is at different levels described complete poor
Point phase inverter delay unit 1 include normal phase input end vp, inverting input vn, positive output end vop, reversed-phase output von and
Control end, fully differential phase inverter described in the normal phase input end vp connection upper levels of the fully differential phase inverter delay units 1 at different levels
The positive output end vop of delay unit 1, the inverting input vn connections upper of the fully differential phase inverter delay units 1 at different levels
The reversed-phase output von of the level fully differential phase inverter delay unit 1, the fully differential phase inverter delay units 1 at different levels are just
Phase output terminal vop is connected to the positive output end vop of fully differential phase inverter delay unit 1 described in next stage, at different levels described complete poor
The reversed-phase output von of phase inverter delay unit 1 is divided to be connected to the anti-phase defeated of fully differential phase inverter delay unit 1 described in next stage
Go out to hold von.The control end of the fully differential phase inverter delay units 1 at different levels all connects the control voltage and amplifies signal.
The annular oscillation circuit also includes six phase inverters 2, the positive of the fully differential phase inverter delay units 1 at different levels
Output end vop and reversed-phase output von export a clock signal by a phase inverter 2 respectively.So the embodiment of the present invention can
Realize six outputs of the clock signal of out of phase.
As shown in figure 4, being the fully differential phase inverter time-delay unit circuit figure employed in the embodiment of the present invention；It is at different levels described
Fully differential phase inverter delay unit 1 all includes respectively：
The first negative circuit being made up of the 4th NMOS tube MN4 and the 7th PMOS MP7, the 4th NMOS tube MN4 and
The grid of the 7th PMOS MP7 is connected together as inverting input vn, the 4th NMOS tube MN4 and the described 7th
The drain electrode of PMOS MP7 is connected together as reversed-phase output von.
The second negative circuit being made up of the 5th NMOS tube MN5 and the 8th PMOS MP8, the 5th NMOS tube MN5 and
The grid of the 7th PMOS MP7 is connected together as normal phase input end vp, the 5th NMOS tube MN5 and the described 8th
The drain electrode of PMOS MP8 is connected together as positive output end vop.
The source electrode of the 7th PMOS MP7 and the 8th PMOS MP8 all connects the control voltage and amplifies signal, i.e.,
The source electrode of the 7th PMOS MP7 and the 8th PMOS MP8 is all connected with the drain electrode of the second PMOS MP2；Institute
The source electrode for stating the 4th NMOS tube MN4 and the 5th NMOS tube MN5 is all grounded.
6th NMOS tube MN6 and the 7th NMOS tube MN7, the source of the 6th NMOS tube MN6 and the 7th NMOS tube MN7
Pole is grounded, and the drain electrode of the 6th NMOS tube MN6, the grid of the 7th NMOS tube MN7 all connect with the reversed-phase output von
Connect, the drain electrode of the 7th NMOS tube MN7, the grid of the 6th NMOS tube MN6 are all connected with the positive output end vop.
The source electrode of the 8th NMOS tube MN8, the 8th NMOS tube MN8 connects the source electrode of the 4th NMOS tube MN4, described
The grid of the 8th NMOS tube MN8, drain electrode and source electrode link together.9th NMOS tube MN9, the source of the 9th NMOS tube MN9
Pole connects the source electrode of the 5th NMOS tube MN5, and the grid of the 9th NMOS tube MN9, drain electrode and source electrode link together.The
The source electrode of nine PMOS MP9, the 9th PMOS MP9 connects the 7th PMOS MP7's and the 8th PMOS MP8
Source electrode, the grid of the 9th PMOS MP9, drain electrode and source electrode link together.The 8th NMOS tube MN8, the described 9th
NMOS tube MN9 and the 9th PMOS MP9 is that fully differential phase inverter delay units 1 at different levels provide shunt capacitance, so as to press down
Power supply processed and Earth noise.
Also include reset function part in the embodiment of the present invention, control to realize answering for circuit by reset signal Reset
Position.As shown in figure 3, the drain electrode of the tenth NMOS tube MN10 connects the control voltage Vcontr, source ground, grid connects reset letter
Number Reset.The drain electrode of the 11st NMOS tube MN11 connects the control voltage amplification signal, source ground, grid and connects reset letter
Number Reset.The source electrode of drain electrode connection the 6th PMOS MP6 of the tenth PMOS MP10, the source electrode of the tenth PMOS MP10
Connect supply voltage, grid and meet reset signal Reset.As shown in figure 4, the drain electrode connection positive of the 12nd NMOS tube MN12 is defeated
Enter signal vn, source ground, grid and meet reset signal Reset.The drain electrode of the 13rd NMOS tube MN13 connects the anti-phase input
Signal vp, source ground, grid meet reset signal Reset.
In the embodiment of the present invention, the control voltage Vcontr is input into by the grid of the first NMOS tube M1, by photovoltaic conversion
Into current-mode, in order to improve the linearity of voltage controlled oscillator, first resistor R1 is added in the source electrode of the first NMOS tube M1, this
Sample constitute source negative feedback structure, with the increase of the control voltage Vcontr, the first NMOS tube M1 electric currents also increase,
The same pressure drop on first resistor R1 can also increase.That is, input voltage is of the control voltage Vcontr
The driving voltage not as the first NMOS tube M1 on present first resistor R1 is separated, therefore causes the electricity of the first NMOS tube M1
Stream is smoothened.First PMOS MP1, the second PMOS MP2, the 3rd PMOS MP3 and the 4th PMOS composition cascade
Current-mirror structure, the grid end of the 3rd PMOS MP3 and the 4th PMOS is connected to the drain terminal of the first NMOS tube M1, in addition to second
PMOS MP2, the 3rd PMOS MP3 are provided and biased all the way, so on the one hand improve the PSRR ability of circuit, another
Aspect allows that the excursion of control voltage Vctrl is wider, further such that the adjustable change frequency of VCO is bigger.Such as
Shown in Fig. 5, be the embodiment of the present invention output clock signal frequency with control voltage variation relation figure；Can intuitively find out
It possesses the preferable linearity, and when voltage range changes 0.8V~3V, frequency can be changed by 80MHz to 700MHz, closed
In the frequency range of the heart i.e.：During 1.5-2.5V, the yield value of voltage controlled oscillator is about 270MHz/V.The embodiment of the present invention is voltage-controlled
Oscillator can provide the clock signal that frequency is 480MHz for the USB2.0 interface circuits.
Due to the requirement to subsequent conditioning circuit, clock data recovery circuit is sampled using six phase overfrequencies, so this implementation
Example uses three-level fully differential delay unit structure.Because the 3rd PMOS MP3 and the 4th PMOS MP4 consume certain electricity
Pressure, so every grade of amplitude of oscillation of fully differential phase inverter delay unit 1 has obtained certain limitation so that speed is obtained with noise suppressed
Preferably compromise；8th NMOS tube MN8 described in fully differential phase inverter delay unit 1, the 9th NMOS tube MN9 and described
Nine PMOS MP9 are bypass transfiguration, can suppress the noise of power supply and ground.7th PMOS MP7 and the 8th PMOS MP8 is using just
Feedback arrangement, can accelerate the upset of output end, improve reversal rate.Every grade of output end is all connected with a phase inverter so that defeated
It is the full amplitude of oscillation to go out.As shown in fig. 6, being that embodiment of the present invention circuit power consumption also exports simulation result；It can be seen that output voltage swing is
The full amplitude of oscillation, dutycycle is close to 50%.And the average current of integrated circuit only has 0.33mA, that is to say, that the power consumption of whole circuit is only
Have less than 1mW.
As shown in fig. 7, being embodiment of the present invention current phase noise simulation result, it can be seen that the phase at 1MHz is made an uproar
Sound about -99dB, the phase noise at 10MHz reaches 119.6dB, so embodiment of the present invention VCO possesses good phase
Noise inhibiting ability.
The present invention has been described in detail above by specific embodiment, but these are not constituted to limit of the invention
System.Without departing from the principles of the present invention, those skilled in the art can also make many deformations and improvement, and these also should
It is considered as protection scope of the present invention.
Claims (6)
1. a kind of voltage controlled oscillator, it is characterised in that：Voltage controlled oscillator includes control voltage gain circuitry and annular oscillation circuit；
Control voltage gain circuitry includes：
First NMOS tube, the control voltage of the grid connection input of first NMOS tube, the source electrode of first NMOS tube leads to
Cross first resistor ground connection, the drain electrode connection common-source common-gate current mirror circuit of first NMOS tube；
The common-source common-gate current mirror circuit includes the first PMOS, the second PMOS, the 3rd PMOS and the 4th PMOS, institute
State the grid of drain electrode, the drain electrode of first PMOS, the 3rd PMOS and the 4th PMOS of the first NMOS tube
Link together, the grid of first PMOS and second PMOS all connects same bias voltage, a PMOS
The drain electrode connection of the source electrode of pipe and the 3rd PMOS, the drain electrode of the source electrode of second PMOS and the 4th PMOS
The source electrode of connection, the 3rd PMOS and the 4th PMOS all connects supply voltage, and the drain electrode of second PMOS is defeated
Go out control voltage and amplify signal；
The control voltage amplifies signal input to the control end of the annular oscillation circuit and for controlling the ring oscillation
The output frequency of circuit；
The annular oscillation circuit is joined end to end by three-level fully differential phase inverter delay unit and is formed；
The fully differential phase inverter delay units at different levels include normal phase input end, inverting input, positive output end, anti-phase output
End and control end, fully differential phase inverter described in the normal phase input end connection upper level of the fully differential phase inverter delay units at different levels
The positive output end of delay unit, the inverting input of the fully differential phase inverter delay units at different levels connects complete described in upper level
The reversed-phase output of differential inverter delay unit, the positive output end of the fully differential phase inverter delay units at different levels is connected to
The normal phase input end of fully differential phase inverter delay unit described in next stage, the fully differential phase inverter delay units at different levels it is anti-phase
Output end is connected to the inverting input of fully differential phase inverter delay unit described in next stage；
The control end of the fully differential phase inverter delay units at different levels all connects the control voltage and amplifies signal；
The fully differential phase inverter delay units at different levels all include respectively：
The first negative circuit being made up of the 4th NMOS tube and the 7th PMOS, the 4th NMOS tube and the 7th PMOS
Grid be connected together as inverting input, the drain electrode of the 4th NMOS tube and the 7th PMOS links together
As reversed-phase output；
The second negative circuit being made up of the 5th NMOS tube and the 8th PMOS, the 5th NMOS tube and the 8th PMOS
Grid be connected together as normal phase input end, the drain electrode of the 5th NMOS tube and the 8th PMOS links together
As positive output end；
The source electrode of the 7th PMOS and the 8th PMOS all connects the control voltage and amplifies signal, the 4th NMOS
The source electrode of pipe and the 5th NMOS tube is all grounded；
The source ground of the 6th NMOS tube and the 7th NMOS tube, the 6th NMOS tube and the 7th NMOS tube, the described 6th
The drain electrode of NMOS tube, the grid of the 7th NMOS tube are all connected with the reversed-phase output, the drain electrode of the 7th NMOS tube,
The grid of the 6th NMOS tube is all connected with the positive output end.
2. voltage controlled oscillator as claimed in claim 1, it is characterised in that：The bias voltage is provided by the first biasing circuit,
First biasing circuit includes：Second NMOS tube, the 3rd NMOS tube, the 5th PMOS and the 6th PMOS, described second
The source ground of NMOS tube, the source electrode of the 3rd NMOS tube connects the drain and gate of second NMOS tube, the described 5th
The grid of PMOS and the grid and drain electrode of drain electrode and the 7th PMOS link together and as the bias voltage
Output end, the source electrode of the 5th PMOS connects the drain and gate of the 6th PMOS, the 6th PMOS
Source electrode connects supply voltage.
3. voltage controlled oscillator as claimed in claim 1, it is characterised in that：The annular oscillation circuit is also anti-phase including six
Device, the positive output end and reversed-phase output of the fully differential phase inverter delay units at different levels export one by a phase inverter respectively
Clock signal.
4. voltage controlled oscillator as claimed in claim 1, it is characterised in that：The fully differential phase inverter delay units at different levels also divide
Do not include：
8th NMOS tube, the source electrode of the 8th NMOS tube connects the source electrode of the 4th NMOS tube, the 8th NMOS tube
Grid, drain electrode and source electrode link together；
9th NMOS tube, the source electrode of the 9th NMOS tube connects the source electrode of the 5th NMOS tube, the 9th NMOS tube
Grid, drain electrode and source electrode link together；
9th PMOS, the source electrode of the 9th PMOS connects the source electrode of the 7th PMOS and the 8th PMOS,
The grid of the 9th PMOS, drain electrode and source electrode link together.
5. voltage controlled oscillator as claimed in claim 1, it is characterised in that：The clock signal of the output of the voltage controlled oscillator is defeated
Enter in USB2.0 interface circuits and for the USB2.0 interface circuits provide clock signal.
6. voltage controlled oscillator as claimed in claim 5, it is characterised in that：The voltage controlled oscillator is USB2.0 interfaces electricity
The frequency that road provides clock signal is 480MHz.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310233941.5A CN104242923B (en) | 2013-06-13 | 2013-06-13 | Voltage controlled oscillator |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310233941.5A CN104242923B (en) | 2013-06-13 | 2013-06-13 | Voltage controlled oscillator |
Publications (2)
| Publication Number | Publication Date |
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| CN104242923A CN104242923A (en) | 2014-12-24 |
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| CN105743494A (en) * | 2016-01-27 | 2016-07-06 | 苏州翠南电子科技有限公司 | Filtering voltage-controlled oscillator |
| CN108712158B (en) * | 2018-08-28 | 2023-08-11 | 广西师范大学 | Annular voltage-controlled oscillator circuit and oscillator |
| CN109560813B (en) * | 2018-11-28 | 2023-01-24 | 中国人民解放军国防科技大学 | Cross-coupling voltage-controlled oscillator with anti-irradiation function |
| CN110954229B (en) * | 2019-12-13 | 2022-04-05 | 海光信息技术股份有限公司 | Temperature detection circuit, temperature detection equipment, chip and circuit structure |
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| CN101884020A (en) * | 2007-12-12 | 2010-11-10 | 桑迪士克公司 | Current mirror device and method |
| CN201854256U (en) * | 2010-11-17 | 2011-06-01 | 无锡中星微电子有限公司 | Oscillator |
| CN102386848A (en) * | 2011-09-21 | 2012-03-21 | 电子科技大学 | Annular voltage-controlled oscillator |
| CN102571045A (en) * | 2010-12-23 | 2012-07-11 | 无锡华润上华半导体有限公司 | Current comparator |
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| US7994869B2 (en) * | 2009-04-27 | 2011-08-09 | Atmel Corporation | Current-controlled hysteretic oscillator |
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| CN101884020A (en) * | 2007-12-12 | 2010-11-10 | 桑迪士克公司 | Current mirror device and method |
| CN201854256U (en) * | 2010-11-17 | 2011-06-01 | 无锡中星微电子有限公司 | Oscillator |
| CN102571045A (en) * | 2010-12-23 | 2012-07-11 | 无锡华润上华半导体有限公司 | Current comparator |
| CN102386848A (en) * | 2011-09-21 | 2012-03-21 | 电子科技大学 | Annular voltage-controlled oscillator |
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