CN112398476B

CN112398476B - Low-power consumption comparator with low delay distortion characteristic

Info

Publication number: CN112398476B
Application number: CN201910742259.6A
Authority: CN
Inventors: 徐江涛; 史晓琳; 聂凯明; 高静
Original assignee: Tianjin University Marine Technology Research Institute
Current assignee: Tianjin University Marine Technology Research Institute
Priority date: 2019-08-13
Filing date: 2019-08-13
Publication date: 2023-04-07
Anticipated expiration: 2039-08-13
Also published as: CN112398476A

Abstract

A low-power consumption comparator with low delay distortion characteristics adopts a fully differential structure, has a common mode node and a virtual ground and is beneficial to reducing the delay distortion of the comparator. The bias stage of the comparator adopts a current mirror structure, so that the current passing through the input stage can be effectively limited, and the power consumption of the comparator is limited. The comparator consists of 10 MOSFET transistors M1-M10, wherein M1, M3, M5, M7 and M8 are P-type MOSFETs, and M2, M4, M6, M9 and M10 are N-type MOSFETs. The comparator effectively realizes high conversion precision. The accuracy of the doublet generated by the ADC, namely, the data used for recording the digital signals and the timestamp used for generating the digital signals, is ensured, and the use occasions of the ADC are further expanded.

Description

Low-power consumption comparator with low delay distortion characteristic

Technical Field

The invention belongs to the field of analog integrated circuits, and particularly relates to a low-power-consumption comparator with low delay distortion characteristics.

Background

The comparator includes an input stage having differential inputs and outputs, wherein the voltage at the output is responsive to the voltage at the input. The comparator further comprises a current limiter for limiting the current through the input stage, wherein the current through the input stage is responsive to the voltage at the input terminal.

An Analog-to-digital converter (ADC) converts an input Analog signal, such as an input voltage or an input current, into a digital signal or a digital code. In an asynchronous ADC, the input signal is not simply sampled, but is continually compared to a reference voltage, which is typically a fixed or continuously varying value. For example, the fixed reference is a direct current voltage or current; the continuous reference voltage is a ramp function. Due to the nature of the continuous mode, the comparator that performs the comparison must operate in the continuous mode, which is a non-clocked mode.

The ADC generates data for recording the digital signal and a time stamp when the digital signal is generated. Data containing these two pieces of information is called a doublet. The two tuples produced by the asynchronous conversion must be accurate or the time stamps and digital signals produced by the ADC will not reflect the analog input signals from which they were produced. Since the comparators in the ADC have a certain delay and the delay depends on the rate of change of the input signal and the voltage difference at the comparator input, i.e. overdrive. To maintain the accuracy of the doublet, the variation of the time stamp must be minimized and must be within a predetermined range of the wideband input signal.

Fig. 1 is a schematic diagram of a conventional low power comparator. The operating voltage of the comparator is GND to VDD. The differential inputs Vinp and Vinn are respectively a positive input end and a negative input end of the comparator, and the differential outputs Voutp and Voutn are respectively a positive output end and a negative output end of the comparator. When the positive input voltage is greater than the negative input voltage, the voltage of output Voutp is greater than the voltage of output Voutn. The comparator flips, i.e., the voltage at output Voutp may be close to the VDD voltage, and the voltage at output Voutn may be close to the GND voltage.

As shown in FIG. 1, the sources of transistors M1 and M3 are both connected to VDD, and the sources of transistors M2 and M4 are both connected to GND. This conventional low power comparator architecture has several disadvantages: the comparator does not implement a full differential because it does not have any common nodes and virtual ground. Also, the leakage current through the comparator is a strong function of the difference between VDD and GND and the magnitude of the voltage transitions at the inputs Vinp and Vinn. In addition, the comparator is sensitive to common mode voltage variations between the voltages at the inputs. Because of these drawbacks, the delay distortion of the comparator is high, making it unsuitable for some asynchronous ADCs. Therefore, the patent proposes a low power consumption comparator with low delay distortion characteristic, thereby effectively realizing high conversion precision.

Disclosure of Invention

Aiming at the problems in the prior art, the invention provides a low-power-consumption comparator with low delay distortion characteristics, which has a common-mode node and a virtual ground, and is beneficial to reducing the delay distortion of the comparator, so that the duplet generated by an ADC (analog to digital converter), namely the precision of data used for recording digital signals and a timestamp used for generating the digital signals, is ensured, and the use occasion of the ADC is further enlarged.

A low power consumption comparator with low delay distortion characteristic is shown in FIG. 2, and comprises 10 MOSFET transistors M1-M10, wherein M1, M3, M5, M7, M8 are P type MOSFETs, M2, M4, M6, M9, M10 are N type MOSFETs. The specific connection relationship is as follows: the source electrode of M5 and the source electrode of M9 are both connected with a power supply VDD, the grid electrode of M5 is connected with the grid electrode of M7, and the drain electrode of M5 is connected with the source electrodes of M1 and M3; the drain electrode of the M3 is connected with the drain electrode of the M4 and serves as a positive output end Voutp of the comparator, and the grid electrode of the M3 is connected with the grid electrode of the M4 and serves as a negative input end Vinn of the comparator; the source electrode of M4 and the source electrode of M2 are both connected with the drain electrode of M6; the drain electrode of the M1 is connected with the drain electrode of the M2 and is used as a negative output end Voutn of the comparator, and the grid electrode of the M1 is connected with the grid electrode of the M2 and is used as a positive input end Vinp of the comparator; the source electrode of M6 and the source electrode of M10 are connected with GND, and the grid electrodes of M6, M10, M7 and M5 are connected; the drain electrode of the M7 is connected with the drain electrode of the M8 and is connected with the grid electrodes of the M6, the M10, the M9 and the M5; the gates of M9 and M8 are connected and to the common-mode voltage VCM of the comparator.

A low-power consumption comparator with low delay distortion characteristic specifically works according to the following principle: the transistors M1 to M4 are input stages of the comparator, the transistors M5 and M6 are current limiters of the input stages of the comparator, and the transistors M7 to M10 are bias stages of the comparator. The gates of transistors M5 and M6 are connected to M7 and M10 in the bias stage so that the current through M5, M6 is a function of the common mode voltage VCM, which is the arithmetic average of the positive and negative inputs of the comparator. In the bias stage, the common-mode voltage VCM is input to the gates of the transistors M8, M9 having different channels, and thus the bias current through M8, M9 is determined by the common-mode voltage VCM. The drains of transistors M8, M9 are connected to the gates of transistors M5, M6, M7 and M10, thereby forming a current mirror structure that effectively limits the current through the input stage and allows nodes n1 and n2 to provide a virtual ground for the comparator. The configuration of transistors M7-M10 also ensures that the differential output voltage Voutp/Voutn is equal to the common-mode voltage VCM. When voltages Vinp and Vinn are equal to common-mode voltage VCM, the output voltage is equal to common-mode voltage VCM. When the input voltages Vinp and Vinn are not equal to the common-mode voltage VCM, the output voltage fluctuates centered on the common-mode voltage VCM.

The invention provides a low-power-consumption comparator with low delay distortion characteristic, thereby effectively realizing high conversion precision. The accuracy of the doublet generated by the ADC, namely, the data used for recording the digital signals and the timestamp used for generating the digital signals, is ensured, and the use occasions of the ADC are further expanded.

Drawings

FIG. 1 is a schematic diagram of a conventional low power comparator circuit;

fig. 2 is a low power consumption comparator with low delay distortion characteristic according to the present invention.

Description of the preferred embodiment

In order to make the objects, technical solutions and advantages of the present invention more apparent, a detailed description of the embodiments of the present invention will be given below with reference to examples.

In this example, M1, M3, M5, M7, M8 are PMOS transistors, and M2, M4, M6, M9, M10 are NMOS transistors. The specific relationship of the width-length ratio of each transistor in the comparator is as follows:

M5/M7= M6/M10=2 × M1/M8=2 × M3/M8=2 × M2/M9=2 × M4/M9. The gate length of each MOS tube is 180nm; the grid widths of M5, M7 and M8 are 1um; the gate widths of M1 and M3 are 500nm; the gate widths of M6, M9 and M10 are 700nm; the gate width of M2 and M4 is 350nm. The common-mode voltage VCM is equal to the arithmetic mean of Vinp and Vinn. The current flowing through the branch formed by transistors M1 and M2 is half that flowing through transistors M5 and M6, and the other half flows through the branch formed by transistors M3 and M4. This current may set the bias condition of the comparator to maximum when the input is at the crossover point. When Vinp is greater than Vinn, transistor M2 is gradually turned on more than transistor M1, thereby causing the output voltage Voutn to decrease. Similarly, transistor M3 is gradually turned on more than transistor M4, thereby making the output voltage Voutp higher. In this operation, nodes n1 and n2 act as virtual ground nodes, thereby reducing the total current through the comparator. The total average current of the comparator is 1uA, and the average power is 3.3 uW.

Claims

1. A low power consumption comparator having a low delay distortion characteristic, comprising: the MOSFET is composed of 10 MOSFET transistors M1-M10, wherein M1, M3, M5, M7 and M8 are P-type MOSFETs, and M2, M4, M6, M9 and M10 are N-type MOSFETs; the source electrode of M5 and the source electrode of M7 are both connected with a power supply VDD, the grid electrode of M5 is connected with the grid electrode of M7, and the drain electrode of M5 is connected with the source electrodes of M1 and M3; the drain electrode of the M3 is connected with the drain electrode of the M4 and is used as a positive output end Voutp of the comparator, and the grid electrode of the M3 is connected with the grid electrode of the M4 and is used as a negative input end Vinn of the comparator; the source electrode of M4 and the source electrode of M2 are both connected with the drain electrode of M6; the drain electrode of the M1 is connected with the drain electrode of the M2 and is used as a negative output end Voutn of the comparator, and the grid electrode of the M1 is connected with the grid electrode of the M2 and is used as a positive input end Vinp of the comparator; the source electrode of M6 and the source electrode of M10 are connected with GND, and the grid electrodes of M6, M10, M7 and M5 are connected; the drain electrode of the M9 is connected with the drain electrode of the M8 and is connected with the grid electrodes of the M6, the M10, the M7 and the M5; the gates of M9 and M8 are connected and to the common mode voltage VCM of the comparator.