CN109884873B - Time-to-digital converter adopting dynamic threshold technology - Google Patents

Time-to-digital converter adopting dynamic threshold technology Download PDF

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CN109884873B
CN109884873B CN201810366965.0A CN201810366965A CN109884873B CN 109884873 B CN109884873 B CN 109884873B CN 201810366965 A CN201810366965 A CN 201810366965A CN 109884873 B CN109884873 B CN 109884873B
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transistor
nmos transistor
pmos
input
dynamic threshold
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CN109884873A (en
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张聪
王子轩
夏晓娟
吉新村
胡善文
蔡志匡
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Nanjing University Of Posts And Telecommunications Nantong Institute Co ltd
Nanjing University of Posts and Telecommunications
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Nanjing University Of Posts And Telecommunications Nantong Institute Co ltd
Nanjing University of Posts and Telecommunications
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Abstract

The invention relates to a time-to-digital converter adopting a dynamic threshold technology, which is suitable for a near-threshold power supply voltage environment and comprises a vernier delay line TDC circuit and an encoder circuit, wherein the vernier delay line TDC circuit judges the time difference between START and STOP signals and outputs a corresponding result in a binary form. Because a lower power supply voltage is adopted, the overdrive voltage of the transistor is insufficient, and the working current of the circuit can be reduced, so that the working time of the vernier delay line TDC is greatly prolonged. The invention adopts a dynamic threshold technology to connect the substrate of the transistor with the grid end, so that the potential of the substrate can change along with the change of the grid voltage, the threshold voltage of the transistor can be greatly reduced, the source-drain current can also be increased, the generation of leakage current can also be avoided to the greatest extent, and the speed and the reliability of the circuit are improved.

Description

Time-to-digital converter adopting dynamic threshold technology
Technical Field
The invention relates to a time-to-digital converter, in particular to a time-to-digital converter adopting a dynamic threshold technology, and belongs to the technical field of numerical control.
Background
The TDC is widely used in an integrated circuit, mainly as a phase discriminator of an all-digital phase-locked loop, and the output digital signal of the TDC directly reflects the time difference between the rising edges of two input clock signals and directly drives a digitally controlled oscillator to change the frequency of the oscillator. In addition, the TDC can be widely applied to the fields of high-energy physics, laser ranging, medical imaging and the like. With the rapid development of modern communication technology, modern communication means such as WI-FI, bluetooth, GPS and the like have been integrated into the daily life of people, and the development of modern communication technology has also promoted the popularization and application of portable devices. The power supply of the portable modern communication device is mainly powered by a battery, and how to reduce power consumption to prolong the endurance time of the battery has become a hot issue of research in the industry.
As a main energy consumption module of a modern wireless communication system, the implementation of a low-power-consumption all-digital phase-locked loop is a key to realize low power consumption of the whole wireless system. The time-to-digital converter is one of the main energy consumption modules of the all-digital phase-locked loop, so that the realization of the time-to-digital converter with low power consumption has important significance.
The power consumption of the system can be directly and effectively reduced by reducing the power supply voltage, so how to implement the function of the time-to-digital converter under the condition of the near-threshold power supply voltage has become a new research hotspot. When the power supply voltage is greatly reduced, the power consumption of the system is also greatly reduced, but the threshold voltage of the transistor is not changed, so that the overdrive voltage of the MOS transistor is insufficient, the current of the gate of the transistor and the charging and discharging speed of the circuit are reduced, the time of the rising edge and the falling edge of the signal is prolonged, and the working speed of the circuit is reduced. At present, time-to-digital converters capable of working normally at low voltage have structures such as vernier delay lines, random time-to-digital converters and the like. Although the conventional vernier delay line time-to-digital converter can normally operate at a low voltage, the delay of the delay buffer is greatly increased relative to the normal power supply voltage, the number of stages of the delay chain is increased to obtain a high resolution, and the operating speed of the circuit is greatly reduced.
Another possible configuration at low voltages is a random time-to-digital converter, which is very simple and consists of only a certain number of identical comparators. This configuration can achieve high resolution, but requires a large number of comparators, and the power consumption thereof increases as the number of comparators increases. In addition, the small measurement range of this structure is another disadvantage thereof.
Disclosure of Invention
The invention aims to: aiming at the defects in the prior art, the time-to-digital converter adopting the dynamic threshold technology is provided, the time difference of the rising edges of two input clock signals can be identified, the binary digital form output can be converted, and under the condition of a power supply voltage close to the threshold value, the dynamic threshold technology is adopted, so that the higher working speed and the lower power consumption can be obtained.
In order to achieve the purpose, the technical scheme of the invention is as follows: a time-to-digital converter adopting dynamic threshold technology comprises a vernier delay line TDC circuit and an encoder circuit, wherein the vernier delay line TDC circuit and the encoder circuit are used for judging the time difference between START and STOP and outputting corresponding results in a binary form; the vernier delay line TDC circuit is composed of three parts, namely a delay line 1 circuit, a delay line 2 circuit and a comparator circuit, wherein the delay line 1 circuit is composed of 32 delay buffers with the delay time of delta t1 and adopting the dynamic threshold technology, the delay line 2 circuit is composed of 32 delay buffers with the delay time of delta t2 and adopting the dynamic threshold technology, and the comparator circuit is composed of 32 differential comparators based on SR latches and adopting the dynamic threshold technology.
The invention is suitable for the environment of near-threshold power supply voltage, and because of adopting lower power supply voltage, the overdrive voltage of the transistor is insufficient, the working current of the circuit can be greatly reduced, so the working time of the TDC circuit of the vernier delay line can be greatly prolonged. The invention adopts a dynamic threshold technology to connect the substrate of the transistor with the grid end, so that the potential of the substrate changes along with the change of the grid voltage, the overdrive voltage of the transistor can be greatly increased, the threshold voltage of the transistor can be greatly reduced, the source-drain current can be increased, the generation of leakage current can be avoided to the greatest extent, and the speed and the reliability of the circuit are improved. .
The further limited technical scheme of the invention is as follows: the delay buffer adopting the dynamic threshold technology comprises a first PMOS (P-channel metal oxide semiconductor) tube MP1A second PMOS transistor MP2First NMOS transistor MN1A second NMOS transistor MN2；
Input signal in and first PMOS tube MP1And a firstNMOS tube MN1The grid electrodes are connected; first PMOS transistor MP1And a first NMOS transistor MN1Drain electrode of and the second PMOS transistor MP1And a second NMOS transistor MN1Is connected with the grid electrode of the second PMOS tube MP1And a second NMOS transistor MN1Is connected to the output signal out;
first PMOS transistor MP1Substrate of (1) and first PMOS transistor MP1Is connected with the grid electrode of the first PMOS tube MP1The drain electrode of the transistor is connected with a power supply Vdd; second PMOS transistor MP1Substrate and second PMOS transistor MP1Is connected with the grid electrode of the first PMOS tube MP1Is connected to the power supply Vdd.
Furthermore, the comparator adopting the dynamic threshold technology comprises a third PMOS tube MP3And the fourth PMOS transistor MP4The fifth PMOS transistor MP5Third NMOS transistor MN3And the fourth NMOS tube MN4The fifth NMOS transistor MN5And a sixth NMOS transistor MN6And a seventh NMOS transistor MN7；
All transistors applied in the comparator adopting the dynamic threshold technology adopt the dynamic threshold technology, and the substrate of each transistor is connected with the grid electrode of the transistor.
Wherein, the input signal a is connected to the gate of the fifth PMOS transistor MP5 and the input terminals of the two-input OR gate OR 1; the input signal b is connected to the gate of the sixth NMOS transistor MN6 and the input ends of the two input OR gates OR 2; the output ends of the two input OR gates OR1 are connected to the gates of the third PMOS transistor MP3, the fourth PMOS transistor MP4 and the fifth PMOS transistor MP 5;
the sources of the third PMOS transistor MP3 and the fourth PMOS transistor MP4 are connected to the power supply Vdd, the substrate of the fifth NMOS transistor MN5 is connected to the power supply Vdd, and the gate of the seventh NMOS transistor MN7 is connected to the power supply Vdd; the sources of the fifth NMOS transistor MN5 and the sixth NMOS transistor MN6 are connected to gnd, and the substrate of the seventh NMOS transistor MN7 is connected to gnd;
the drain of the third PMOS transistor MP3 is connected to the drain of the third NMOS transistor MN3, and the source of the third NMOS transistor MN3 is connected to the drain of the fifth NMOS transistor MN 5; the drain of the fourth PMOS transistor MP4 is connected to the drain of the fourth NMOS transistor MN4, and the source of the fourth NMOS transistor MN4 is connected to the drain of the sixth NMOS transistor MN 6; the source electrode of the fifth PMOS transistor MP5 is connected to the drain electrode of the third PMOS transistor MP3, and the drain electrode of the fifth PMOS transistor MP5 is connected to the drain electrode of the fourth PMOS transistor MP 4; the drain electrode of the seventh NMOS transistor MN7 is connected with the drain electrode of the fifth NMOS transistor MN5, and the source electrode of the seventh NMOS transistor MN7 is connected with the drain electrode of the sixth NMOS transistor MN 6;
the gate of the third NMOS transistor MN3 is connected to the drain of the fourth PMOS transistor MP4 and the input terminal S1 of the two-input NAND gate NAND1, and the gate of the fourth NMOS transistor MN4 is connected to the drain of the third PMOS transistor MP3 and the input terminal R1 of the two-input NAND gate NAND 2;
the input terminal S2 of the two-input NAND gate NAND1 is connected to the output terminal of the two-input NAND gate NAND2, the input terminal R2 of the two-input NAND gate NAND2 is connected to the output terminal of the two-input NAND gate NAND1, and the output of the two-input NAND gate NAND1 is the result of the comparator.
Furthermore, two input signals START and STOP are connected to the input end of the vernier delay line TDC, and after each signal passes through the first-stage delay buffer, two clock signals are sent to the differential comparator to identify the speed of the rising edge. When the START signal leads the STOP signal, the output result of the comparator is high level; when the START signal lags the STOP signal, the comparator output is low. The discrimination result is sent to the encoder for processing, and the encoder finds the position where the signal jumps from 1 to 0 by processing the discrimination result and outputs the corresponding result in binary form.
Compared with the prior art, the invention adopting the technical scheme has the following technical effects:
the invention adopts the dynamic threshold technology to connect the substrate of the transistor with the grid of the transistor, so that the potential of the substrate is not fixed but can change along with the change of the grid voltage, the overdrive voltage of the transistor can be greatly increased, the source-drain current can be increased, the generation of leakage current can be avoided to the greatest extent, and the speed and the reliability of the circuit are improved. Taking a PMOS tube as an example below, the technical effect of adopting the dynamic threshold technology is explained, when the grid electrode and the substrate of the transistor are both connected with low level, the transistor is conducted, the threshold voltage is reduced, and the source-drain current and the overdrive voltage are both increased; when the grid and the substrate of the transistor are both connected to high level, the transistor is cut off, and no leakage current is generated because the drain voltage and the source voltage are both smaller than the substrate voltage. Therefore, the delay time of the delay buffer adopting the dynamic threshold technology is greatly reduced, the comparator adopting the dynamic threshold technology can still achieve the discrimination precision of 1ps, and the overall performance of the circuit is improved.
Drawings
The invention will be further described with reference to the accompanying drawings.
Fig. 1 is a diagram showing a basic circuit configuration of the present invention.
Fig. 2 is a main circuit block diagram of the vernier delay line TDC circuit in the present invention.
Fig. 3 is a schematic circuit diagram of the delay buffer of the present invention.
Fig. 4 is a schematic circuit diagram of the comparator in the present invention.
FIG. 5 is a simulation comparison graph of leakage current and source-drain current of a transistor and a common transistor using dynamic threshold technique according to the present invention.
FIG. 6 is a comparison graph of transient simulation of a delay buffer using dynamic threshold technique according to the present invention and a conventional delay buffer.
Fig. 7 is a transient simulation diagram of the comparator of the present invention.
Detailed Description
The embodiment provides a time-to-digital converter adopting a dynamic threshold technology, which has a structure as shown in fig. 1 and comprises a vernier delay line TDC circuit and an encoder circuit, wherein the vernier delay line TDC circuit discriminates the time difference between START and STOP signals, the decision result is sent to an encoder, and the encoder outputs a corresponding result in a binary form.
The vernier delay line TDC comprises three parts of a delay line 1 circuit, a delay line 2 circuit and a comparator circuit, wherein:
delay line 1 is composed of 32 stages of delay buffers with delay time Δ t1, delay line 2 is composed of 32 stages of delay buffers with delay time Δ t2, and Δ t1 is greater than Δ t 2;
the clock signals START and STOP are respectively connected with the input ends of the first-stage delay buffers of the delay line 1 and the delay line 2, the results of the clock signals are sent to the comparator for comparison after the clock signals are delayed by the first-stage delay buffers each time, when the output result of the comparator of the START signal leading the STOP signal is 1, and when the output result of the comparator of the START signal lagging the STOP signal is 0, the encoder finds the position where the signal jumps from 1 to 0 by processing the judgment result of the comparator and outputs the corresponding result in a binary form.
As shown in FIG. 3, the delay buffer using dynamic threshold technique includes two PMOS transistors MP1、MP2Two NMOS transistors MN1、MN2Wherein:
input signal in is connected to MP1And MN1A gate electrode of (1); mP1And MN1Drain electrode of (2) is connected with MP1And MN1Of the grid electrode, MP1And MN1The drain of (1) is connected with out; mP1Substrate of (2) is connected with MP1Of the grid electrode, MP1Is connected to Vdd; mP1Substrate of (2) is connected with MP1Of the grid electrode, MP1The drain of which is connected to Vdd.
As shown in fig. 4, the comparator has a differential structure, and includes three PMOS transistors, five NMOS transistors, one or gate, and two nand gates, where:
all transistors used in this configuration employ dynamic threshold techniques, connecting the substrate of the transistor to the gate of the transistor.
Input signal a is connected to MP5And the input terminals of a two-input OR gate OR 1; input signal b is connected to MN6And the input terminals of a two-input OR gate OR 2; the output end of the two-input OR gate OR1 is connected to MP3、MP4And MP5A gate electrode of (1).
MP3And MP4Is connected to Vdd, MN5To Vdd, MN7The gate of which is connected to Vdd; mN5And MN6To gnd, MN7To gnd.
MP3Is connected to MN3Drain electrode of, MN3Is connected to MN5A drain electrode of (1); mP4Is connected to MN4Drain electrode of, MN4Is connected to MN6A drain electrode of (1); mP5Source and M ofP3Is connected to the drain electrode of MP5Drain electrode of (1) andP4the drain electrodes of the two electrodes are connected; mN7Drain electrode of (1) and (M)N5Is connected to the drain electrode of MN7Source and MN6Are connected.
MN3Is connected to MP4And an input terminal S1 of a two-input NAND gate NAND 1; mN4Is connected to MP3And an input terminal R1 of a two-input NAND gate NAND 2; the input terminal S2 of the two-input NAND gate NAND1 is connected to the output terminal of the two-input NAND gate NAND2, the input terminal R2 of the two-input NAND gate NAND2 is connected to the output terminal of the two-input NAND gate NAND1, and the output of the two-input NAND gate NAND1 is the result of the comparator.
FIG. 5 is a simulation comparison graph of leakage current and source-drain current of a conventional transistor using dynamic threshold technique, substrate forward bias technique, in accordance with the present invention. As can be seen from the figure, the transistor using the dynamic threshold technique has a larger source-drain current than the transistor using the substrate forward bias technique and the substrate normal bias. However, the transistor adopting the substrate forward bias technology has large leakage current, and the leakage current of the transistor adopting the dynamic threshold technology is almost the same as that of the transistor adopting the normal bias, is less than 100pA, and can be basically ignored in the design, so the dynamic threshold technology is suitable for low voltage.
FIG. 6 is a comparison graph of transient simulation of the delay buffer of the present invention using dynamic threshold technique and a conventional delay buffer. As can be seen from the figure, the delay time Δ t1 for each stage of delay of the clock signal is 261ps in the conventional delay buffer, while the delay time Δ t2 for each stage of delay of the clock signal is 187ps in the dynamic threshold technique. The delay is reduced by 74ps compared to a conventional delay buffer, so that the operation speed can be greatly improved by using the dynamic threshold technique.
Fig. 7 is a transient simulation diagram of the comparator of the present invention. As can be seen from the figure, when the clock signal a leads the clock signal b, the comparator outputs a high level; when the clock signal a lags behind the clock signal b, the comparator outputs a low level. This shows that the comparator can work normally under the power supply voltage close to the threshold value after the dynamic threshold value technology is adopted. It can also be seen from the figure that the discrimination precision of the comparator is 1ps, so that after the dynamic threshold value technology is adopted, the comparator still keeps high precision, and the reliability of the circuit is greatly improved.
In summary, the vernier delay line time-to-digital converter of the present invention adopts a dynamic threshold technique to connect the substrate of the transistor with the gate of the transistor under the condition of the near-threshold power supply voltage, so that the potential of the substrate changes with the change of the gate voltage, the overdrive voltage of the transistor is greatly increased, the source-drain current is also increased, the generation of leakage current can be avoided to the greatest extent, and the problems of the reduction of the operating speed and the reduction of the reliability of the circuit under the near-threshold power supply voltage are solved.
The above description is only a preferred embodiment of the present invention, and the scope of the present invention is not limited to the above embodiment, but equivalent modifications or changes made by those skilled in the art according to the present disclosure should be included in the scope of the present invention as set forth in the appended claims.

Claims (4)

1. A time-to-digital converter adopting a dynamic threshold technology is characterized by comprising a vernier delay line TDC circuit and an encoder circuit, wherein the vernier delay line TDC circuit and the encoder circuit are used for judging the time difference between START and STOP and outputting corresponding results in a binary form; the vernier delay line TDC circuit comprises three parts, namely a delay line 1 circuit, a delay line 2 circuit and a comparator circuit, wherein the delay line 1 circuit comprises 32 delay buffers with the delay time of delta t1 and adopting the dynamic threshold technology, the delay line 2 circuit comprises 32 delay buffers with the delay time of delta t2 and adopting the dynamic threshold technology, and the comparator circuit comprises 32 differential comparators based on SR latches and adopting the dynamic threshold technology;
the delay buffer adopting the dynamic threshold technology comprises a first PMOS (P-channel metal oxide semiconductor) tube MP1A second PMOS transistor MP2First NMOS transistor MN1A second NMOS transistor MN2；
Input signal in and first PMOS tube MP1And a first NMOS pipe MN1The grid electrodes are connected; first PMOS transistor MP1And a first NMOS transistor MN1Drain electrode of and the second PMOS transistor MP1And a second NMOS transistor MN1Is connected with the grid electrode of the second PMOS tube MP1And a second NMOS transistor MN1Is connected to the output signal out;
first PMOS transistor MP1Substrate of (1) and first PMOS transistor MP1Is connected with the grid electrode of the first PMOS tube MP1The drain electrode of the transistor is connected with a power supply Vdd; second PMOS transistor MP1Substrate and second PMOS transistor MP1Is connected with the grid electrode of the first PMOS tube MP1Is connected with a power supply Vdd;
the comparator adopting the dynamic threshold technology comprises a third PMOS tube MP3And the fourth PMOS transistor MP4The fifth PMOS transistor MP5Third NMOS transistor MN3And the fourth NMOS tube MN4The fifth NMOS transistor MN5And a sixth NMOS transistor MN6And a seventh NMOS transistor MN7；
All transistors applied in the comparator adopting the dynamic threshold technology adopt the dynamic threshold technology, and the substrate of each transistor is connected with the grid electrode of the transistor.
2. The time-to-digital converter using dynamic threshold technique according to claim 1, characterized in that: the input signal a is connected to the fifth NMOS transistor MN5And the input terminals of a two-input OR gate OR 1; the input signal b is connected to the sixth NMOS transistor MN6And the input terminals of a two-input OR gate OR 1; the output ends of the two input OR gates 1 are connected to the third PMOS transistor MP3And the fourth PMOS transistor MP4And a fifth PMOS transistor MP5A gate electrode of (1);
third PMOS transistor MP3And a fourth PMOS transistor MP4The source of the NMOS transistor is connected to a power supply Vdd, and the fifth NMOS transistor MN5The substrate of the NMOS transistor is connected to a power supply Vdd, and the seventh NMOS transistor MN7The gate of which is connected to a power supply Vdd; fifth NMOS transistor MN5And a sixth NMOS transistor MN6Is connected to gnd, and a seventh NMOS transistor MN7The substrate of which is connected to gnd;
third PMOS transistor MP3Is connected to the third NMOSPipe MN3Drain electrode of (1), third NMOS tube MN3Is connected to the fifth NMOS transistor MN5A drain electrode of (1); fourth PMOS transistor MP4Is connected to the fourth NMOS transistor MN4Drain electrode of (1), fourth NMOS tube MN4Is connected to the sixth NMOS transistor MN6A drain electrode of (1); fifth PMOS transistor MP5Source electrode of and third PMOS transistor MP3Is connected with the drain electrode of the fifth PMOS tube MP5Drain electrode of and fourth PMOS tube MP4The drain electrodes of the two electrodes are connected; seventh NMOS transistor MN7Drain electrode of and the fifth NMOS transistor MN5Is connected with the drain electrode of the seventh NMOS tube MN7Source electrode of (1) and sixth NMOS transistor MN6The drain electrodes of the two electrodes are connected;
third NMOS transistor MN3Is connected to the fourth PMOS transistor MP4And the input end S1 of a two-input NAND gate 1, and a fourth NMOS tube MN4Is connected to the third PMOS transistor MP3And an input terminal R1 of a two-input NAND gate NAND 2;
the input terminal S2 of the two-input NAND gate NAND1 is connected to the output terminal of the two-input NAND gate NAND2, the input terminal R2 of the two-input NAND gate NAND2 is connected to the output terminal of the two-input NAND gate NAND1, and the output of the two-input NAND gate NAND1 is the result of the comparator.
3. The time-to-digital converter using dynamic threshold technique according to claim 1, characterized in that: two input signals START and STOP are connected to the input end of the TDC circuit of the vernier delay line, and after each signal passes through a first-stage delay buffer, two clock signals are sent to a differential comparator to identify the speed of a rising edge;
when the START signal leads the STOP signal, the output result of the comparator is high level; when the START signal lags the STOP signal, the comparator output is low.
4. The time-to-digital converter using dynamic threshold technique according to claim 1, characterized in that: the discrimination result is sent to an encoder for processing, and the encoder finds a position where the signal jumps from 1 to 0 by processing the discrimination result and outputs the corresponding result in a binary form.
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CN111025884B (en) * 2019-12-08 2021-10-26 复旦大学 Two-step high-speed dynamic time-to-digital converter
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CN112506030B (en) * 2021-02-04 2021-07-13 南京邮电大学 Time-digital converter based on PVT detection circuit

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