CN103078644A - Time-to-digit converter - Google Patents
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- CN103078644A CN103078644A CN2012105911971A CN201210591197A CN103078644A CN 103078644 A CN103078644 A CN 103078644A CN 2012105911971 A CN2012105911971 A CN 2012105911971A CN 201210591197 A CN201210591197 A CN 201210591197A CN 103078644 A CN103078644 A CN 103078644A
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Abstract
The invention discloses a time-to-digit converter, which comprises a vernier delay line time-to-digit converter, an error selection circuit, an error integration circuit and an error compensation circuit, wherein a first input signal and a second input signal are input into the vernier delay line time-to-digit converter; the vernier delay line time-to-digit converter is used for comparing the time differences of the first input signal and the second input signal, quantifying the time difference into a digital code, and outputting to the error selection circuit and the error compensation circuit; the time difference is also input into the error selection circuit; after the time difference is amplified through the error selection circuit, a correct quantification error is selected and output to the error integration circuit; the error integration circuit is used for extracting the quantification error, integrating and inputting an integration value into the error compensation circuit; and the error compensation circuit is used for comparing the integration value with a reference voltage, and adding 1 to a digital code for outputting if the integration value is higher than the reference voltage. According to the time-to-digit converter, the loss of quantification error information is avoided, and the resolution of the time-to-digit converter is increased.
Description
Technical field
The present invention relates to a kind of time-to-digit converter (TDC:Time-Digital Converter), be specifically related to a kind of time meta-digital quantizer with error compensation function, can differentiate the time difference of two rising edge clock signals and express with digital coding to have the function of compensation quantization error and improve the characteristics of quantified precision.
Background technology
TDC has a wide range of applications in integrated circuit, be mainly used to differentiate for digital phase-locked loop provides phase place, in addition, at medical image, lasers range is surveyed, and many application scenarios such as half-life of detecting particle all rely on TDC and differentiate that the small time (phase place) is poor.TDC adopts digital technique to realize, along with process dwindles gradually, has portable good advantage.In addition, digital TDC circuit has better noise immunological characteristic, and power consumption is also lower.
In digital phase-locked loop, TDC is a kind of poor circuit of discriminating time (phase place) that replaces traditional phase discriminator.The time difference that the digital control word of TDC output has reflected two input signal rising edges, and driving oscillator adjusts frequency, therefore very high for the evaluation resolution requirement of TDC.Structure commonly used is delay line TDC, the buffer series connection very little by a string delay consists of delay line, allow one of them input signal transmit by delay line, every through comparing with another input signal after the one-level delay, the result who compares is each time delivered to encoder, encoder is found out in the comparative result by 0 and is jumped to 1 or jump to 0 position and the corresponding coding of output by 1, and this coding has just represented the time difference of two signal rising edges.The TDC of this delay-line structure has advantages of simple in structure, but its resolution is subject to the restriction of the time of delay of buffer, can produce larger quantization error, and worsens the in-band noise of all-digital phase-locked loop.Another kind of TDC based on delay line (VDL:Vernier Delay Line) structure is vernier delay line TDC.This structure has adopted two delay lines, and the buffer that forms every delay line has identical time of delay, but with time of delay of buffer on another delay line is arranged small time difference.Two input signals are respectively by a delay line transmission, every postpone through one-level after more once, and comparative result delivered to encoder, the output encoder of encoder represents the time difference of two signal rising edges.The resolution of vernier delay line TDC equals time of delay poor of two buffers on the delay line.The resolution of this structure is compared traditional delay line TDC and is increased, but still can produce certain quantization error, has reduced the quantified precision of TDC.
Summary of the invention
Goal of the invention: the problem and shortage for above-mentioned prior art exists the purpose of this invention is to provide a kind of time-to-digit converter with error compensation function.
Technical scheme: for achieving the above object, the technical solution used in the present invention is a kind of time-to-digit converter, comprises vernier delay line time-to-digit converter, error selection circuit, error intergal circuit and error compensation circuit; The first input signal and the second input signal are inputted described vernier delay line time-to-digit converter, described vernier delay line time-to-digit converter compares the time difference of the first input signal and the second input signal, and this time difference is quantified as digital coding exports error to and select circuit and error compensation circuit, the described time difference goes back error originated from input and selects circuit; Described error is chosen correct quantization error and is exported to the error intergal circuit after selecting circuit that the described time difference is amplified; Described error intergal circuit extracts described quantization error and integration, and with integrated value error originated from input compensating circuit; Described error compensation circuit compares integrated value and reference voltage, if integrated value greater than reference voltage, then makes digital coding add 1 output.
Further, described vernier delay line time-to-digit converter comprises two delay line, N identical decision device and encoders of being comprised of N level delay cell, described error selects circuit to comprise N identical time amplifier and MUX, described error intergal circuit comprises a phase discriminator, a charge pump and a capacitor, and described error compensation circuit comprises a voltage comparator and an adder; Wherein:
The first input signal connects the delay line that is comprised of delay cell D1-1～D1-N, the second input signal connects the delay line that is comprised of delay cell D2-1～D2-N, the input of the decision device that the output termination of every grade of delay cell is corresponding, the output of decision device connects the input of encoder, and the output of encoder connects the input control end of MUX;
The input of the time amplifier that the output termination of every grade of delay cell is corresponding, the output of every grade of time amplifier connects the input of MUX;
The output of MUX connects the input of phase discriminator, and the output of phase discriminator connects the input of charge pump, and the output of charge pump connects the top crown of capacitor, the bottom crown ground connection of capacitor;
Electric charge delivery side of pump and reference voltage connect the input of voltage comparator;
The output of voltage comparator and the output of encoder connect the input of adder, and the output of adder is as the output of whole time-digital converter circuit.
Further, described vernier delay line time-to-digit converter compares the time difference of the first input signal and the second input signal rising edge.
Beneficial effect: compared with prior art, the present invention has following beneficial effect:
Introduce the thought of error compensation on the basis of traditional VDL TDC, select circuit by adding error, error intergal circuit and error compensation circuit, the error that produces in the quantizing process extracted and carry out integration, when error accumulation is arrived greater than reference voltage Vref, the digital coding of finally exporting is added 1.The TDC of this structure has avoided losing of control information in the quantizing process, has the function of compensation quantization error and improves the characteristics of TDC resolution.
Description of drawings
Fig. 1 is overall circuit block diagram of the present invention;
Fig. 2 is overall circuit figure of the present invention;
Fig. 3 (a) is the circuit structure diagram of delay cell, and Fig. 3 (b) is the circuit structure diagram of decision device, and Fig. 3 (c) is the circuit structure diagram of time amplifier; Fig. 3 (d) is the circuit structure diagram of voltage comparator;
Fig. 4 is sequential analogous diagram of the present invention.
Embodiment
Below in conjunction with the drawings and specific embodiments, further illustrate the present invention, should understand these embodiment only is used for explanation the present invention and is not used in and limits the scope of the invention, after having read the present invention, those skilled in the art all fall within the application's claims limited range to the modification of the various equivalent form of values of the present invention.
As depicted in figs. 1 and 2, TDC circuit of the present invention comprises two delay lines that are comprised of N level delay cell, N identical decision device, an encoder, N identical time amplifier, a MUX, a phase discriminator, a charge pump, a voltage comparator, a capacitor and an adder; Wherein: the first input signal START connects the delay line that is comprised of delay cell D1-1 ~ D1-N, the second input signal STOP connects the delay line that is comprised of delay cell D2-1 ~ D2-N, the output of D1-1 and D2-1 connects the input of decision device 1, the output of D1-2 and D2-2 connects the input of decision device 2, the like, the input of the decision device that the output termination of every grade of delay cell is corresponding, the output of decision device connects the input of encoder.The output of D1-1 and D2-1 connects the input of time amplifier 1, the output of D1-2 and D2-2 connects the input of time amplifier 2, the like, the input of the time amplifier that the output termination of every grade of delay cell is corresponding, the output of every grade of time amplifier connects the input of MUX.The output of MUX connects the input of phase discriminator, and the output of phase discriminator connects the input of charge pump, and the output of charge pump connects the top crown of capacitor, the bottom crown ground connection of capacitor.Electric charge delivery side of pump and reference voltage Vref connect the input of voltage comparator.The output of voltage comparator and the output of encoder connect the input of adder, the output of the output of adder meta-quantizer circuit when whole.
VDL TDC compares the time difference of the rising edge of two input signal START and STOP, and it is quantified as digital coding, exports by encoder.Signal after every one-level postpones is all received the input of time amplifier, will amplify rear input signal as MUX the time difference.The input control end of MUX is received in encoder output, makes the quantization error after MUX is chosen correct process amplification, and exports to phase discriminator.Quantization error after phase discriminator and charge pump will amplify is converted into corresponding electric current, and by discharging and recharging of electric capacity become voltage signal.When this voltage signal during greater than the reference voltage Vref value, voltage comparator output high level, final digital coding value also adds 1 thereupon, has realized the function of compensation quantization error.
Fig. 3 is each submodular circuits figure of TDC of the present invention.Fig. 3 (a) connects power supply for the source electrode of the circuit structure of delay cell: PMOS pipe PM1 and PM2, the source ground of NMOS pipe NM1 and NM2.Input signal connects the grid of PM1 and NM1, and the drain electrode of PM1 and NM1 links to each other and connects the grid of PM2 and NM2, and the drain electrode of PM2 and NM2 links to each other as the output of delay unit circuit.Fig. 3 (b) is the circuit structure of decision device: input clock signal clk1, clk2 meet respectively NMOS pipe M1, the grid of M2, and M1, the source electrode of M2 links to each other and ground connection, and the drain electrode of M1 connects the source electrode of M3, and the drain electrode of M2 connects the source electrode of M4.The grid of M3 connects respectively the S end of SR latch and the drain electrode of M4, and the grid of M4 connects respectively the R end of R latch and the drain electrode of M3; The drain electrode of M3 connects the drain electrode of PMOS pipe M5, and the drain electrode of M4 connects the drain electrode of PMOS pipe M6, and the source electrode of M5, M6 meets power supply Vdd.Or the input of door OR1 connects respectively input clock signal clk1, clk2, or the door output termination M5 of OR1 and the grid of M6.The grid of the S input termination M3 of SR latch, the grid of R input termination M4; Output Q, Qn are as the output of whole decision device circuit.Fig. 3 (c) is the circuit structure of time amplifier: input signal clk1 and clk2 connect respectively the input of buffer buffer1 and buffer2, clk1 connects the input of NAND gate nand3, clk2 connects the input of NAND gate nand2, the output of buffer1 connects the input of nand1, and the output of buffer2 connects the input of nand4.The output of nand1 connects the input of nand2, and the output of nand2 connects the input of nand1, and the output of nand3 connects the input of nand4, and the output of nand4 connects the input of nand3.The output of nand1 connects the top crown of capacitor C 1, and the output of nand2 connects the top crown of capacitor C 2, and the output of nand3 connects the top crown of capacitor C 3, and the output of nand4 connects the top crown of capacitor C 4, capacitor C 1, C2, C3, the bottom crown ground connection of C4.The output of nand1 and nand2 connects the input of NOR gate xor1, and the output of nand3 and nand4 connects the input of NOR gate xor2, and the output of xor1 and xor2 is as the output of whole time amplifier circuit.Fig. 3 (d) is the circuit structure of voltage comparator: input signal v1 and v2 connect respectively the grid of NMOS pipe NM1 and NM2, and input control voltage vb connects the grid of NM3.The source electrode of NM1 and NM2 links to each other with the drain electrode of NM3, the source ground of NM3.The drain electrode of NM1 connects output terminals A, and the drain electrode of NM2 meets output B.One termination A of resistance R 1, the drain electrode of another termination PMOS pipe PM1, a termination B of resistance R 2, the drain electrode of another termination PM2.The grounded-grid of PM1 and PM2, the source electrode of PM1 and PM2 connects power supply.In addition, encoder, MUX and adder are described by hardware language, and phase discriminator and charge pump adopt traditional structure to realize.
Fig. 4 is the sequential analogous diagram of TDC circuit of the present invention.As can be seen from the figure, this TDC circuit carries out integration with the quantization error of per cycle generation with the form of voltage.When integrated value during greater than reference voltage Vref, voltage comparator output high level, final digital coding becomes 101 from 100.
In sum, the present invention adds an error by the basis at traditional VDL TDC and selects circuit and error intergal circuit, the error that produces in the quantizing process extracted and carry out integration, thereby avoided losing of quantization error information, realized the function of compensation quantization error and the characteristics of raising TDC resolution.
Claims (3)
1. a time-to-digit converter is characterized in that: comprise vernier delay line time-to-digit converter, error selection circuit, error intergal circuit and error compensation circuit; The first input signal and the second input signal are inputted described vernier delay line time-to-digit converter, described vernier delay line time-to-digit converter compares the time difference of the first input signal and the second input signal, and this time difference is quantified as digital coding exports error to and select circuit and error compensation circuit, the described time difference goes back error originated from input and selects circuit; Described error is chosen correct quantization error and is exported to the error intergal circuit after selecting circuit that the described time difference is amplified; Described error intergal circuit extracts described quantization error and integration, and with integrated value error originated from input compensating circuit; Described error compensation circuit compares integrated value and reference voltage, if integrated value greater than reference voltage, then makes digital coding add 1 output.
2. described time-to-digit converter according to claim 1, it is characterized in that: described vernier delay line time-to-digit converter comprises two delay line, N identical decision device and encoders of being comprised of N level delay cell, described error selects circuit to comprise N identical time amplifier and MUX, described error intergal circuit comprises a phase discriminator, a charge pump and a capacitor, and described error compensation circuit comprises a voltage comparator and an adder; Wherein:
The first input signal connects the delay line that is comprised of delay cell D1-1～D1-N, the second input signal connects the delay line that is comprised of delay cell D2-1～D2-N, the input of the decision device that the output termination of every grade of delay cell is corresponding, the output of decision device connects the input of encoder, and the output of encoder connects the input control end of MUX;
The input of the time amplifier that the output termination of every grade of delay cell is corresponding, the output of every grade of time amplifier connects the input of MUX;
The output of MUX connects the input of phase discriminator, and the output of phase discriminator connects the input of charge pump, and the output of charge pump connects the top crown of capacitor, the bottom crown ground connection of capacitor;
Electric charge delivery side of pump and reference voltage connect the input of voltage comparator;
The output of voltage comparator and the output of encoder connect the input of adder, and the output of adder is as the output of whole time-digital converter circuit.
3. described time-to-digit converter according to claim 1 is characterized in that: described vernier delay line time-to-digit converter is the time difference of the first input signal and the second input signal rising edge relatively.
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Cited By (21)
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| CN103257569A (en) * | 2013-05-23 | 2013-08-21 | 龙芯中科技术有限公司 | Circuit, method and system for time measurement |
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| CN104199275B (en) * | 2014-09-19 | 2016-08-31 | 中国人民解放军国防科学技术大学 | A kind of TDC time interval measurement temperature compensation |
| CN106681126A (en) * | 2016-12-09 | 2017-05-17 | 深圳市锐能微科技股份有限公司 | Time-digital converter and error calibration device and method thereof |
| CN107643674A (en) * | 2016-07-20 | 2018-01-30 | 南京理工大学 | A kind of Vernier type TDC circuits based on FPGA carry chains |
| CN107968649A (en) * | 2017-11-13 | 2018-04-27 | 东南大学 | A kind of high accuracy number time converter and its control method |
| CN108459491A (en) * | 2017-02-22 | 2018-08-28 | 精工爱普生株式会社 | Circuit device, physical amount measuring device, electronic equipment and moving body |
| CN109274376A (en) * | 2018-09-05 | 2019-01-25 | 东南大学 | A kind of ring-like time-to-digit converter of vernier that compressible maximum conversion is time-consuming |
| CN109450398A (en) * | 2018-09-30 | 2019-03-08 | 南京邮电大学 | A kind of programmable time amplifier |
| CN109884873A (en) * | 2018-04-23 | 2019-06-14 | 南京邮电大学 | A kind of time-to-digit converter using dynamic threshold technology |
| CN110069008A (en) * | 2019-04-29 | 2019-07-30 | 复旦大学 | A kind of time-to-digit converter system and the multiple delay phase-locked loop comprising the system |
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| CN111077760A (en) * | 2020-01-07 | 2020-04-28 | 东南大学 | Time-to-digital converter and conversion method |
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| CN113552793A (en) * | 2021-07-26 | 2021-10-26 | 大连理工大学 | Self-calibration high-precision digital time conversion circuit |
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| CN113552791A (en) * | 2021-06-08 | 2021-10-26 | 西安电子科技大学 | Ultra-high speed time encoder and encoding method based on transmission line traveling wave quantization |
| CN116300377A (en) * | 2023-03-06 | 2023-06-23 | 深圳市镭神智能系统有限公司 | Time-to-digital converter and laser radar |
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| CN103257569B (en) * | 2013-05-23 | 2015-10-21 | 龙芯中科技术有限公司 | Time measuring circuit, method and system |
| CN103532500B (en) * | 2013-10-22 | 2016-04-13 | 天津大学 | Wide input range electric capacity-comparator-type time-reversal mirror method and amplifier |
| CN103532500A (en) * | 2013-10-22 | 2014-01-22 | 天津大学 | Wide input range capacitor-comparer type time amplification method and amplifier |
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| CN107968649B (en) * | 2017-11-13 | 2021-01-12 | 东南大学 | High-precision digital time converter and control method thereof |
| CN109884873B (en) * | 2018-04-23 | 2021-10-29 | 南京邮电大学 | Time-to-digital converter adopting dynamic threshold technology |
| CN109884873A (en) * | 2018-04-23 | 2019-06-14 | 南京邮电大学 | A kind of time-to-digit converter using dynamic threshold technology |
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| CN109450398A (en) * | 2018-09-30 | 2019-03-08 | 南京邮电大学 | A kind of programmable time amplifier |
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| CN110401441A (en) * | 2019-07-30 | 2019-11-01 | 福州大学 | A kind of phase-locked loop circuit and its control method based on time register |
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| CN113552793B (en) * | 2021-07-26 | 2022-04-05 | 大连理工大学 | Self-calibration high-precision digital time conversion circuit |
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| CN116300377A (en) * | 2023-03-06 | 2023-06-23 | 深圳市镭神智能系统有限公司 | Time-to-digital converter and laser radar |
| CN116300377B (en) * | 2023-03-06 | 2023-09-08 | 深圳市镭神智能系统有限公司 | Time-to-digital converter and laser radar |
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| CN103078644B (en) | 2016-02-10 |
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