CN109450398A - A kind of programmable time amplifier - Google Patents
A kind of programmable time amplifier Download PDFInfo
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- CN109450398A CN109450398A CN201811153743.7A CN201811153743A CN109450398A CN 109450398 A CN109450398 A CN 109450398A CN 201811153743 A CN201811153743 A CN 201811153743A CN 109450398 A CN109450398 A CN 109450398A
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- 230000005611 electricity Effects 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 3
- 238000000034 method Methods 0.000 description 3
- 238000005259 measurement Methods 0.000 description 2
- 230000003321 amplification Effects 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000001514 detection method Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000002474 experimental method Methods 0.000 description 1
- 238000003384 imaging method Methods 0.000 description 1
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Classifications
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03G—CONTROL OF AMPLIFICATION
- H03G3/00—Gain control in amplifiers or frequency changers
- H03G3/20—Automatic control
- H03G3/30—Automatic control in amplifiers having semiconductor devices
- H03G3/3089—Control of digital or coded signals
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03G—CONTROL OF AMPLIFICATION
- H03G2201/00—Indexing scheme relating to subclass H03G
- H03G2201/60—Gain control characterized by varying time constants in control loop
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Abstract
The invention discloses a kind of programmable time amplifiers, including time-digital converter circuit TDC and time amplifier TA；Two input terminals of time-digital converter circuit TDC distinguish external input START and input STOP, the Q of time-digital converter circuit TDC0~QnThe Q of signal output end and time amplifier TA0~QnSignal input part one-to-one correspondence is connected, the D of TDCCOThe D of signal output end and time amplifier TACOSignal input part correspondence is connected.By digital control part control time amplifier TA gain N, when the trip point of TDC is forward, by after trip point N grade XOR gate output do it is cumulative, when the trip point of TDC rearward when, by before trip point N grade XOR gate export do it is cumulative.The problem of it is big that the present invention solves typical time amplifier leakage current, poor linearity makes the output of time amplifier TA have the good linearity.
Description
Technical field
The present invention relates to a kind of programmable time amplifiers, belong to fields of numeric control technique.
Background technique
TDC plays important role in many scientific research fields, according to its application, can be roughly divided into two types:
One kind is the TDC for measuring the flight time.This kind of TDC be mostly by measurement particle or laser flight time come detect with
The distance between target object, such as high-energy physics experiment, laser radar detection, 3D imaging technique etc..
Traditional delay chain TDC it is some require high measurement accuracy application in, such as medical image, high-precision 3D at
Picture, ADPLL higher to noise perfomiance requirements etc., the TDC based on delay-line structure cannot be met the requirements.And pipeline
Type TDC is then ideal selection in these applications.And TA is then most important one part.
Summary of the invention
Technical problem to be solved by the invention is to provide a kind of novel programmable time amplifiers, solve typical time
Poor linearity present in amplifier, the big problem of leakage current, make time amplifier of the invention have the preferable linearity with
Programmable-gain.
In order to solve the above-mentioned technical problem the present invention uses following technical scheme:
A kind of programmable time amplifier of the invention, including time-digital converter circuit TDC and time amplifier TA；
Two input terminals of the time-digital converter circuit TDC distinguish external input START and input STOP, the time figure
The Q of converter circuit TDC0~QnThe Q of signal output end and time amplifier TA0~QnSignal input part one-to-one correspondence is connected,
The D of the time-digital converter circuit TDCCOThe D of signal output end and time amplifier TACOSignal input part is corresponding to be connected
It connects, wherein n is the positive integer more than or equal to 3.
The above-mentioned every level-one START of time-digital converter circuit TDC and STOP make xor operation and send to time amplifier
TA passes through digital control module (an only simple traditional digital control module, without repeating) control time amplifier
The gain N of TA, it is when the trip point of the time-digital converter circuit TDC is forward, the N grade XOR gate after trip point is defeated
Do out it is cumulative, when the trip point of the time-digital converter circuit TDC rearward when, the N grade XOR gate before trip point is defeated
Cumulative, realization time-reversal mirror is done out.
Above-mentioned time amplifier TA includes n+1 delay cell N0~Nn, n or door OR0~ORn-1, n+1 MUX circuit
A0~An；Described first or door OR0Input terminal meets time amplifier input terminal Q respectively0With the first MUX circuit A0Output end,
Two or door OR1Input terminal meets time amplifier input terminal Q respectively1With the second MUX circuit A1Output end ... n-th or door ORn-1
Input terminal meets time amplifier input terminal Q respectivelynWith the (n+1)th MUX circuit AnOutput end；The first MUX circuit A0Input terminal
Ground connection and the second delay cell N respectively1Output end；Second MUX circuit A1Input terminal is grounded respectively and third delay cell N2Output
The (n+1)th MUX circuit A of end ...nInput terminal is grounded respectively and time amplifier input terminal Qn；N+1 MUX circuit A0~AnBy counting
The control of word control module；The first delay cell N0Input terminal be first or door OR0Output end, output end access number control
Molding block；Second delay cell N1Input terminal be second or door OR1Output end, output end one terminate the first MUX circuit A0, one
(n+1)th delay cell N is terminated into digital control ...nInput terminate the (n+1)th MUX circuit AnOutput end, output end one terminate
First MUX circuit A0, digital control module is accessed in one end.
Above-mentioned time-digital converter circuit TDC includes n delay cell M1~Mn, n comparator arb1~arbn；N
XOR gate X1~Xn；First XOR gate X1Input terminal meets input START and input STOP, output end Q respectively0；Second XOR gate
X2Input terminal meets the first delay cell M respectively1Output and input STOP, output end Q1... the n-th XOR gate XnInput terminal point
The (n-1)th delay cell M is not metn-1Output and input STOP, output end Qn-1；First comparator arb1Input terminal connects defeated respectively
Enter START and input STOP；Second comparator arb2Input terminal meets input STOP and the first delay cell M respectively1Output ...
N-th comparator arbnInput terminal meets input STOP and the n-th delay cell M respectivelynOutput.
First delay cell M1Input connect input START；Second delay cell M2Input meet the first delay cell M1's
The n-th delay cell M of output ...nThe (n-1)th delay cell of input Mn-1Output.
The value of n is 16.
A kind of programmable time amplifier of the present invention compared with the prior art by using the above technical solution, has following
Technical effect: programmable time amplifier designed by the present invention, using parallel input, the structure of Serial output is every by front TDC
Level-one START and STOP makees exclusive or input entry time amplifier TA, controls time amplifier TA's by digital control part
Gain, when the trip point of TDC is forward by after trip point part export, TDC trip point rearward when by trip point it
The problem of preceding part output, it is big to solve typical time amplifier leakage current, poor linearity, makes the output of time amplifier TA
With the good linearity.
Detailed description of the invention
Fig. 1 is the main body circuit block diagram of programmable time amplifier of the present invention；
Fig. 2 is the electrical block diagram of time-to-digit converter of the present invention；
Fig. 3 is the electrical block diagram of time amplifier of the present invention.
Specific embodiment
Specific embodiments of the present invention will be described in further detail with reference to the accompanying drawings of the specification.
As shown in Figure 1, a kind of digital controlled oscillator of work of the invention under nearly threshold power voltage, including time figure
Converter circuit TDC and time amplifier TA, wherein two input terminals difference of time-digital converter circuit TDC is external defeated
Enter START and STOP；The Q of time-digital converter circuit TDC0~Q16The Q of signal output end and time amplifier0~Q16Signal
Input terminal one-to-one correspondence is connected；The D of time-digital converter circuit TDCCOThe D of signal output end and time amplifier TACOLetter
Number input terminal correspondence is connected.
Programmable time amplifier of the invention is in actual application process, wherein time-digital converter circuit
TDC is further designed, as shown in Fig. 2, the time-digital converter circuit TDC is traditional delay chain time-to-digit converter.
The time-digital converter circuit TDC includes the first delay cell M1, the second delay cell M2, third delay cell M3Deng one
Totally 16 delay cell M1~M16；First comparator arb1, the second comparator arb2, third comparator arb3Deng 16 altogether ratios
Compared with device arb1~arb16；First XOR gate X1, the second XOR gate X2, third XOR gate X3Deng 16 XOR gate X altogether1~X16；Its
In: the first XOR gate X of time-digital converter circuit TDC1Input terminal connects the input of time-digital converter circuit TDC respectively
START and input STOP, output end Q0；Second XOR gate X2Input terminal meets the first delay cell M respectively1Output and the time
The input STOP of quantizer circuit TDC, output end Q1；Third XOR gate X3Input terminal meets the second delay cell M respectively2
Output and time-digital converter circuit TDC input STOP, output end Q2；And so on；
First comparator arb1Input terminal meets the input START and STOP of TDC respectively；Second comparator arb2Input terminal point
The input START and STOP of TDC are not met；Third comparator arb3Input terminal meets the input START and STOP of TDC respectively；With this
Analogize；First delay cell M1Input meet the input START of TDC；Second delay cell M2Input meet the first delay cell M1
Output；Third delay cell M3The second delay cell of input M2Output；And so on；
In practical application, the present invention proposes specific design not only for time-digital converter circuit TDC, and
Specific circuit structure is devised for time amplifier, as shown in figure 3, the time amplifier TA includes the first delay cell
N0, the second delay cell N1, third delay cell N2Deng 17 delay cell N altogether0~N16；First or door OR0, second or door
OR1, third or door OR2Deng 16 or OR altogether0~OR15；First MUX circuit A0, the second MUX circuit A1, third MUX circuit A2
Deng 17 MUX circuit A altogether0~A16, in which: the first or door OR of time amplifier TA0Input terminal connects time amplifier respectively
Input terminal Q0With the first MUX circuit A0Output end；The second or door OR of time amplifier TA1Input terminal connects time-reversal mirror respectively
Device input terminal Q1With the second MUX circuit A1Output end；The third or door OR of time amplifier TA2Input terminal connects the time respectively and puts
Big device input terminal Q2With third MUX circuit A2Output end；And so on；First MUX circuit A0Input terminal is grounded and second respectively
Delay cell N1Output end；Second MUX circuit A1Input terminal is grounded respectively and third delay cell N2Output end；Third MUX circuit
A2Input terminal is grounded respectively and the 4th delay cell N3Output end；And so on；17th MUX circuit A16Input terminal is grounded respectively
With time amplifier input terminal Q16；MUX circuit is by digital control control；First delay cell N0Input terminal be first or door
OR0Output end, output end access are digital control；Second delay cell N1Input terminal be second or door OR1Output end, output end
One the first MUX circuit A of termination0, one end is accessed digital control；Third delay cell N2Input terminal be third or door OR2Output
End, output end one terminate the second MUX circuit A1, one end is accessed digital control；And so on；17th delay cell N17Input
Terminate the 17th MUX circuit A16Output end, output end one terminate the first MUX circuit A0, one end is accessed digital control.Time puts
The output of big device TA is
Wherein, N indicates the amplification factor of TA, TQIndicating the delay time of delay cell, Δ indicates the quantization error of TDC,
DCOIndicate the output of TDC.
In conclusion programmable time amplifier designed by the present invention, using parallel input, the structure of Serial output will
The every level-one START of front TDC and STOP makees exclusive or input entry time amplifier TA, is put by the digital control part control time
The gain of big device TA, exports the part after trip point when the trip point of TDC is forward, TDC trip point rearward when will
The problem of part output before trip point, it is big to solve typical time amplifier leakage current, poor linearity, make time amplifier
The output of TA has the good linearity.
Embodiments of the present invention are explained in detail above in conjunction with attached drawing, but the present invention is not limited to above-mentioned implementations
Mode within the knowledge of a person skilled in the art can also be without departing from the purpose of the present invention
It makes a variety of changes.
Claims (6)
1. a kind of programmable time amplifier, it is characterised in that: including time-digital converter circuit TDC and time amplifier
TA；Two input terminals of the time-digital converter circuit TDC distinguish external input START and input STOP, the time
The Q of quantizer circuit TDC0~QnThe Q of signal output end and time amplifier TA0~QnSignal input part corresponds phase
Connection, the D of the time-digital converter circuit TDCCOThe D of signal output end and time amplifier TACOSignal input part is corresponding
It is connected, wherein n is the positive integer more than or equal to 3.
2. programmable time amplifier according to claim 1, it is characterised in that: the time-digital converter circuit
The every level-one START of TDC and STOP make xor operation and send to time amplifier TA, control time-reversal mirror by digital control module
The gain N of device TA, when the trip point of the time-digital converter circuit TDC is forward, by the N grade XOR gate after trip point
Output do it is cumulative, when the trip point of the time-digital converter circuit TDC rearward when, by the N grade XOR gate before trip point
Cumulative, realization time-reversal mirror is done in output.
3. programmable time amplifier according to claim 1 or 2, it is characterised in that: the time amplifier TA includes n
+ 1 delay cell N0~Nn, n or door OR0~ORn-1, n+1 MUX circuit A0~An；
Described first or door OR0Input terminal meets time amplifier input terminal Q respectively0With the first MUX circuit A0Output end, second
Or door OR1Input terminal meets time amplifier input terminal Q respectively1With the second MUX circuit A1Output end ... n-th or door ORn-1It is defeated
Enter end and meets time amplifier input terminal Q respectivelynWith the (n+1)th MUX circuit AnOutput end；
The first MUX circuit A0Input terminal is grounded respectively and the second delay cell N1Output end；Second MUX circuit A1Input terminal
Ground connection and third delay cell N respectively2The (n+1)th MUX circuit of output end ... AnInput terminal is grounded respectively and time amplifier input
Hold Qn；N+1 MUX circuit A0~AnIt is controlled by digital control module；
The first delay cell N0Input terminal be first or door OR0Output end, output end access digital control module；Second
Delay cell N1Input terminal be second or door OR1Output end, output end one terminate the first MUX circuit A0, one end access number control
The (n+1)th delay cell N of system ...nInput terminate the (n+1)th MUX circuit AnOutput end, output end one terminate the first MUX circuit
A0, digital control module is accessed in one end.
4. programmable time amplifier according to claim 1 or 2, it is characterised in that: the time-to-digit converter electricity
Road TDC includes n delay cell M1~Mn, n comparator arb1~arbn；N XOR gate X1~Xn；
First XOR gate X1Input terminal meets input START and input STOP, output end Q respectively0；Second XOR gate X2Input terminal
The first delay cell M is met respectively1Output and input STOP, output end Q1... the n-th XOR gate XnInput terminal connects n-th-respectively
1 delay cell Mn-1Output and input STOP, output end Qn-1；
First comparator arb1Input terminal meets input START and input STOP respectively；Second comparator arb2Input terminal connects defeated respectively
Enter STOP and the first delay cell M1The n-th comparator of output ... arbnInput terminal connects input STOP and the n-th delay cell respectively
MnOutput.
5. programmable time amplifier according to claim 4, it is characterised in that: the first delay cell M1Input connect it is defeated
Enter START；Second delay cell M2Input meet the first delay cell M1The n-th delay cell of output ... MnInput (n-1)th
Delay cell Mn-1Output.
6. programmable time amplifier according to claim 1, it is characterised in that: the value of n is 16.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811153743.7A CN109450398B (en) | 2018-09-30 | 2018-09-30 | Programmable time amplifier |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811153743.7A CN109450398B (en) | 2018-09-30 | 2018-09-30 | Programmable time amplifier |
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| Publication Number | Publication Date |
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| CN109450398A true CN109450398A (en) | 2019-03-08 |
| CN109450398B CN109450398B (en) | 2022-11-29 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN201811153743.7A Active CN109450398B (en) | 2018-09-30 | 2018-09-30 | Programmable time amplifier |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113162566A (en) * | 2021-05-17 | 2021-07-23 | 合肥工业大学 | Programmable high-precision high-dynamic-range time amplifier |
Citations (3)
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|---|---|---|---|---|
| KR20110118458A (en) * | 2010-04-23 | 2011-10-31 | 삼성전자주식회사 | A time to digital converter and proceesing method of the time to converter |
| CN103078644A (en) * | 2012-12-31 | 2013-05-01 | 东南大学 | Time-to-digit converter |
| CN108521280A (en) * | 2018-04-12 | 2018-09-11 | 中国科学院微电子研究所 | A kind of time amplifier calibration method of combination two-step time-to-digit converter |
-
2018
- 2018-09-30 CN CN201811153743.7A patent/CN109450398B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20110118458A (en) * | 2010-04-23 | 2011-10-31 | 삼성전자주식회사 | A time to digital converter and proceesing method of the time to converter |
| CN103078644A (en) * | 2012-12-31 | 2013-05-01 | 东南大学 | Time-to-digit converter |
| CN108521280A (en) * | 2018-04-12 | 2018-09-11 | 中国科学院微电子研究所 | A kind of time amplifier calibration method of combination two-step time-to-digit converter |
Non-Patent Citations (1)
| Title |
|---|
| 魏星 等: "基于新型时间放大器流水线时间数字转换器", 《太赫兹科学与电子信息学报》 * |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113162566A (en) * | 2021-05-17 | 2021-07-23 | 合肥工业大学 | Programmable high-precision high-dynamic-range time amplifier |
| CN113162566B (en) * | 2021-05-17 | 2022-12-06 | 合肥工业大学 | Programmable high-precision high-dynamic-range time amplifier |
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