CN106059521A - Time amplifier based on delay chain structure - Google Patents
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03G—CONTROL OF AMPLIFICATION
- H03G3/00—Gain control in amplifiers or frequency changers
- H03G3/20—Automatic control
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K23/00—Pulse counters comprising counting chains; Frequency dividers comprising counting chains
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Abstract
The invention discloses a time amplifier based on a delay chain structure. The time amplifier comprises a time sample-and-hold unit, a time amplification unit, a trigger and an exclusive-OR gate, wherein the time sample-and-hold unit is triggered by an enabling high-level signal, and used for realizing sampling and holding of an input pulse signal Tin; the time amplification unit is used for linearly amplifying the input pulse signal Tin which is subjected to sampling and holding; the trigger is triggered by a falling edge of the input pulse signal Tin; and the exclusive-OR gate is used for performing an exclusive-OR logical operation on the output of the time amplification unit and the output of the trigger, and transforming a high level to a low level in order to realize M-times amplification of the input pulse signal Tin. Through adoption of the time amplifier based on the delay chain structure provided by the invention, linear, accurate and dynamically-settable time amplification gain values can be realized. When the time amplifier is applied to a TDC (Time-to-Digital Converter), the conversion rate of the TDC can be increased.
Description
Technical field
The present invention is about a kind of time domain amplifier based on delay chain structure (time amplifier), particularly a kind of suitable
For time m-digital converter (TDC) time domain amplifier.
Background technology
Simulate, (such as all-digital phase-locked loop ADPLLs and time domain modulus turn the Digital Realization trend of mixed signal circuit
Parallel operation ADCs) make time domain become more and more important to numeric field transducer (TDC).As it is shown in figure 1, Fig. 1 is that tradition PLL is with complete
Digital PLL, ADC contrast with the structured flowchart of time domain ADC.In ADPLL, TDC and digital loop filters (DLF) instead of biography
The analog circuit (electric charge pump and loop filter) of system.But, in order to minimize the output clock jitter of digital phase-locked loop, need
Improve the precision of TDC.On the other hand, in order to maximize the incoming frequency scope of digital phase-locked loop, when needing the input improving TDC
Between scope.
To this end, scholars utilize the CMOS integrated circuit technique of advanced person, develop substantial amounts of TDC technology.Current CMOS
TDC technology is based primarily upon gate delay unit, benefits from CMOS technology characteristic size and reduces, and the time delay of gate delay unit is corresponding
Reducing, this is conducive to the raising of TDC time precision.
Time delay chain TDC is the earliest, to be also the most widely used customization TDC structure, its operation principle and structure and tradition electricity
Flash-type analog-digital converter ADC is similar for die pressing type.Its, depositor unit cascaded by gate delay and thermometer encoder form.This
The advantage planting structure is simple in construction, can realize with digital logic gate, and particularly time figure switching rate is all customizations
In TDC structure the fastest, but its time precision is limited to the gate delay time, its time-quantum method scope is little simultaneously, for increase
Add the quantity that its time-quantum method scope often leads to delay cell to linearly increase, thus increase chip area and power consumption, additionally,
Also reduce time figure switching rate.
In order to solve the problems referred to above, gate delay unit is used to realize the temporal resolution less than single gate delay, scholar
Propose vernier type TDC structure, this TDC contains two delay lines being respectively arranged with same number delay cell, by making two
In bar delay line there is trickle time difference in td1 and td2 time delay of gate delay unit, and can realize precision is △=td1-
The time interval measurement of td2, therefore, in theory by adjusting the time difference of two delay line delay cells, can measure nothing
Limit little time precision.2000, D.Piotr et al. devised a vernier type TDC, and its highest resolution is up to 5ps.But
Being that vernier type TDC is not unlimited raising to the raising of time precision, the actual multiple that improves is limited in 4-10 times.Meanwhile, prolong
Limiting factor (such as time-quantum method scope, the poor linearity that the non-match error of delay cell causes) in chain TDC is in trip late
In mark type TDC more seriously, in the range of identical time-quantum method, its switching rate is also below delay chain TDC.Although can use
Collimation technique compensates these errors, but collimation technique is complicated and needs according to depending on system structure.
In recent years, in order to, while improving TDC time precision, improve its switching rate, time amplifier thought is met the tendency
And give birth to, based on time amplifier, time interval can be carried out " thick quantization-amplify-carefully quantify ", simply use coarse quantization
Device just can obtain higher temporal resolution.To this end, there is researcher to propose different types of time domain amplifier.At document
[Time difference amplifier] and [A 9b, 1.25ps resolution coarse-fine time-to-
Digital converter in 90nm CMOS that amplifies a time residue] in, time domain amplifier is led to
Cross and use the S/R latch of input time_varying sequence to realize, as in figure 2 it is shown, S/R latch works in metastable zone.But it lacks
Point is: the gain of the most this time domain amplifier is unpredictable and inaccuracy；2. due to its meta-stable behavior, so needing correction；
3. input linear scope is the least, and gain is immutable.Document [A 1.25ps resolution 8b cyclic TDC in
0.13 μm CMOS] propose a kind of different metastable state time domain amplifier, as shown in Figure 3.Although this circuit is also adopted by being similar to
Cross coupling structure shown in Fig. 2, but its gain is relatively easy to control, because its gain is by arranging between two discharge paths
Different discharge capacities determine, gain is about 2, and owing to being cross-coupled structure, this circuit yet suffers from gain inexactness
The problem not enough with input linear scope, so being also required to correction.Document [A128-channel, 9ps column-parallel
two-stage TDC based on time difference amplification for time-resolved
Imaging] propose another time domain amplifier, as shown in Figure 4, it is different from above two kinds of time domain amplifier.By adopting
By cross-couplings chain of delay and the difference of their transmission time, obtain the amplification of time.But this structure there is also
Non-linear gain and the problem needing DLL to correct, meanwhile, gain is immutable.In order to obtain line in wide input range
Property, gain precisely and variably, document [A 7bit, 3.75ps resolution two-step time-to-digital
Converter in 65nm CMOS using pulse-train time amplifier] when proposing a kind of pulse train
Territory amplifier, as shown in Figure 5.The basic thought of this structure is the sequence N number of identical pulse (pulse width is Tin) constituted
Being equivalent to a wide pulse, the pulse width of this broad pulse is N × Tin.Pulse train and broad pulse have identical total
Pulse width, therefore by this concept, can realize Tin pulse width and be enlarged into the pulse width of N × Tin.But, time this
Territory amplifier architecture is in order to avoid overlap interpulse in pulse train, and it needs sufficiently long time delay, and therefore this can lead
Cause the reduction of TDC switching rate.
In view of background above, need to propose a kind of disclosure satisfy that can obtain in wide input range linear, accurately and can
The gain become and the time domain amplifier based on delay chain structure of the TDC switching rate that can improve its application.
Summary of the invention
(1) to solve the technical problem that
Present invention is primarily targeted at and providing a kind of gain is base that is linear, accurate and that can dynamically set, change
Time domain amplifier in delay chain structure.
(2) technical scheme
For reaching above-mentioned purpose, the invention provides a kind of time domain amplifier based on delay chain structure, should be based on delay
The time domain amplifier of chain structure includes time sampling holding unit, time-reversal mirror unit, trigger and XOR gate, wherein: the time
Sample holding unit, is triggered by enabling high level signal, for realizing the sampling to input pulse signal Tin and holding；Time
Amplifying unit, for carrying out linear amplification to the input pulse signal Tin with holding of sampling；Trigger, is believed by input pulse
The trailing edge of number Tin triggers；XOR gate, for carrying out XOR fortune to the output of the output of time-reversal mirror unit with trigger
Calculate, transfer high level to low level, it is achieved M times of input pulse signal Tin is amplified.
In such scheme, described time sampling holding unit has the first delay chain, and this first delay chain is by multiple delays
Unit is in series, and the Enable Pin of each delay cell is triggered by enabling high level signal, and input pulse signal Tin is sampled and protected
Hold in the first delay chain of time sampling holding unit.
In such scheme, described time-reversal mirror unit has the second delay chain sum counter, and this second delay chain is by multiple
Delay cell is in series, and described time-reversal mirror unit is by the input pulse in described time sampling holding unit the first delay chain
Signal Tin copies in the second delay chain of time-reversal mirror unit, by setting count value M of enumerator, makes input pulse believe
Number Tin circulates M time in the second delay chain of time-reversal mirror unit, so that the single wide pulse signal Tout pulse of output
Width is M times of the single narrow pulse signal Tin pulse width of input.
In such scheme, the Enable Pin of the delay cell in the second delay chain of described time-reversal mirror unit by switch with
Power vd D is connected, and enables high level and triggers, and wherein, switch is defeated by delay cell corresponding in time sampling holding unit
Go out signal C0、C1、…、CnControl, high level switch conduction, low level switches off.
In such scheme, in described time-reversal mirror unit, the output of each delay cell is connected to meter by a switch respectively
The input end of clock of number device, control signal Cout of switch conduction and output signal C of delay cell in sample holding unit0、
C1、…、CnBetween relation as shown in the table, wherein, Cout has log2(n+1) position control bit:
In such scheme, when output signal C of delay cell in described time sampling holding uniti(i=0,1 ..., n)
During for high level, the first switches set conducting between time sampling holding unit and time-reversal mirror unit, in time-reversal mirror unit
Delay cell connect power supply and normally work；And delay cell Reset signal each with time-reversal mirror unit be connected
The work of two switches set, then need according to Ci(i=0,1 ..., n) depending on, corresponding truth table is as shown above；In conjunction with true
Value table, by the first switches set and second switch group, time sampling holding unit is by the input pulse signal Tin's that records
Pulse width passes to time-reversal mirror unit.
In such scheme, when Reset signal is become high level from low level, enumerator M count once, meanwhile, the time
All delay cells in amplifying unit reset, and when the counting of enumerator is full, produce carry-out A.
In such scheme, it is high level that the trailing edge of input pulse signal Tin triggers described trigger output B, now counts
Number device output A is low level, and XOR gate output is transferred to high level by low level；When rolling counters forward is full, produce carry-out A
For high level, XOR gate output is become low level from high level.
(3) beneficial effect
Time domain amplifier based on delay chain structure provided by the present invention can realize linear, accurate and can dynamically set
Fixed time-reversal mirror yield value.It applies in TDC, the switching rate of TDC can be made to obtain and improve.
Accompanying drawing explanation
Fig. 1 is the structured flowchart contrast of tradition PLL and digital PLL, ADC with time domain ADC.
Fig. 2 is time domain amplifier based on delay chain structure based on S/R latch.
Fig. 3 is the time domain amplifier based on delay chain structure of a kind of meta-stable behavior.
Fig. 4 is time domain amplifier based on cross-couplings chain of delay.
Fig. 5 is pulse train time domain amplifier.
Fig. 6 is the schematic diagram of the time domain amplifier based on delay chain structure according to the embodiment of the present invention.
Fig. 7 is the schematic diagram of the time domain amplifier based on delay chain structure according to another embodiment of the present invention.
Fig. 8 is corresponding to Fig. 7, the working timing figure as Tin=4 τ, n=7, M=3.
Detailed description of the invention
For making the object, technical solutions and advantages of the present invention clearer, below in conjunction with specific embodiment, and reference
Accompanying drawing, the present invention is described in more detail.
As shown in Figure 6 and Figure 7, embodiments provide a kind of time domain amplifier based on delay chain structure, this time
Territory amplifier includes time sampling holding unit, time-reversal mirror unit, trigger and XOR gate, wherein: time sampling keeps single
Unit, is triggered by enabling high level signal, for realizing the sampling to input pulse signal Tin and holding；Time-reversal mirror unit, uses
In input pulse signal Tin that is that sample and that keep is carried out linear amplification；Trigger, by the decline of input pulse signal Tin
Along triggering；XOR gate, for the output of the output of time-reversal mirror unit with trigger is carried out XOR computing, turns high level
For low level, it is achieved M times of input pulse signal Tin is amplified.
Wherein, time sampling holding unit has the first delay chain, this first delay chain connected by multiple delay cells and
Becoming, the Enable Pin of each delay cell is triggered by enabling high level signal, and the time that is sampled and held at by input pulse signal Tin adopts
In first delay chain of sample holding unit.
Time-reversal mirror unit has the second delay chain sum counter, this second delay chain connected by multiple delay cells and
Becoming, the input pulse signal Tin in time sampling holding unit the first delay chain is copied to time-reversal mirror by time-reversal mirror unit
In second delay chain of unit, by setting count value M of enumerator, make input pulse signal Tin at time-reversal mirror unit
Second delay chain circulates M time, so that the single wide pulse signal Tout pulse width of output is the single narrow arteries and veins of input
Rush signal Tin pulse width M times.
The Enable Pin of the delay cell in the second delay chain of time-reversal mirror unit is connected with power vd D by switch,
Enable high level triggers, and wherein, switchs by output signal C of delay cell corresponding in time sampling holding unit0、C1、…、
CnControl, high level switch conduction, low level switches off.
The clock that in time-reversal mirror unit, the output of each delay cell is connected to enumerator by a switch respectively inputs
End, control signal Cout of switch conduction and output signal C of delay cell in sample holding unit0、C1、…、CnBetween pass
Being as shown in the table, wherein, Cout has log2(n+1) position control bit:
When output signal C of delay cell in time sample holding uniti(i=0,1 ..., when n) being high level, the time
The first switches set conducting between sample holding unit and time-reversal mirror unit, the delay cell in time-reversal mirror unit connects electricity
Source and normally work；And the work of second switch group that delay cell Reset signal each with time-reversal mirror unit is connected, then
Need according to Ci(i=0,1 ..., n) depending on, corresponding truth table is as shown above；In conjunction with truth table, by the first switch
Group and second switch group, when the pulse width of the input pulse signal Tin recorded is passed to by time sampling holding unit
Between amplifying unit.
When Reset signal is become high level from low level, enumerator M count once, meanwhile, in time-reversal mirror unit
All delay cells reset, and when the counting of enumerator is full, produce carry-out A.
It is high level that the trailing edge of input pulse signal Tin triggers trigger output B, and this hour counter output A is low electricity
Flat, XOR gate output is transferred to high level by low level；When rolling counters forward is full, generation carry-out A is high level, XOR gate
Output is become low level from high level.
Please again according to Fig. 6, the time domain amplifier based on delay chain structure shown in Fig. 6 is made up of four essential parts:
Time sampling holding unit 60, time-reversal mirror unit 61, XOR gate 62 and d type flip flop 63.Wherein, time sampling holding unit by
Delay cell 601,602 ..., 606 etc. constitute delay chain structure.Time-reversal mirror unit by switches set 6131,6132 ..., 6137,
Switches set 6121,6122 ..., 6127, delay cell 6101,6102 ..., 6107 and enumerator 64 are constituted.
In Fig. 6, time sampling holding unit 60 is under the high level of input Tin enables, and logic 1 level is by delay cell
601,602 ..., 606 etc. constitute in delay chain and transmit, until Tin is low level, now delay cell 601,602 ..., 606 by
Duty transfers hold mode to.Control switch 6131,6132 ..., the break-make of 6137 by C0, C1 ..., Cn, Cout according to
C0, C1 ..., the Determines switch 6121 of Cn, 6122 ..., the break-make of 6127, thus realize Tin pulse temporal width multiple
Make in time amplifying unit 61.When the trailing edge of Tin arrives, trigger d type flip flop 63 and export high level signal, this high electricity
Ordinary mail number produces the high level output of Tout by XOR gate 62, and the high level signal of d type flip flop 63 output simultaneously was put in the time
Circulating M time the count value of enumerator 64 (M be) in the delay chain of big unit, circulate M required time is Tin × M, expires when circulating
When M time, enumerator 64 produces carry high level output, and by XOR gate 62, Tout is transferred to low level by high level, thus realizes
M times of Tin is amplified.
Specifically, when Tin becomes high level, delay cell 601,602 ..., 606 etc. enabling work, logic 1 is being prolonged
Transmitting in chain late, C0, C1 ..., Cn are transferred to high level by level successively, until Tin becomes low level, delay cell 601,
602 ..., 606 etc. enable and quit work, the time interval that therefore Tin pulse width is corresponding is maintained at time sampling holding unit
In the delay chain of 60；Switch 6131 in time-reversal mirror unit 61,6132 ..., 6137 controlled by corresponding C0, C1 ..., Cn,
High level turns on, and low level disconnects.When switch 6131,6132 ..., 6137 conducting, delay cell 6101,6102 ..., 6107 companies
Connect power supply and normally work.Switch 6121,6122 ..., 6127 respectively with Cout control word group one_to_one corresponding, any instant, only
Having one group of Cout control word effective, i.e. switch 6121,6122 ..., only one of which is conducting state in 6127, remaining disconnects.
In Cout and sample holding unit, the relation between the output signal (C0, C1 ..., Cn) of delay cell is as shown in the table, wherein,
Cout has log2(n+1) position control bit:
By switches set 6131,6132 ..., 6137 and switches set switch 6121,6122 ..., 6127, can be by time sampling
The time Tin that holding unit 60 samples copies in time-reversal mirror unit 61.
When the trailing edge triggering d type flip flop 63 of Tin produces high level output, its high level output produced is to XOR gate
The B input of 62, the enumerator carry-out connected due to the A input of XOR gate 62 is low level, so Tout is by low electricity
Flat turn is high level.With this simultaneously, the high level signal of d type flip flop 63 output will depend in the delay chain of time-reversal mirror unit 60
Secondary transmission, after elapsed time Tin, Reset signal is high, rolling counters forward 1 time, simultaneously delay cell 6101,6102 ...,
6107 reset, and Reset signal is transferred to low level by high level, circulates M time with this, until enumerator produces after completing M counting
Raw carry high level output, now the A input of XOR gate 62 is high level, and XOR gate 62 exports and transferred to low electricity by high level
Flat, M times that Tout pulse temporal width is Tin pulse temporal width of generation.
Fig. 7 is the schematic diagram of the time domain amplifier based on delay chain structure of another embodiment of the present invention, with Fig. 6 in Fig. 7
Corresponding circuit or element, its function repeats no more.Assume that delay cell number is 8 (i.e. n=7), counter M=
3, Tin=4 τ, truth table when following table is n=7, between Cout Yu C0, C1 ..., C7.When the pulse width of Tin is 4 τ, the most right
Answering the switch conduction that C0, C1, C2, C3 and Cout=011 control, rest switch disconnects.From the sequential working figure of Fig. 8, warp
Tout=12 τ after amplification, it is achieved that 3 times of amplifications of time.
Particular embodiments described above, has been carried out the purpose of the present invention, technical scheme and beneficial effect the most in detail
Describe in detail bright, be it should be understood that the specific embodiment that the foregoing is only the present invention, be not limited to the present invention, all
Within the spirit and principles in the present invention, any modification, equivalent substitution and improvement etc. done, should be included in the guarantor of the present invention
Within the scope of protecting.
Claims (8)
1. a time domain amplifier based on delay chain structure, it is characterised in that this time domain amplifier includes that time sampling keeps
Unit, time-reversal mirror unit, trigger and XOR gate, wherein:
Time sampling holding unit, is triggered by enabling high level signal, for realizing the sampling to input pulse signal Tin and guarantor
Hold；
Time-reversal mirror unit, for carrying out linear amplification to the input pulse signal Tin with holding of sampling；
Trigger, is triggered by the trailing edge of input pulse signal Tin；
XOR gate, for the output of the output of time-reversal mirror unit with trigger is carried out XOR computing, transfers to high level
Low level, it is achieved M times of input pulse signal Tin is amplified.
Time domain amplifier based on delay chain structure the most according to claim 1, it is characterised in that described time sampling is protected
Holding unit and have the first delay chain, this first delay chain is in series by multiple delay cells, the Enable Pin of each delay cell by
Enable high level signal triggers, and input pulse signal Tin is sampled and held at the first delay chain of time sampling holding unit
In.
Time domain amplifier based on delay chain structure the most according to claim 1, it is characterised in that described time-reversal mirror list
Unit has the second delay chain sum counter, and this second delay chain is in series by multiple delay cells, described time-reversal mirror unit
Input pulse signal Tin in described time sampling holding unit the first delay chain is copied to the second of time-reversal mirror unit prolong
Late in chain, by setting count value M of enumerator, make input pulse signal Tin in the second delay chain of time-reversal mirror unit
Circulate M time, so that the single wide pulse signal Tout pulse width of output is the single narrow pulse signal Tin pulse of input
M times of width.
Time domain amplifier based on delay chain structure the most according to claim 3, it is characterised in that described time-reversal mirror list
The Enable Pin of the delay cell in the second delay chain of unit is connected with power vd D by switch, enables high level and triggers, its
In, switch by output signal C of delay cell corresponding in time sampling holding unit0、C1、...、CnControl, high level is opened
Closing conducting, low level switches off.
Time domain amplifier based on delay chain structure the most according to claim 4, it is characterised in that described time-reversal mirror list
In unit, the output of each delay cell is connected to the input end of clock of enumerator respectively by a switch, the control letter of switch conduction
Number Cout and output signal C of delay cell in sample holding unit0、C1、...、CnBetween relation as shown in the table, wherein,
Cout has log2(n+1) position control bit:
Time domain amplifier based on delay chain structure the most according to claim 5, it is characterised in that when described time sampling
Output signal C of delay cell in holding uniti(i=0,1 ..., when n) being high level, time sampling holding unit and time
The first switches set conducting between amplifying unit, the delay cell in time-reversal mirror unit connects power supply and normally works；And with
In time-reversal mirror unit, the work of the second switch group that each delay cell Reset signal is connected, then need according to Ci(i=0,
1 ..., n) depending on, corresponding truth table is as shown above；In conjunction with truth table, by the first switches set and second switch group,
The pulse width of the input pulse signal Tin recorded is passed to time-reversal mirror unit by time sampling holding unit.
Time domain amplifier based on delay chain structure the most according to claim 6, it is characterised in that when Reset signal by
When low level becomes high level, once, meanwhile, all delay cells in time-reversal mirror unit reset enumerator M count, work as meter
When the counting of number device is full, produce carry-out A.
Time domain amplifier based on delay chain structure the most according to claim 6, it is characterised in that input pulse signal
It is high level that the trailing edge of Tin triggers described trigger output B, and this hour counter output A is low level, and XOR gate exports by low
Level transfers high level to；When rolling counters forward is full, generation carry-out A is high level, and XOR gate output is become from high level
Low level.
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| CN110824889A (en) * | 2019-11-08 | 2020-02-21 | 中山大学 | Time-to-digital converter based on novel time amplifier |
| CN111669137A (en) * | 2020-04-27 | 2020-09-15 | 上海交通大学 | Self-adaptive variable gain delay amplifier |
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| CN108549205A (en) * | 2018-04-12 | 2018-09-18 | 中国科学院微电子研究所 | A kind of two-step time-to-digit converter based on time amplifier |
| CN108549205B (en) * | 2018-04-12 | 2020-08-04 | 中国科学院微电子研究所 | Two-step time-to-digital converter based on time amplifier |
| CN110824889A (en) * | 2019-11-08 | 2020-02-21 | 中山大学 | Time-to-digital converter based on novel time amplifier |
| CN111669137A (en) * | 2020-04-27 | 2020-09-15 | 上海交通大学 | Self-adaptive variable gain delay amplifier |
| CN111669137B (en) * | 2020-04-27 | 2022-02-11 | 上海交通大学 | Self-adaptive variable gain delay amplifier |
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