CN111669137B - Self-adaptive variable gain delay amplifier - Google Patents
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Abstract
The invention provides a self-adaptive variable gain delay amplifier, which comprises: the two-path self-adaptive pulse contraction circuit is used for receiving the two paths of pulse signals and contracting the time delay between the two paths of pulse signals when the time delay of the two paths of pulse signals is greater than a threshold value, so that the time delay of the two paths of pulse signals is adaptive to the input variable range of the variable gain time delay amplifying circuit; and the variable gain time-delay amplifying circuit amplifies the time delay of the two-way pulse signal output by the two-way self-adaptive pulse shrinking circuit based on the metastable state effect of the RS latch. The implementation and control mode of the delay amplifier provided by the invention has the advantages of simple structure, controllable gain and strong stability; and a mode of preprocessing input by adopting a double-path self-adaptive pulse contraction unit is adopted, the linear interval and the dynamic gain are improved, and the gain is controllable.
Description
Technical Field
The present invention relates to the field of semiconductor integrated circuits, and in particular, to a delay amplifier, and more particularly, to an adaptive variable gain delay amplifier.
Background
As Complementary Metal Oxide Semiconductor (CMOS) technology evolves below 10 nanometers, voltage signal based designs become more challenging due to reduced gain, increased leakage current, and reduced signal power. And the process is reduced, so that the time delay of the door is smaller, and the information processing by using the time delay information becomes more competitive. Processing techniques based on delay information can be more adaptable to the trend towards smaller areas, higher integration densities and faster switching speeds for integrated circuit designs. In time domain information processing, a time-to-digital converter (TDC) serves as a front-end module responsible for quantizing the time interval of two rising edges and extracting the information therein. In addition, the TDC is widely used in time of flight (ToF) in high-energy physics, All Digital Phase Locked Loop (ADPLL), high-speed data transmission, jitter measurement in integrated circuit testing, and the like.
In order to improve the time resolution of the TDC, it is necessary to amplify the input of the previous stage using a delay amplifier. The time delay amplifier circuit amplifies the interval between the rising edge and the falling edge of the two signals, so that a subsequent circuit can extract data information conveniently according to time delay information, and information processing is realized.
Current delay amplifiers mainly comprise: (1) using the metastable effect of the SR latch; (2) based on a controlled discharge principle; (3) pulse train circuit based (pulse train); (4) based on a ring oscillator circuit; (5) based on variable chains, etc. The above main designs can be divided into two types, wherein (1) and (2) realize the input amplification output by changing the charging and discharging time of input and output, and are similar to analog amplification circuits. The advantage is that it can amplify tiny signal, the disadvantage is that the linearity of amplification is poor, the variable range of input is small; the pulse sequence-based amplifying circuit can realize superposition of a plurality of circuits, but is difficult to work independently and needs a subsequent TDC circuit to complete the cooperation; the amplifying circuit based on the variable chain or the frequency variable ring oscillator utilizes the amplification realized by different units or different oscillation periods before and after switching, and has the characteristics of large amplification range, good controllability, good PVT change resistance and the like. However, the frequency and speed of the conventional ring oscillator based on inverters or nand gates are limited by the limitations of the inverters or nand gates. Meanwhile, in the process of changing the size of the inverter, the adjustable range depends on the adjustable range of the size of the inverter, when multiple amplification factors are required, more inverter circuits need to be integrated to increase the adjustable capacity, and therefore the amplification selectivity is weaker.
Disclosure of Invention
In view of the defects in the prior art, an object of the present invention is to provide an adaptive variable gain delay amplifier, which solves the problem of small linear range of the existing delay amplifier by combining an amplifying circuit based on metastable state effect of SR latch with an adaptive pulse shrinking circuit.
The technical scheme provided by the invention is as follows:
an adaptive variable gain delay amplifier, comprising:
the two-path self-adaptive pulse contraction circuit is used for receiving the two paths of pulse signals and contracting the time delay between the two paths of pulse signals when the time delay of the two paths of pulse signals is greater than a threshold value, so that the time delay of the two paths of pulse signals is adaptive to the input variable range of the variable gain time delay amplifying circuit;
and the variable gain delay amplifying circuit amplifies the delay of the two-way pulse signal output by the two-way self-adaptive pulse shrinking circuit based on the metastable state effect of the RS latch.
The invention is further improved in that each path of the self-adaptive pulse shrinking circuit comprises an inverter chain and a plurality of time delay extraction units;
the inverter chain is used for receiving a path of pulse signal X;
the output end of the delay extraction unit is connected with the control end of a discharge circuit; the discharge circuit is connected with the input end of one inverter of the inverter chain;
the delay extraction unit is used for judging whether the delay between the pulse signal X received by the phase inverter chain and the other path of pulse signal Y is larger than a threshold value or not, and controlling the discharge circuit to discharge the input capacitor of the phase inverter connected with the discharge circuit when the delay is larger than the threshold value, so that the propagation speed of the pulse signal X is reduced.
The invention further improves that the discharge circuit comprises a transistor, the grid of the transistor is connected with the output end of the delay extraction unit, one pole of the other two poles of the transistor is connected with the input end of the inverter, and the other pole of the transistor is grounded; when the pulse strength output by the delay extraction unit is greater than the conduction threshold of the transistor, the transistor is conducted, so that the input capacitor of the inverter is discharged.
The further improvement of the present invention is that two input ends of the delay extraction unit respectively receive a pulse signal X and another path of pulse signal Y, and a logic expression of an output signal of the delay extraction unit is as follows:
the larger the time delay between the pulse signal X and the other pulse signal Y is, the larger the pulse intensity of the output signal OUT of the time delay extraction unit is.
The invention has the further improvement that the time delay extraction unit comprises an NMOS tube and a PMOS tube; the source electrode of the PMOS tube receives a pulse signal X, the grid electrodes of the PMOS tube and the NMOS tube receive a pulse signal Y, and the drain electrodes of the PMOS tube and the NMOS tube are connected together to serve as the output end of the time delay extraction unit; and the source electrode of the NMOS tube is grounded.
In a further improvement of the present invention, the variable gain delay amplifying circuit includes two RS latches; the reset ends of the two RS latches are connected with the output end of one path of self-adaptive pulse shrinking circuit, and the set ends of the two RS latches are connected with the output end of the other path of self-adaptive pulse shrinking circuit; a set end of the RS latch is connected with a delay unit T in seriesoffThe reset end of the other RS latch is connected with a delay unit T in seriesoff(ii) a And two output ends of the RS latch are connected with an exclusive-OR gate and used for generating an output pulse signal.
A further improvement of the invention is that each output of the RS latch is connected to a gain control unit; the gain control unit is used for adjusting the gain of the variable gain delay amplifying circuit by controlling the output capacitance of each output end of the RS latch.
A further development of the invention is that the gain control unit comprises a plurality of capacitors; the capacitor is connected with one output end of the RS latch through a switch connected in series; and the switch of each capacitor is controlled by a register respectively, and the output capacitor of each RS latch is adjusted by configuring the numerical value of each register.
The invention has the further improvement that each capacitor is built by adopting an MOS tube.
Compared with the prior art, the invention has the following beneficial effects:
1. the delay amplifier provided by the invention has the advantages of simple structure, controllable gain and strong stability;
2. the delay amplifier provided by the invention is based on the metastable state principle of the SR latch, is improved aiming at the problem of small linear interval, adopts a mode of preprocessing input by a double-path self-adaptive pulse contraction unit, improves the linear interval and dynamic gain, and has controllable gain;
3. the time delay amplifier provided by the invention has a larger linear interval relative to a time unit, does not need a large time unit, and has better performance of resisting PVT fluctuation relative to other amplifiers.
Drawings
Other features, objects and advantages of the invention will become more apparent upon reading of the detailed description of non-limiting embodiments with reference to the following drawings:
FIG. 1 is a basic delay amplifier schematic;
FIG. 2 is a block diagram of the delay amplifier of the present invention;
FIG. 3 is a schematic diagram of a two-way adaptive pulse-shrinking circuit;
FIG. 4 is a schematic diagram of an adaptive pinch control bypass;
FIG. 5 is a schematic diagram of a variable gain amplification circuit;
FIG. 6 is a timing diagram of the output signal of the delay amplifier of the present invention;
FIG. 7 is a simulation diagram of a pulse puncturing unit;
fig. 8 is a comparison graph of the whole structure simulation.
Detailed Description
The present invention will be described in detail with reference to specific examples. The following examples will assist those skilled in the art in further understanding the invention, but are not intended to limit the invention in any way. It should be noted that it would be obvious to those skilled in the art that various changes and modifications can be made without departing from the spirit of the invention. All falling within the scope of the present invention.
As shown in fig. 2, the present invention provides an adaptive variable gain delay amplifier, which includes a dual-path adaptive pulse shrinking circuit and a variable gain delay amplifying circuit. The two-way self-adaptive pulse contraction circuit is used for receiving two-way pulse signals IN1 and IN2, and contracting the time delay between the two-way pulse signals when the time delay of the two-way pulse signals is larger than a threshold value, so that the time delay of the two-way pulse signals is adaptive to the input variable range of the variable gain time delay amplifying circuit. The variable gain time-delay amplifying circuit amplifies the time delay of the two-way pulse signals output by the two-way self-adaptive pulse shrinking circuit based on the metastable state effect of the RS latch and outputs two-way time-delay amplified pulse signals OUT1 and OUT 2. The flexibility and the stability of the amplifier can be improved by the combination mode of the double-path self-adaptive pulse shrinking circuit and the variable gain time-delay amplifying circuit.
As shown in fig. 2 and 6, the input/output timing of the adaptive variable gain delay amplifier is: the two-way self-adaptive pulse contraction circuit is used for receiving two-way pulse signals IN1 and IN 2; the rising edge of the two pulse signals is delayed by TinAfter the variable gain time-delay amplifying circuit carries out time-delay amplification on the two paths of pulse signals, the time-delay amplification of the output two paths of rising edges is ToutThe two pulse signals OUT1 and OUT 2.
The variable gain time-delay amplifying circuit is based on the RS latch, has the problem of small linear interval, adopts the two-way self-adaptive pulse contraction circuit and the variable gain amplifying circuit to realize the quantitative contraction and gain control of the pulse so as to improve the linearity and gain controllability of the amplifying interval, and has better PVT (voltage-to-current) fluctuation resistance compared with other amplifiers because the linear interval is larger than a time unit.
As shown in fig. 5, in the present embodiment, the variable gain delay amplifying circuit includes two RS latches. The reset ends of the two RS latches are connected with the output end of the adaptive pulse shrinking circuit, and the two RS latchesThe setting end of the device is connected with the output end of the other path of self-adaptive pulse contraction circuit; a set end of the RS latch is connected with a delay unit T in seriesoffThe reset end of the other RS latch is connected in series with a delay unit Toff. Two output ends of the RS latch are connected with an exclusive-OR gate and used for generating an output pulse signal.
The principle of the variable gain delay amplifying circuit is described below with reference to the accompanying drawings:
FIG. 1 shows a basic delay amplifier schematic based on the meta-stable structure of symmetric SR latches. The SR latch and the xor gate constitute the basic structure of the amplifier. If the rising edge acts on both the S and R ports of the latch (IN 1, IN2 IN FIG. 1) at approximately the same time, the SR latch will be meta-stable. When both inputs reach high level, the initial voltage of the SR latch output is proportional to the initial delay difference of the inputs, and the final output is 1 or 0. The SR latch outputs a voltage difference that is,
A(t)＝A(0)·et/τ
A(0)＝α·ΔTSR
where alpha is a scale factor, tau is a recovery time constant, C is the output capacitance of the NAND gate, gmIs the transconductance of the nand gate. When the difference in the output voltages of the latches reaches a threshold voltage, the XOR gate switches to 1, indicating that recovery from the metastable state is complete. When the time difference between the two inputs becomes short, the SR latch takes longer to recover. The recovery time is a logarithmic function of the edge difference. When the threshold value is reached (i.e. A (t)) a threshold V is reachedTHDiscrimination can be achieved by an exclusive or gate), meaning that a steady state is restored, and the time for the circuit to restore the steady state is inversely related to the SR two-port input interval.
ΔTOUT＝τ·(ln(VTH)-ln(|α·ΔTSR|))
Adding a bias to one of the two inputs in the SR latch quantitatively changes the delay amplifier propagation characteristics. Although the entire delay amplification is nonlinear, the region near the zero point may be regarded as one TA. The final TA equation is derived as follows:
Tout＝τ[log(Toff+Tin)-log(Toff-Tin)]
wherein A isTFor small signal gain, gmIs the metastable transconductance of the NAND gate, and C is the output capacitance. Both gain and linear range may be passed by the time offset ToffTo control.
The above is the principle of the basic delay amplifier. As shown in fig. 5, in the embodiment of the present invention, in order to adjust the gain of the delay amplifier, each output terminal of the RS latch is connected to the gain control unit; the gain control unit adjusts the gain of the variable gain delay amplifying circuit by controlling the output capacitance of each output end of the RS latch.
As shown in fig. 5(b), in order to realize gain control, the gain control unit includes a plurality of capacitors; the capacitor is connected with one output end of the RS latch through a switch connected in series; each output end of the RS latch is connected with at least one capacitor. The switches of the capacitors are respectively controlled by the registers, and the output capacitors of the RS latches are adjusted by configuring the numerical values of the registers, so that the output delay of the SR latches is adjusted.
The capacitor bank is connected with the output end of the SR latch in parallel, and the number of the connected capacitors in the capacitor bank can be adjusted, so that capacitance values with different sizes are connected in parallel, and different control accuracies are realized. The switch control circuit is composed of a multi-bit control register, and the size of a control value can be modified. The gain of the time delay amplifying circuit is changed by modifying the value of the control register so as to change the size of the accessed parallel capacitor, thereby realizing the controllable gain. The value of the register is configured through the Ctrl signal terminal. As shown in fig. 5(b), in the specific implementation of the capacitor, one example is implemented by using a MOS transistor to reduce layout area and process deviation.
In order to solve the problem of small linear range, a two-way adaptive pulse shrinking circuit is introduced in the embodiment, and the principle of solving the problem of small linear range is as follows:
the fundamental reason for the small linearity range of the basic SR-latch based latches is the gain error introduced by the truncation of the high order terms. If the input is delayed by Tin＜＜ToffThe gain error does not increase much, but often this limitation reduces the amplification. Therefore, the magnification factor is formulated in
The point spread is obtained by spreading out the points,
t relaxation by Taylor expansioninAnd ToffFar greater than the limit, we only require T when considering only cubic termsin 5＜＜Toff 5And (4) finishing. When stipulating
Equivalent Tin 5＜＜Toff 5As long as it satisfies
And (4) finishing. Theoretically, when T is compared with the basic SR-latch structure delay amplifieroffMeanwhile, the measuring range can be improved by 6 times; with the same equivalent weight range, ToffThe reduction of (A) is 16%. Therefore, the TA magnification is stabilized by correcting the third order.
Looking for f (T)in) So as to realize the pretreatment of the time delay and meet the requirement,
f(Tin)·Atagal T reality＝Tin·AT ideal
f(Tin)＝Tin+ΔT
Will f (T)in) Substituting T by substitutingin，
To satisfy the relation with TinThe first order functional relationship of (a), if desired,
Toff 2ΔT+(Tin+ΔT)3＝0
the repair of the cubic terms can be guaranteed to be completed by satisfying the formula. The principle of solving the problem of small linear interval by adopting the self-adaptive pulse shrinking circuit is adopted.
In order to realize the function, the two paths of adaptive pulse shrinking circuits are of a symmetrical structure, and each path of adaptive pulse shrinking circuit comprises an inverter chain and a plurality of time delay extraction units. The inverter chain is used for receiving a path of pulse signal X. The output end of the time delay extraction unit is connected with the control end of a discharge circuit; the discharge circuit is connected to an input of one of the inverters of the chain of inverters. The delay extraction unit is used for judging whether the delay between the pulse signal X received by the inverter chain and the other path of pulse signal Y is larger than a threshold value or not, and controlling the discharge circuit to discharge the input capacitor of the inverter connected with the discharge circuit when the delay is larger than the threshold value, so that the propagation speed of the pulse signal X is reduced.
The discharging circuit comprises a transistor, the grid electrode of the transistor is connected with the output end of the delay extraction unit, one electrode of the other two electrodes of the transistor is connected with the input end of the inverter, and the other electrode of the transistor is grounded. In one embodiment, the discharge circuit is implemented as an NMOS transistor with its source connected to ground and its drain connected to the input of an inverter. When the pulse strength output by the delay extraction unit is greater than the conduction threshold of the transistor of the discharge circuit, the transistor is conducted, so that the input capacitor of the inverter is discharged.
In each path of adaptive pulse shrinking circuit, two input ends of the delay extraction unit respectively receive a pulse signal X (the pulse signal received by the path of adaptive pulse shrinking circuit) and another pulse signal Y (the pulse signal received by the other path of adaptive pulse shrinking circuit). The logic expression of the output signal of the delay extraction unit is as follows:
the larger the time delay between the pulse signal X and the other pulse signal Y is, the larger the pulse intensity of the output signal OUT of the time delay extraction unit is.
As shown in fig. 4(b), the implementation manner of the delay extraction unit is: the time delay extraction unit comprises an NMOS tube and a PMOS tube. The source electrode of the PMOS tube receives a pulse signal X, the grid electrodes of the PMOS tube and the NMOS tube receive a pulse signal Y, and the drain electrodes of the PMOS tube and the NMOS tube are connected together to serve as the output end of the delay extraction unit; the source electrode of the NMOS tube is grounded.
The logic expression of the circuit implementation is
The expression is a biased exclusive or expression. Adaptive pulse shrinking circuitWhen the rising edge of the received pulse signal X is earlier than that of the other pulse signal Y, the delay extraction unit theoretically outputs a high level. However, because the transistor has a conducting process, the strength of the pulse signal output by the delay extraction unit is positively correlated with the delay between the pulse signal X and the other pulse signal Y.
As shown in FIG. 4(c), the pulse signal X leads the delay T of the other pulse signal YinThe larger the pulse output by the delay extraction unit is, the stronger the pulse output by the delay extraction unit is. Time delay TinGreater than TSTARTWhen the amplitude of the output pulse signal is larger than VT，VTIs the turn-on threshold of the transistor of the discharge circuit. Thus, TSTARTIn order to self-adaptive pulse contraction circuit to begin to scale the delayed threshold value, the delay between the pulse signal X and the other pulse signal Y is greater than TSTARTAnd when the adaptive pulse contraction circuit is used, the two paths of pulse signals are delayed and contracted.
The following is a quantitative analysis of the shrinkage process of the two-way adaptive pulse shrinkage circuit. In general, the shrinking of pulses by the inverter chain can be achieved in two ways: (1) slowing down the charging speed of the PMOS and reducing the size of the PMOS; (2) the discharge speed of the NMOS is increased, and the size of the NMOS is increased. Pulse broadening can be achieved in two ways: the charging speed of the PMOS is increased, and the size of the PMOS is increased; and the discharge speed of the NMOS is slowed down, and the size of the NMOS is reduced. The rising edge steepness of the output waveform of the middle stage is directly changed by changing the size of the PMOS, and the falling edge steepness of the output waveform of the middle stage is directly changed by changing the size of the NMOS. The specific theoretical calculation is as follows, CiIs the input capacitance of the inverter of the ith stage,
ΔT1＝tpLH1-tpHL1
ΔT2＝tpLH2-tpHL2
hypothesis-VTp＝VTn，
C1＝C3
Theoretical analysis of adaptive control will be described in detail later. Two-way adaptive pulse shrinking circuit for realizing T-input delay for each timeinThe output is the time delay after contraction, and the time delay is input to the controllable gain time delay amplifying circuit.
Fig. 4 is an adaptive control bypass schematic. The delay extraction unit is an asymmetric exclusive-or subunit, as shown in fig. 4(b),
only the rising edge of the input waveform is extracted with a delay. Delay T for different inputsinThe input delay is used for controlling the starting of the discharge circuit to realize the discharge of the input capacitor of a certain inverter in the inverter chain, and the process is equivalent to dynamically changing the PMOS size of the corresponding inverter in the inverter chain. When T isinWhen the voltage is smaller, the output amplitude and the level duration of the delay extraction unit are very small, the discharge circuit cannot be started, and the rising and falling edges of the waveform in the inverter chain cannot be changed. When T isinWhen the voltage is gradually increased, the output voltage and the level duration of the delay extraction unit are gradually increased, the discharge circuit is gradually started, the charging current of the inverter chain is discharged through the discharge circuit, the waveform rising and falling edge duration is increased, and the change amount is along with TinAnd increased by an increase. Analyzing the node a in conjunction with fig. 4(a), the specific derivation is as follows,
IC＝IP-IN
at [0, Δ trise]Within the interval, INThe current is only in the pulse width gamma TinInner significant, gamma is a proportionality coefficient, although T may occurin＞ΔtriseBut the true valid input is only gamma Tin. Provision of INNot following TinChange, actually with TinIncrease of (A) to (B), INAnd (4) increasing. Δ triseInvariably, will actually follow TinIncreases but slightly increases. It can be seen that with TinThe charging current of the capacitor C is gradually reduced until convergence, and the equivalent charging current I of the PMOS is increasedPequTrend of change and capacitor charging current ICavrgThe trend of the change is the same. In the charging process, the PMOS tube can be considered to work in a saturation region, and the equivalent width W of the PMOS tubePequWith the pulse width TinIncreasing and decreasing until convergence. FIG. 4(c) is the inherent transfer function curve of the delay extraction unit, output V of the delay extraction unitOUTAnd TinThe mathematical relationship of (a) can only be obtained by actual measurement. Only VOUT＞VTThen the NMOS transistor is turned on, VTCorresponding input TSTARTThe moment of action for the opening of the retraction unit. When V isOUT＝VDDWhen the shrinkage is not changed, the shrinkage of the shrinkage unit is not changed. I isNThe variations of (c) can be summarized as: with TinIncrease of (A) to (B), INGradually increases and gradually converges and stabilizes. When T isin＜TTHWhen, VOUT＝0，IPequIs substantially unchanged; when T isTH＜Tin＜TSTARTWhen, VOUTWith TinIncreasing gradually, due to the sub-threshold property of the MOS transistor, IPequIs gradually decreased, WPequGradually decrease; when T isin＞TSTARTWhen, VOUTWith TinThe increase gradually increases and gradually converges to VDD，IPequGradually decrease and converge, WPequGradually decreases and converges. Thus, with input delay TinDynamically controlling the turn-on of the discharge circuit equivalently to dynamically varying the PMOS width Wp2。
Fig. 7 is a simulation diagram of an adaptive pulse puncturing circuit, for a range of [ -36ps, 36ps ], fig. 7(a) compares the actual puncturing output with the theoretical puncturing output, and fig. 7(b) compares the puncturing error.
FIG. 8 is a comparison graph of simulation of the overall structure, wherein the results are labeled as the simulation results of the adaptive variable gain delay amplifier of the present invention after optimization, and the simulation results are basically based on SR-latch delay amplifier before optimization. Fig. 8(a) shows the input-gain simulation result, fig. 8(b) shows the input ← gain error simulation result, and fig. 8(c) shows the input ← gain error simulation result, and output simulation result. For the range of [ -36ps, 36ps ], the gain can be stable in the interval, and the gain error is small.
In the description of the present application, it is to be understood that the terms "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", and the like indicate orientations or positional relationships based on those shown in the drawings, and are only for convenience in describing the present application and simplifying the description, but do not indicate or imply that the referred device or element must have a specific orientation, be constructed in a specific orientation, and be operated, and thus, should not be construed as limiting the present application.
The foregoing description of specific embodiments of the present invention has been presented. It is to be understood that the present invention is not limited to the specific embodiments described above, and that various changes or modifications may be made by one skilled in the art within the scope of the appended claims without departing from the spirit of the invention. The embodiments and features of the embodiments of the present application may be combined with each other arbitrarily without conflict.
Claims (8)
1. An adaptive variable gain delay amplifier, comprising:
the two-path self-adaptive pulse contraction circuit is used for receiving the two paths of pulse signals and contracting the time delay between the two paths of pulse signals when the time delay of the two paths of pulse signals is greater than a threshold value, so that the time delay of the two paths of pulse signals is adaptive to the input variable range of the variable gain time delay amplifying circuit;
the variable gain time-delay amplifying circuit is used for amplifying the time delay of the two-way pulse signal output by the two-way self-adaptive pulse shrinking circuit based on the metastable state effect of the RS latch;
each path of the self-adaptive pulse shrinking circuit comprises an inverter chain and a plurality of time delay extraction units;
the inverter chain is used for receiving a path of pulse signal X;
the output end of the delay extraction unit is connected with the control end of a discharge circuit; the discharge circuit is connected with the input end of one inverter in the inverter chain;
the delay extraction unit is used for judging whether the delay between the pulse signal X received by the phase inverter chain and the other path of pulse signal Y is larger than a threshold value or not, and controlling the discharge circuit to discharge the input capacitor of the phase inverter connected with the discharge circuit when the delay is larger than the threshold value, so that the propagation speed of the pulse signal X is reduced.
2. An adaptive variable gain delay amplifier according to claim 1, wherein the discharge circuit comprises a transistor, a gate of the transistor is connected to the output terminal of the delay extraction unit, the other two poles of the transistor are connected to the input terminal of the inverter, and the other pole of the transistor is grounded; when the pulse strength output by the delay extraction unit is greater than the conduction threshold of the transistor, the transistor is conducted, so that the input capacitor of the inverter is discharged.
3. The adaptive variable gain delay amplifier of claim 2, wherein two input terminals of the delay extraction unit respectively receive the pulse signal X and the other pulse signal Y, and a logic expression of an output signal of the delay extraction unit is:
the larger the time delay between the pulse signal X and the other pulse signal Y is, the larger the pulse intensity of the output signal OUT of the time delay extraction unit is.
4. The adaptive variable gain delay amplifier of claim 2, wherein the delay extraction unit comprises an NMOS transistor and a PMOS transistor; the source electrode of the PMOS tube receives a pulse signal X, the grid electrodes of the PMOS tube and the NMOS tube receive a pulse signal Y, and the drain electrodes of the PMOS tube and the NMOS tube are connected together to serve as the output end of the time delay extraction unit; and the source electrode of the NMOS tube is grounded.
5. An adaptive variable gain delay amplifier according to claim 1, wherein the variable gain delay amplifying circuit comprises two RS latches; the reset ends of the two RS latches are connected with the output end of one path of self-adaptive pulse shrinking circuit, and the set ends of the two RS latches are connected with the output end of the other path of self-adaptive pulse shrinking circuit; a set end of the RS latch is connected with a delay unit T in seriesoffThe reset end of the other RS latch is connected with a delay unit T in seriesoff(ii) a And two output ends of the RS latch are connected with an exclusive-OR gate and used for generating an output pulse signal.
6. An adaptive variable gain delay amplifier according to claim 5, wherein each output of the RS latch is connected to a gain control unit; the gain control unit is used for adjusting the gain of the variable gain delay amplifying circuit by controlling the output capacitance of each output end of the RS latch.
7. An adaptive variable gain delay amplifier as claimed in claim 6, wherein said gain control unit comprises a plurality of capacitors; the capacitor is connected with one output end of the RS latch through a switch connected in series; and the switch of each capacitor is controlled by a register respectively, and the output capacitor of each RS latch is adjusted by configuring the numerical value of each register.
8. An adaptive variable gain delay amplifier according to claim 7, wherein each of the capacitors is built with a MOS transistor.
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