DE602007007300D1 - DEVICES WITH A DELAYING LINE FOR APPLYING A VARIABLE DELAY TO A CLOCK SIGNAL - Google Patents

DEVICES WITH A DELAYING LINE FOR APPLYING A VARIABLE DELAY TO A CLOCK SIGNAL

Info

Publication number
DE602007007300D1
DE602007007300D1 DE602007007300T DE602007007300T DE602007007300D1 DE 602007007300 D1 DE602007007300 D1 DE 602007007300D1 DE 602007007300 T DE602007007300 T DE 602007007300T DE 602007007300 T DE602007007300 T DE 602007007300T DE 602007007300 D1 DE602007007300 D1 DE 602007007300D1
Authority
DE
Germany
Prior art keywords
delay
clock signal
devices
banks
controller
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
DE602007007300T
Other languages
German (de)
Inventor
Mustafa Badaroglu
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Interuniversitair Microelektronica Centrum vzw IMEC
Original Assignee
Interuniversitair Microelektronica Centrum vzw IMEC
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Interuniversitair Microelektronica Centrum vzw IMEC filed Critical Interuniversitair Microelektronica Centrum vzw IMEC
Publication of DE602007007300D1 publication Critical patent/DE602007007300D1/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
    • H03K5/131—Digitally controlled
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
    • H03K5/133—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals using a chain of active delay devices
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K7/00—Modulating pulses with a continuously-variable modulating signal
    • H03K7/04—Position modulation, i.e. PPM
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
    • H04B1/69—Spread spectrum techniques
    • H04B1/7163—Spread spectrum techniques using impulse radio
    • H04B1/7183—Synchronisation

Abstract

The disclosure relates to a device comprising at least one delay line for applying a variable delay to a clock signal and a controller for controlling the variable delay of the delay line. Each delay line comprises a plurality of concatenated delay banks which provide different delay values with respect to each other, a bypass parallel over each of said the delay banks, and switching elements associated with each of the delay banks for selecting either the respective delay bank or the respective bypass. Each of the delay banks is provided with a delay bank status indicator for indicating propagation of the clock signal through the delay bank towards the controller. The controller is provided for taking the indicated propagation of the clock signal into account upon setting said switching elements. Devices according to this disclosure are, amongst other uses, suited for use in Ultra Wide Band (UWB) receiving or transmitting devices, in particular those devices, designed for low power consumption, by enabling power on and off switching of parts of such devices as analog to digital converters and integrators, during timing windows.
DE602007007300T 2006-02-03 2007-02-02 DEVICES WITH A DELAYING LINE FOR APPLYING A VARIABLE DELAY TO A CLOCK SIGNAL Active DE602007007300D1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
EP06101272 2006-02-03
PCT/EP2007/051052 WO2007088211A1 (en) 2006-02-03 2007-02-02 Devices comprising delay line for applying variable delay to clock signal

Publications (1)

Publication Number Publication Date
DE602007007300D1 true DE602007007300D1 (en) 2010-08-05

Family

ID=38042504

Family Applications (1)

Application Number Title Priority Date Filing Date
DE602007007300T Active DE602007007300D1 (en) 2006-02-03 2007-02-02 DEVICES WITH A DELAYING LINE FOR APPLYING A VARIABLE DELAY TO A CLOCK SIGNAL

Country Status (6)

Country Link
US (1) US8233579B2 (en)
EP (1) EP1987589B1 (en)
JP (1) JP5090371B2 (en)
AT (1) ATE472194T1 (en)
DE (1) DE602007007300D1 (en)
WO (1) WO2007088211A1 (en)

Families Citing this family (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4695021B2 (en) * 2006-06-05 2011-06-08 富士通株式会社 Impulse radio equipment
JP4350133B2 (en) * 2007-02-19 2009-10-21 富士通株式会社 Transmission circuit and wireless transmission device
FR2941113B1 (en) * 2009-01-15 2011-03-11 St Microelectronics Grenoble 2 METHOD FOR DETECTING THE LATCHING OF A PHASE LOCKED LOOP AND ASSOCIATED DEVICE
KR101115474B1 (en) 2009-03-30 2012-02-27 주식회사 하이닉스반도체 Delay circuit
KR101053523B1 (en) * 2009-05-08 2011-08-03 주식회사 하이닉스반도체 Delay device of semiconductor integrated circuit and its control method
EP2429089A1 (en) * 2010-09-08 2012-03-14 Fraunhofer-Gesellschaft zur Förderung der Angewandten Forschung e.V. Receiver and method for determining a time measure depending on a time of arrival of a pulse signal
GB201015729D0 (en) 2010-09-20 2010-10-27 Novelda As Pulse generator
GB201015730D0 (en) * 2010-09-20 2010-10-27 Novelda As Continuous time cross-correlator
US9143140B2 (en) 2011-02-15 2015-09-22 Cavium, Inc. Multi-function delay locked loop
US8682181B2 (en) * 2011-03-05 2014-03-25 Alcatel Lucent System, method, and apparatus for high-sensitivity optical detection
US8698670B2 (en) * 2011-06-01 2014-04-15 Panasonic Corporation High speed high resolution wide range low power analog correlator and radar sensor
US8547154B2 (en) * 2011-06-22 2013-10-01 International Business Machines Corporation Programmable duty cycle selection using incremental pulse widths
US8576116B2 (en) * 2011-10-20 2013-11-05 Panasonic Corporation High speed high resolution wide range low power analog correlator and radar sensor
TWI451700B (en) * 2011-12-05 2014-09-01 Global Unichip Corp Clock and data recovery circuit
US9281034B2 (en) 2013-10-03 2016-03-08 Cavium, Inc. Data strobe generation
KR102528561B1 (en) * 2018-05-09 2023-05-04 삼성전자주식회사 Apparatus and method for generating clock
CN111669137B (en) * 2020-04-27 2022-02-11 上海交通大学 Self-adaptive variable gain delay amplifier

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US622407A (en) * 1899-04-04 Hen s nest
JP3378667B2 (en) * 1994-08-10 2003-02-17 株式会社アドバンテスト Variable delay circuit for periodic clock
JPH0854957A (en) * 1994-08-12 1996-02-27 Hitachi Ltd Clock distribution system
KR100295052B1 (en) * 1998-09-02 2001-07-12 윤종용 Delay locked loop including a controller capable of changing a number of unit delay in voltage controlled delay line
US6222407B1 (en) * 1999-03-05 2001-04-24 International Business Machines Corporation Dual mode programmable delay element
JP3605033B2 (en) * 2000-11-21 2004-12-22 Ｎｅｃエレクトロニクス株式会社 Fixed-length delay generation circuit
US6605969B2 (en) * 2001-10-09 2003-08-12 Micron Technology, Inc. Method and circuit for adjusting the timing of ouput data based on an operational mode of output drivers
JP2004192202A (en) * 2002-12-10 2004-07-08 Konica Minolta Holdings Inc Clock signal distributing circuit and semiconductor integrated circuit
US7234069B1 (en) * 2004-03-12 2007-06-19 Altera Corporation Precise phase shifting using a DLL controlled, multi-stage delay chain

Also Published As

Publication number Publication date
EP1987589B1 (en) 2010-06-23
JP2009525649A (en) 2009-07-09
US8233579B2 (en) 2012-07-31
JP5090371B2 (en) 2012-12-05
WO2007088211A1 (en) 2007-08-09
US20100225369A1 (en) 2010-09-09
EP1987589A1 (en) 2008-11-05
ATE472194T1 (en) 2010-07-15

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