JPH0854957A - Clock distribution system - Google Patents

Abstract

PURPOSE:To surely guarantee the equal time property by a clock signal while securing the degree of freedom on the arrangement of a circuit receiving the line laying of a transmission line and the distribution of the clock signal and suppressing the line laying amount of the transmission line to a minimum. CONSTITUTION:A single line circulating route Lo is formed by two sets of transmission lines L1 and L2 which are parallel with each other, the clock signals of the same phase are transmitted in the opposite directions each other from a fixed position of this circulating route Lo, plural clock reception parts 2 are arranged at arbitrary portions on the circulating route, and the clock signal where the middle point between the changed point of the reception clock signal from the transmission line of one side and the changed point of the reception clock signal from the transmission line of the other side is defined as a timing reference is generated every reception part 2. Thus, the transmission lines L1 and L2 are capable of performing a simple line laying drawn by one stroke of a pen, regardless of the number and arrangement of the reception parts 2.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a technique effective when applied to a clock distribution system, and further to a high speed clock signal distribution system, for example, to a synchronous electronic device or system using a clock signal. It is related to effective technology.

[0002]

2. Description of the Related Art When a plurality of circuits are operated in synchronization, a clock signal having the same phase is distributed to each circuit so that the respective operation timings are the same, that is, so-called isochronism is guaranteed. However, for example, in a recent high-speed large-scale logic semiconductor integrated circuit device (LSI) or the like, when distributing a clock signal for synchronously operating the circuits of the respective parts, the transmission delay of the distribution cannot be ignored, and the clock is delayed. Guaranteeing isochronousness by signals is becoming difficult (for example, "Nikkei Electronics, February 18, 1991, no. 520", published by Nikkei BP 13
4 to 137: see Logic LSI).

Therefore, recently, in order to ensure the above-mentioned isochronism, as shown in FIG. 8, the transmission conditions for distributing the clock signals have been made uniform.

FIG. 8 shows a schematic configuration example of a conventional clock distribution system. In the figure, the clock signal φo output from the clock transmission unit 1 is the trunk transmission lines L10, L2.
It is distributed to the terminal circuit 3 from 0 through the branch line transmission lines L11 and L21. At this time, the clock transmission path lengths from the transmission unit 1 to each circuit 3 are made uniform. This allows
The timings of the clock signals φo in the circuits 3 can be aligned with each other by setting the transmission delay amounts from the transmitter 1 to the circuits 3 to the same conditions. That is, isochronism can be ensured.

[0005]

However, the present inventors have clarified that the above-mentioned technique has the following problems.

That is, in the above-described conventional clock distribution system, as shown in FIG. 8, the length of the main line transmission line L10 and the length of the branch line transmission line L20 are respectively set because it is necessary to ensure isochronism by the clock signal. Must have the same length.

For this reason, the clock signal transmission system is complicated by the trunk transmission line and the branch transmission line. Further, in order to make the lengths of the transmission lines the same, as indicated by the symbol dL in FIG. The waste of largely bypassing the transmission line may be inevitable. As a result, a problem arises in that the amount of cloth applied to the transmission line increases and the degree of freedom regarding the wiring of the transmission line and the arrangement of the circuit receiving the distribution of the clock signal is impaired.

It is an object of the present invention to secure the degree of freedom regarding the wiring of the transmission line and the arrangement of the circuit receiving the distribution of the clock signal without complicating the transmission system of the clock signal, and to minimize the amount of transmission line transmission. It is an object of the present invention to provide a technique for surely guaranteeing isochronousness by a clock signal while suppressing the limit.

The above and other objects and characteristics of the present invention will be apparent from the description of the present specification and the accompanying drawings.

[0010]

Of the inventions disclosed in the present application, a representative one will be briefly described below.
It is as follows.

That is, a single loop path is formed by two sets of transmission paths that are parallel to each other, and a clock transmission section is placed at a certain position of this loop path, and from this transmission section, the above-mentioned 2
While transmitting the clock signals of the same phase in opposite directions to the set of transmission lines, a plurality of clock receiving units are arranged at arbitrary positions on the loop path, and for each receiving unit,
A clock signal is generated with the midpoint between the change point of the received clock signal from one transmission line and the change point of the received clock signal from the other transmission line as a timing reference, and distributed to the circuits near the receiving unit. , Is.

[0012]

According to the above-described means, the sum of the transmission delay amounts of the clock signals received from the two sets of transmission lines is the same at any receiving position. Therefore, if the midpoint between the change point of the received clock signal from one transmission line and the change point of the received clock signal from the other transmission line is used as a reference, the clock with a constant timing is always generated regardless of the reception position. A signal can be generated. Further, the transmission path can be freely and shortly routed by so-called one-stroke writing regardless of the number and arrangement of the receiving units.

Thus, the degree of freedom regarding the wiring of the transmission line and the arrangement of the circuit receiving the distribution of the clock signal is ensured without complicating the transmission system of the clock signal, and the transmission dose of the transmission line is minimized. At the same time, the purpose of ensuring the isochronousness by the clock signal is achieved.

[0014]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT A preferred embodiment of the present invention will be described below with reference to the drawings. In the drawings, the same reference numerals denote the same or corresponding parts. FIG. 1 shows an embodiment of a clock distribution system to which the technique of the present invention is applied, in which 1 denotes clock signals φ1 and φ2 having the same phase.
, A clock transmission driver 11, 12 is a clock transmission driver, L1 and L2 are clock transmission lines, 2 is a clock reception unit, 3 is a circuit which operates in synchronization with a clock signal,
Z is a terminating resistor for impedance matching.

Here, the transmission lines L1 and L2 are wired in parallel with each other to form a single loop path Lo. One transmission line L1 has one end connected to the output of the one clock transmission driver 11 and the other end connected to the terminating resistor Z. The other transmission line L2, contrary to L1,
The output of one clock transmission driver 11 is connected to the other end, and the terminating resistor Z is connected to one end thereof. As a result, one clock signal φ1 is transmitted from one end of the circulation path Lo to the other end, and the other clock signal φ2 is transmitted from the other end of the circulation path Lo to one end. There is. That is, the transmission driver 1
Clock signals φ1 and φ of the same phase at the output points of 1 and 12
2 is transmitted to the two sets of transmission lines L1 and L2 in opposite directions.

The clock receiving section 2 is arranged at arbitrary points A, B and C of the loop path Lo, and each receiving section 2 receives a clock signal φ1 received from one transmission line L1.
Change point and the clock signal φ received from the other transmission line
A clock signal is generated with the midpoint between the two change points as a timing reference, and this is distributed to the circuit 3 near the receiving unit.

FIG. 2 shows a concrete embodiment of the clock receiving section 2. The clock receiving unit 2 shown in the figure includes two variable delay circuits 21 and 22 which are variably controlled in conjunction with each other so as to have the same delay amount, and delays of the variable delay circuits 21 and 22. It is composed of a phase comparison circuit 23 for feedback controlling the quantity.

Here, the two variable delay circuits 21 and 22 are connected in multiple stages in series and sequentially delay-transmit the clock signal φ1 received from one transmission line L1. Phase comparison circuit 23
Detects a phase difference between the clock signal φd sequentially delayed and transmitted by the two variable delay circuits 21 and 22 and the clock signal φ2 received from the other transmission line L1, and the detected phase difference is zero. So that the above two variable delay circuits 2
A phase control loop that changes the delay amounts of 1 and 22 while interlocking with each other is formed. Then, under this phase control loop, the clock signal φd taken out from the intermediate point of the two variable delay circuits 21 and 22 is output and distributed to the circuit 3 in the vicinity.

It is assumed that one clock signal φ1 input to the variable delay circuits 21 and 22 has a smaller delay amount than the other clock signal φ2. That is, the clock signal φ1 transmitted from the transmission path having the shorter transmission distance from the transmission unit 1 is delayed and transmitted by the variable delay circuits 21 and 22 so as to be subjected to the phase comparison. Therefore, if the transmission distance of the clock φ2 is shorter, that clock φ2
Is input to the variable delay circuits 21 and 22 and delayed and transmitted.

FIG. 3 is a waveform chart showing an operation example when the clock receiving unit 2 shown in FIG. 2 is used in the clock distribution system shown in FIG. In the figure, (A) shows clock signals φ1, φ2 received at point A of the loop path Lo shown in FIG. 1, and (B) shows clock signals φ1, φ2 received at point B of the same path Lo. (C) shows clock signals φ1 and φ2 received at point C of the same path Lo, respectively. As shown in (A), (B), and (C) of FIG. 6, the clock signals φ1 and φ2 received at any point of the loop path Lo are transmitted by the transmission delay amount Tpd from the transmission unit 1.
The sum of 1 and Tpd2 is constant. This is because the sum of the transmission distance of one clock signal φ1 and the transmission distance of the other clock signal φ2 is always the total length of the loop path Lo.

Therefore, in the clock receiving section 2 shown in FIG. 2, two variable delays are set so that the delay amount of one reception clock signal φ1 becomes the same as the delay amount of the other reception clock signal φ2 at the time of reception. By performing feedback control of the delay amounts of the circuits 21 and 22 by the detection output of the phase detection circuit 23, the delay amounts (2 × tdx) of the two variable delay circuits 21 and 22 are the two reception clock signals φ1 and φ2. Is the difference (| Tpd2-Tpd1 |) between the reception delay amounts Tpd1 and Tpd2. Here, the two variable delay circuits 21 and 22 have the same delay amount (td
x) so that it is variably controlled in conjunction,
From the intermediate point of the two variable delay circuits 21 and 22, it is possible to take out the clock signal φm which constantly changes at the same timing at any of the receiving points A, B and C.

That is, since the sum of the transmission distance of one clock signal φ1 and the transmission distance of the other clock signal φ2 is always the total length of the loop path Lo, the delay amount Tpd1 of one reception clock signal φ1 and the reception amount of the other reception clock signal φ1. Clock signal φ2
The sum (| Tpd2 + Tpd1 |) of the delay amount Tpd2 of
The same applies to any of the receiving points A, B, and C on the loop route Lo. Therefore, as shown in FIG. 3, the midpoint between the change point of one reception clock signal φ1 and the change point of the other reception clock signal φ2 is at any reception point A, B, C on the loop path Lo. Will be the same. The midpoint timing of these two reception clock signals φ1 and φ2 is shown in FIG.
, The two receive clock signals φ1 and φ2
Of the reception delay amounts Tpd1 and Tpd2 (| Tpd2-T
pd1 |) becomes exactly half (| Tpd2-Tp
d1 | / 2).

In this way, the clock signal φm with the timing reference being the midpoint between the changing point of the reception clock signal φ1 from one transmission line L1 and the changing point of the reception clock signal φ2 from the other transmission line. There are two variable delay circuits 2
It is taken out from the intermediate connection point of 1 and 22 and distributed to the circuit 3 near the receiving section.

FIG. 4 shows a concrete embodiment of the variable delay circuits 21 and 22. In this case, only one (21) of the two variable delay circuits 21 and 22 is shown in the figure, but the other (22) is also configured in the same manner. The variable delay circuit 21 shown in the figure is a delay circuit array 21 in which a large number of unit delay circuits each including an inverter and a capacitor are connected in series in multiple stages.
1. A switch circuit array 212 that variably controls the number of multi-stage connection stages of the unit delay circuits in the delay circuit array 211, and a register 213 that variably controls the on / off state of each unit switch circuit in the switch circuit array 212. Then, the total delay amount in the delay circuit array 211 is variably controlled by variably setting the data value loaded in the register 213 based on the detection output of the phase comparison circuit 23 (FIG. 2).

As described above, the two sets of transmission lines L1 and L2 which are parallel to each other form a single loop path Lo, and the clock transmission section 1 is placed at a certain position of this loop path Lo. 1 to the above two sets of transmission lines L1 and L2
On the other hand, the clock signals φ1 and φ2 having the same phase are transmitted in opposite directions to each other, while a plurality of clock receivers 2 are arranged at arbitrary points A, B and C on the loop path Lo, and the points A, B and C are respectively arranged. One transmission line L for each receiving unit 2 of
A clock signal φm is generated with a timing reference at the midpoint between the change point of the reception clock signal φ1 from 1 and the change point of the reception clock signal φ2 from the other transmission line L2.
This is distributed to the circuit 3 in the vicinity of the receiving section for each of the points A, B, and C.

At this time, the transmission delay amount (Tpd) of the clock signals φ1 and φ2 received from the two sets of transmission lines L1 and L2.
The sum of (1, Tpd2) is the same in any of the receiving units A, B, C. Therefore, if the midpoint between the changing point of the clock signal φ1 received from the one transmission line L1 and the changing point of the clock signal φ2 received from the other transmission line is taken as a reference, the position of the receiving unit is irrelevant. Instead, the clock signal φm can always be generated at a constant timing.
Further, the transmission lines L1 and L2 can be freely and shortly wired by so-called one-stroke writing regardless of the number and positions of the receiving units 2.

Thus, the degree of freedom regarding the wiring of the transmission line and the arrangement of the circuit receiving the distribution of the clock signal can be secured without complicating the transmission system of the clock signal, and the dose of the transmission line can be minimized. It becomes possible to surely guarantee the isochronous property by the clock signal while suppressing.

FIG. 5 shows a further preferred embodiment of the invention described above. In the embodiment shown in the figure, the clock transmission unit 1
Are clock frequency sources f1 and f2 having different frequencies.
And a switch circuit S1 for switching and selecting the plurality of clock frequency sources f1 and f2. At the same time, when the detection output of the phase comparison detection circuit becomes zero in the phase control loops of all the clock receivers 2 arranged at arbitrary points A, B, and C on the loop path Lo, the switch circuit S1 is switched on. The clock frequency switching control means 4 is provided to change the clock frequency sources f1 and f2 from the lower one (f1) to the higher one (f2).

The above-mentioned configuration is effective in distributing a high-speed clock signal having a shorter cycle than the transmission delay time in the transmission lines L1 and L2. That is, when the transmission delay time in the transmission lines L1 and L2 becomes longer than the cycle of the clock signal, the midpoint of each change point of the two clock signals φ1 and φ2 received from the transmission lines L1 and L2 becomes the above-mentioned phase. The control loop may not be able to make the correct decision. That is, in the configurations shown in FIGS. 1 to 4, there is a frequency limit in the clock timing adjustment by the phase control loop.

However, according to the embodiment shown in FIG. 5, timing adjustment can be correctly performed even with a high-speed clock signal exceeding the frequency limit as described below. That is, first, with the lower clock frequency f1, the middle point between the two reception clock signals φ1 and φ2 is set in a state where the period of the clock signal is sufficiently longer than the transmission delay time in the frequency transmission lines L1 and L2. Make the right decision.
When this state is established, when the clock frequency is switched from the lower frequency (f1) to the higher frequency (f2), the timing adjusted by the lower frequency f1 is inherited as it is at the higher frequency f2. As a result, it is possible to correctly perform the timing adjustment even with a high-speed clock signal exceeding the frequency limit.

FIG. 6 shows another embodiment of the clock receiver 2. FIG. 7 shows an example of an operation waveform chart of the receiving section 2 shown in FIG. 6 and 7, the clock receiver 2
Are waveform shaping circuits 24 and 25 for blunting the rising waveform of the clock signal φ1 received from one transmission line L1 and the falling waveform of the clock signal φ2 received from the other transmission line L2 into a slope shape, respectively, and A level comparison circuit 2 for detecting a level crossing point between the rising waveform v1 of the clock signal received from the line L1 and the falling waveform v2 of the clock signal φ2 received from the other transmission line L2.
6 and outputs the clock signal φm with the level crossing point detected by the level comparison circuit 26 as the timing reference of the change point.

The clock signal φm obtained by using the receiving unit 2 of this embodiment is further delayed than the received clock signal (φ2) having the larger transmission delay amount, but the delay amount is one reception signal. The midpoint between the changing point of the clock signal φ1 and the changing point of the other received clock signal φ2 is used as a reference, and its timing is constant regardless of the position of the receiving section 2. Also, because it does not use the phase control loop,
It has the advantage of being relatively easy to configure.

Although the invention made by the present inventor has been specifically described based on the embodiments, the present invention is not limited to the above embodiments, and various modifications can be made without departing from the scope of the invention. Needless to say.

In the above description, the case where the invention made by the present inventor is mainly applied to the clock signal distribution system which is the field of application which is the background of the invention has been described. It can also be applied to a simultaneous transmission system of a specific code string that forms one cycle with a clock.

[0035]

The effects of the typical ones of the inventions disclosed in this application will be briefly described as follows.

That is, without complicating the clock signal transmission system, the degree of freedom regarding the wiring of the transmission line and the arrangement of the circuit receiving the distribution of the clock signal is secured, and the amount of transmission line transmission is minimized. In addition, it is possible to obtain the effect that the isochronous property of the clock signal can be surely guaranteed.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a first embodiment of a clock distribution system to which the technique of the present invention is applied.

FIG. 2 is a block diagram showing a configuration example of a clock receiving unit used in the present invention.

3 is a waveform chart showing an operation example of the clock receiving unit 2 shown in FIG.

4 is a block diagram showing a configuration example of a variable delay circuit used in the clock receiving unit shown in FIG.

FIG. 5 is a block diagram showing a second embodiment of the present invention.

FIG. 6 is a block diagram showing another configuration example of a clock receiving unit.

7 is a waveform chart showing an operation example of the receiving section 5 shown in FIG.

FIG. 8 is a circuit diagram showing an outline of a conventional clock distribution system.

[Explanation of symbols]

 1 Clock Transmission Unit 11, 12 Transmission Driver 2 Clock Reception Unit 21, 22 Variable Delay Circuit 23 Phase Comparison Circuit 24, 25 Waveform Shaping Circuit 26 Level Comparison Circuit L1, L2 Transmission Line Z Termination Resistor Lo Circular Path φ1, φ2 Received Clock Signal φm Clock signal whose isochronism is guaranteed 3 Circuit that operates synchronously with clock signal φm f1 Clock frequency source (low) f2 Clock frequency source (high) S1 switch circuit 4 Clock frequency control circuit

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI technical display location // H03K 5/13

Claims (4)

[Claims] 1. A single loop path is formed by two sets of transmission lines parallel to each other, and a clock transmission section is placed at a certain position of this loop path, and the transmission section is the same for the two sets of transmission paths. While transmitting phase clock signals in opposite directions, a plurality of clock receivers are placed at arbitrary points on the loop path, and each receiver receives a change point of the received clock signal from one transmission path. A clock distribution system, which generates a clock signal with a midpoint between a change point of a received clock signal from the other transmission line and a change point as a timing reference, and distributes the generated clock signal to a circuit in the vicinity of the receiving unit. 2. The clock receiving unit includes two variable delay circuits that sequentially delay-transmit a received clock signal from one transmission line in series, and the clock signals sequentially delayed and transmitted by the two variable delay circuits and the other. And a phase comparison circuit for detecting a phase difference between the received clock signal from the transmission line of
Under the phase control loop that varies the delay amounts of the two variable delay circuits while interlocking with each other so that the phase difference detected by the phase comparison circuit becomes zero, the variable delay circuits are extracted from the intermediate point of the two variable delay circuits. The clock distribution system according to claim 1, wherein the clock distribution system outputs a clock signal that is generated. 3. The clock transmission section comprises clock frequency switching means for changing the frequency of the clock signal transmitted to the two sets of transmission lines from a low frequency to a high frequency. The described clock distribution system. 4. The clock receiving section includes waveform shaping means for blunting a rising waveform of a reception clock signal from one transmission line and a falling waveform of a reception clock signal from the other transmission line in a slope shape, and The level comparison means for detecting a level crossing point between the rising waveform of the reception clock signal from the transmission line and the falling waveform of the reception clock signal from the other transmission line is provided, and the level crossing point detected by the level comparison means is detected. The clock signal is output with reference to the timing of the change point.
4. The clock distribution system according to any one of 3 to 3.