JPS63181515A - Automatic delay time adjusting system - Google Patents

Abstract

PURPOSE:To coincide the reaching time of a clock at both the reception ends of a reference transmission line and a transmission line to be adjusted by providing a return line whose propagation delay time is equal to that of a go line in both the reference transmission line and transmission line to be adjusted, detecting the time difference of pulses at the respective transmission ends and return ends, and controlling a variable delay circuit with the time difference. CONSTITUTION:The return line whose propagation delay time is equal to that of the go line are provided in both reference transmission line and transmission line to be adjusted and the time difference between pulses at the respective transmission ends A and D and return ends C and F is detected. And the detected time difference is converted into the voltage which is proportioned to the time difference at the reception ends B and E of the reference transmission line and the transmission line to be adjusted and a variable delay circuit 6 is controlled with the voltage. Thus, the delay time of the transmission line to be adjusted can be automatically adjusted in order that the reaching time of clocks at the reception ends B and E of the reference transmission line and the transmission line to be adjusted are made equal.

Description

[Detailed Description of the Invention] [Summary] A return path with equal propagation time as the outgoing path is provided on both the reference transmission line and the adjusted transmission line, and the time difference between the pulses at each sending end and return end is detected and calculated. By converting to a voltage proportional to the time difference at the receiving ends of the reference transmission line and the adjusted transmission line and controlling the variable delay circuit with this voltage, the arrival of the clock at the receiving ends of the reference transmission line and the adjusted transmission line is controlled. To automatically adjust the delay time of a transmission line to be adjusted so that time is lost.

[Industrial application field]

The present invention relates to an automatic delay time adjustment method, and particularly to a method for automatically adjusting delay time so that clocks arrive at two or more locations at the same time.

[Conventional technology]

The clock in a synchronous logic circuit is generated in one place,
The clock must arrive at the same time to multiple circuits that use it. However, this is because the distances from the clock generation circuit to each clock usage circuit and the propagation speeds of the transmission paths are not equal.

You need to adjust the delay time in some way.

The conventional delay time adjustment method.

(1) If the propagation speed of the transmission path can be considered constant, use equal length wiring.

(2) If the delay time is determined by calculation, design the circuit so that the delay times are equal.

(3) After manufacturing, an adjustable delay circuit is provided.

Adjustments are made manually.

etc., and what is the method for automatically adjusting the delay time?

It didn't exist before.

[Problem that the invention seeks to solve]

Conventional methods (1) and (2) require a large amount of design man-hours, and method (3) requires + jF! There is a problem in that not only does it require a lot of man-hours, but it also has to be adjusted for each product.

[Means for solving problems]

In the present invention, a return path having the same propagation time as the outgoing path is provided on both the reference transmission path and the adjusted transmission path, and the time difference between the pulses at the respective sending and returning ends is detected.

By converting this into a voltage proportional to the time difference at the receiving ends of the reference transmission line and the adjusted transmission line, and controlling the variable delay circuit with this voltage, the clock at the receiving ends of the reference transmission line and the adjusted transmission line is The delay time of the adjusted transmission path is automatically adjusted so that the arrival times of the two match.

FIG. 1 is a diagram showing the basic configuration of the present invention.

In Figure 1, A is the sending end of the reference transmission line, B is the receiving end of the reference transmission line, C is the return end of the reference transmission line, 5D is the sending end of the adjusted transmission line, and E is the receiving end of the adjusted transmission line. .

F is the return end of the transmission line to be adjusted, 1 is the clock generation circuit, 2
3 is a first time detector, 4 is a second time detector, and 5 is a time difference comparator.

6 is a variable delay circuit.

The transmission line (A-B) is a reference transmission line, and il! ! Always.

Select the transmission path with the longest propagation time.

The transmission path (B-C) is a return path of the reference transmission path.

Standard transmission line (A-B) and transmission! Set the times to be the same.

The transmission line (D-E) is a transmission line to be adjusted.

The transmission path (E-F) is a return path of the adjusted transmission path, and is set so that the propagation time is the same as that of the adjusted transmission path (D-E).

The clock generation circuit 1 is a circuit for generating clocks used within the logic circuit.

The automatic delay time adjustment circuit 2 includes a first time detector 3, a second time detector 45, a time difference comparator 5, and a variable delay circuit 6.

The first time detector 3 detects the time difference (G) at the sending ends (A, D) of the reference transmission line (A-B) and the adjusted transmission line (D-E)'.

The second time detector 4 detects a time difference (H ) is detected.

The time difference comparator 5 compares the one time difference (G) and (H) and outputs a voltage corresponding to the difference.

The variable delay circuit 6 controls the delay time of the transmission line to be adjusted (D-E) based on the output voltage of the one-time difference comparator 5.

[Operation] The transmission line with the longest propagation time is selected as the reference transmission line (A-B). Other transmission lines are adjusted transmission lines <D-E)
As such, a variable delay circuit 6 is inserted between the sending end (D) and the clock generation circuit 1.

A return path (B-C) having the same propagation time as the reference transmission path (A-B) is provided on the reference transmission path (A-8), and a return path (B-C) having the same propagation time as the standard transmission path (A-B) is provided.
E) is provided with a return path (E-F) having the same transmission time as the adjusted transmission path (D-E).

The clock generated by clock generation circuit l is.

After propagating through the base 1 transmission line (A-B) and reaching the receiving end (B), it propagates along the return path (B-C) and reaching the return end (C). On the other hand, the clock propagating through the first adjusted transmission line (D-E) is delayed by the variable delay circuit 6, and after propagating through the adjusted transmission line (D-E) and reaching the receiving end (E), It propagates along the return path (E-F) and reaches the return end (F).

The delay time of the variable delay circuit 6 is initially set to an appropriate value.

The first time detector 3 is connected to the sending end (A-B) of the reference transmission path (A-B).
) and the exclusive OR (EX-OR) of the clock at the sending end (D) of the transmission line to be adjusted (D-E) (G=A(E)D
).

The second time detector 4 detects the return path (B) of the reference transmission path (A-B).
Negation (H=C ■Take F).

The time difference comparator 5 calculates the time difference between the output (G) of the first time detector 3 and the output ([I) of the second time detector 4, and calculates the time difference between the output ([I]) of the first time detector 3 and the receiving end (B) of the reference transmission path (A-B). and adjusted transmission line (D
-E) outputs a voltage (J) proportional to the time difference at the receiving end (E).

The variable delay circuit 6 controls the delay time using the output voltage (J) of the 1-time difference comparator 5, so that the clock generated by the clock generation circuit 1 is transmitted to the receiving end (B) and the receiving end (B) of the reference transmission path (A-B). Automatic adjustment is made so that the receiving end (E) of the adjustment transmission line (D-E) is reached at the same time.

Figure 2 is a time chart showing a state where the timings at the receiving ends of the two transmission lines match, Figure 3 is a time chart showing a state where the timing of the adjusted transmission line is fast, and Figure 4 is the adjusted transmission line. 3 is a time chart showing a state in which the timing is slow.

【Example〕

FIG. 5 is a diagram showing the configuration of one embodiment of the present invention.

In FIG. 5, 11 is a clock generation circuit, 12 is a delay time automatic adjustment circuit, and 13 is a phase comparator.

14 is a low pass filter, and 15 is a voltage controlled delay circuit.

The phase comparator 13 performs a negation (NOT) of the exclusive OR (EX-OR) of the sending end signals (A, D) of the reference transmission line (A-B) and the adjusted transmission line (D-E). A sending end phase difference signal (G=A+D) is created by taking
A-B) and each return path (B-C) of the adjusted transmission path (D-E)
, E-F) of the return end signals (C, F) (E
A return end phase difference signal (H=C■F) is generated by taking the negation (NOT) of (X-OR).

FIG. 6 shows an example of a phase comparator.

The low-pass filter 14 outputs to the output terminal J a voltage corresponding to the difference between the Lo period of the G terminal and the Low period of the I terminal.

FIG. 7 shows an example of a low-pass if1 filter.

The voltage-controlled delay circuit 15 controls the delay time using the output voltage (J) of the low-pass filter 14.

The clock generated by the clock generation circuit 11 is transmitted to the receiving end (B) of the reference transmission line (A-B) and the adjusted transmission line (D-E).
) to reach the receiving end (E) at the same time.

FIGS. 8(a) and 8(b) show examples of voltage-controlled delay circuits.

The voltage-controlled delay circuit shown in FIG. 8(a) converts the voltage applied to the control voltage input terminal (J) into a digital signal using an A/I converter, and uses this digital signal to determine the number of stages that pass through the delay element. The delay time is adjusted by switching the multiplexer.

The voltage controlled delay circuit shown in FIG. 8(b) has a switching circuit for each delay element, and sets the delay time of the delay element to be twice the delay time of the subsequent stage. The voltage controlled delay circuit of this example can vary the delay time over a wider range than the voltage controlled delay circuit of FIG. 8(a). On the other hand, since the receiver has switching at each stage, the overall minimum delay time is.

It is larger than the voltage controlled delay circuit shown in FIG. 8(a).

An example of a complete circuit diagram combining each component described above is shown in the 9th section.
Shown in Figures (a) and (b).

In the example of FIG. 9(a), the output voltage of the low-pass filter increases when the delay time has to be increased, so the 5-voltage control delay circuit works when the control voltage is large. It is necessary to design so that the delay time is large.However, there is no problem if the whole thing is reversed.

The example shown in FIG. 9(b) is effective when the propagation delay time of the transmission line is longer than the clock cycle.

At the beginning, the operation starts with the holding circuit off and the frequency dividing circuit on. When all 9 circuits enter a steady state and the automatic adjustment of the delay time is completed, the holding circuit is turned on and the 5 frequency dividing circuit is turned off. This provides stable operation.

〔Effect of the invention〕

According to the present invention, it becomes possible to automatically adjust the delay time of a transmission path, which was previously impossible.

[Brief explanation of the drawing]

Fig. 1 is a diagram showing the basic configuration of the present invention, Fig. 2 is a time chart showing a state in which the timings at the receiving ends of two transmission lines match, and Fig. 3 is a state in which the timing of the adjusted transmission line is fast. 4 is a time chart showing a state in which the timing of the transmission line to be adjusted is slow, FIG. 5 is a diagram showing the configuration of an embodiment of the present invention, and FIG. 6 is a diagram showing an example of a phase comparator. Figure 7 shows an example of a low-pass filter, Figures 8 (a) and (b) show an example of a voltage-controlled delay circuit, and Figures 9 (a) and (b) show automatic delay time adjustment. It is an overall diagram of the circuit. 41 in Figure 1. A: Sending end of the reference transmission line B: Receiving end of the reference transmission line C: Return end of the reference transmission line D = Sending end of the adjusted transmission line E: Receiving end of the adjusted transmission line F: Return of the adjusted transmission line Terminal l: Chronograph generation circuit 2: Delay time automatic adjustment circuit 3: First time detector 4; Second time detector 5: Time difference comparator 6: Variable delay circuit

Claims (1)

[Claims] In a delay time adjustment method including a clock generation circuit (1), a reference transmission line (A-B), a transmission line to be adjusted (D-E), and a delay time adjustment circuit, the reference transmission line (A -B) and the return path (B-C) with equal propagation time and the adjusted transmission path (D-E
) and the return path (E-F) with the same propagation time, the first time detector (3), the second time detector (4), and the time difference comparator (5
), and a delay time automatic adjustment circuit (2) consisting of a variable delay circuit (6). (D-E) and the sending end (D) are detected, and the second time detector (4) detects the time difference (G) between the return end (C) of the reference transmission line (A-B) and the adjusted transmission line ( The time difference (H) with the return end (F) of D-E) is detected, and the time difference (G) and (H) are detected by the time difference comparator (5).
A voltage (J) proportional to the time difference at the receiving ends (B, E) of the reference transmission line (A-B) and the adjusted transmission line (D-E) is generated by comparing the time differences between the two. ) to control the delay time of the variable delay circuit (6) to control the reference transmission line (A
-B) and the adjusted transmission line (D-E) so that the clock arrival times at the receiving ends (B, E) of the adjusted transmission line (D-E) match.
A delay time automatic adjustment method characterized in that the delay time of D-E) is automatically adjusted.