JPH11225173A - Delay adjustment circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a circuit that automatically adjusts dispersions in a signal transmission time in a long distance signal transmission system as a system especially between LSIs. SOLUTION: A variable delay control circuit 5 measures a difference in delays between a selector output signal 102 and a received signal 106 resulting from the selector output signal 102 that passes through a variable delay circuit 3, an input output buffer 6, a transmission line 8, and is reflected in a receiver side LSI terminal 12 and returns through the transmission line 8 and the input output buffer 6 again. Thus, delays in the input output buffer 6 and in the transmission line 8 are checked and a delay in the variable delay circuit 3 is adjusted so as to obtain a delay as a setting value of the system.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a signal transmission method between a plurality of units in an information processing apparatus, and more particularly to an information processing apparatus suitable for a case where a signal transmission time between units has a large variation.

[0002]

2. Description of the Related Art In an information processing device such as a large-scale computer, it is necessary to shorten a clock cycle in order to speed up a processing operation. For this purpose, a signal transmission time, that is, a delay in the information processing device must be reduced. Must.
The delay includes a delay due to a logic element, a delay due to a wiring resistance and a wiring capacitance, and particularly, a delay in a long transmission line such as a wiring between LSIs becomes a problem. In order to overcome the problem of wiring delay between LSIs while shortening the clock cycle,
A method of transferring signals between LSIs using a plurality of cycles instead of one clock has been adopted. In this case, signals need to be transmitted between LSIs at the designed number of cycles.

FIG. 5 shows an example of a conventional delay adjustment circuit for inter-LSI transfer. The transmission side LSI 9 and the reception side LSI 10 are connected by the transmission line 8. The data signal 110 output from the output flip-flop 13 is output from the output buffer 22 via the fixed delay circuit 21 and reaches the transmission-side LSI terminal 11 to become a signal 104. The signal 104 becomes a signal 105 through the transmission line 8 and reaches the receiving LSI terminal 12. The signal 105 is input to the input buffer 7 to become a signal 111, and is input to the input flip-flop 14. Here, in order for the signal output from the output flip-flop 13 to be properly latched by the input flip-flop 14 after a specified number of cycles (hereinafter referred to as N cycles), the input from the output of the output flip-flop 13 It is necessary that the delay (d (second)) up to the input of the flip-flop 14 always satisfies Equation 1.

[0004]

(N-1) · T <d + b <N · T (1) where T is a clock cycle (second), and b is a mounting system or an LSI.
3 shows delay variations (seconds) due to manufacturing variations and environmental changes. Conventionally, the delay variation could be suppressed so as to satisfy Expression 2, and therefore, Expression 1 could be satisfied by adjusting the delay with the fixed delay circuit 21 and the transmission line 8 so as to obtain Expression 3.

[0005]

| B | <T / 2 (2)

[0006]

D = (N − ／) · T (3)

[0007]

In order to enhance the information processing capability, the clock cycle of the information processing apparatus tends to be further shortened. Also, the number of transmission lines between LSIs is increasing in order to increase the number of data to be handled simultaneously. For these reasons, the ratio of the delay variation with respect to the clock cycle increases, and Equation 2 is not satisfied. Therefore, in the conventional method of embedding a common delay adjustment fixed delay circuit in all data lines, it has become impossible to secure an operation margin for delay variation. In such a system, the delay adjustment in the operating state must be performed individually for each data line.

An object of the present invention is to provide a signal transmission system, particularly an LSI
It is an object of the present invention to provide a circuit which automatically adjusts a variation in signal transmission time over a long distance as described above and realizes stable high-speed transfer.

[0009]

According to the present invention, a first unit for transmitting or receiving a signal, a second unit for receiving or transmitting a signal, the first unit and the second unit are provided. A variable delay circuit for adjusting a time for transmitting a signal from the first unit to the second unit;
A variable delay amount control circuit for controlling a delay amount of the variable delay circuit; a signal transmitted from the first unit to the second unit; and a signal transmitted from the second unit to the first unit. A first signal present in the first unit, and a second signal transmitted using the signal transmission means, the first signal being present in the first unit, and the second signal being transmitted using the signal transmission means. The amount of delay of the variable delay circuit is determined based on the difference in delay time until input to the variable delay circuit.

Further, according to the present invention, in the signal transmission means, a first transmission line for transmitting a signal from the first unit to the second unit, and a first transmission line from the second unit to the first transmission line. The second transmission line for transmitting a signal to the unit was the same.

Further, according to the present invention, in the signal transmitting means, a signal transmitted from the first unit to the second unit is reflected at an input portion of the second unit, and a reflected wave is reflected by the second unit. The second unit transmitted to the first unit.

Further, according to the present invention, in the signal transmission means, an input / output circuit capable of switching the function of an input circuit and an output circuit is used for an input section of the second unit. The signal transmitted to the second unit is received by using the input / output circuit of the second unit as an input circuit, and the received signal is further transmitted by using the input / output circuit as an output circuit. A signal was transmitted to the first unit.

According to the invention, in the signal transmission means, a first transmission line for transmitting a signal from the first unit to the second unit, and a first transmission line from the second unit to the first transmission line. The second transmission line for transmitting a signal to the unit is different from the second transmission line.

[0014]

FIG. 1 shows an embodiment of the present invention.
The mode switching signal 109 is a switching signal for switching between the delay adjustment mode and the data transfer mode. The delay adjustment signal generation circuit 1 outputs a delay adjustment signal 101. The selector 2 outputs the delay adjustment signal 101 in the delay adjustment mode and the data signal 110 output from the output flip-flop 13 in the normal data transfer mode, according to the mode switching signal 109. The variable delay circuit 3 delays the selector output signal 102 and outputs it as a signal 103. The delay amount in the variable delay circuit 3 is adjusted by the variable delay amount control signal 108. The variable delay amount control circuit 5 measures a delay difference between the selector output signal 102 and the received signal 106, calculates an appropriate set value of the variable delay circuit 3, and outputs the calculated value as a variable delay amount control signal 108. The input / output buffer 6 is switched between an output buffer and an input buffer by an input / output buffer switching signal 107.

When the input / output buffer 6 is set to the output mode and the transmission side LSI 9 is set to the delay adjustment mode, the delay adjustment signal 101 is output as the selector output signal 102. The selector output signal 102 reaches the reception side LSI terminal 12 through the variable delay circuit 3, the input / output buffer 6, the transmission side LSI terminal 11, and the transmission line 8, and becomes a signal 105.
Here, if the input impedance when the reception side LSI 10 is viewed from the reception side LSI terminal 12 is sufficiently large with respect to the impedance of the transmission line 8, the signal 105 is reflected and the transmission line 8 is transmitted to the transmission side LSI 9. The signal proceeds toward the transmission-side LSI terminal 11 and becomes a signal 104. At this time, if the input / output buffer 6 is switched to the input mode,
The signal 104 passes through the input / output buffer 6 to become a reception signal 106 and is input to the variable delay control circuit 5.

On the other hand, the selector output signal 102 is also input to the variable delay control circuit 5. By measuring the delay difference between the selector output signal 102 and the received signal 106 by the variable delay amount control circuit 5, the sum of the delay of the variable delay circuit 3 and the delay of reciprocating between the input / output buffer 6 and the transmission line 8 can be determined. Based on this value, the variable delay amount control signal 108 is set so that the delay from the output of the output flip-flop 13 to the input of the input flip-flop 14 in the data transfer mode, that is, the data path delay becomes the target value, and the variable delay The delay value of the circuit 3 is controlled. After the adjustment of the delay value is completed, by switching the mode switching signal 109 to the data transfer mode, data transfer can be performed with a stable number of cycles.

FIG. 2 shows an embodiment of the variable delay amount control circuit 5. The variable delay amount control circuit 5 includes a counter 51 and a variable delay amount calculation circuit 52. The counter 51 receives the selector output signal 102 and the received signal 106 as inputs and outputs the counter output signal 151 as an output. Selector output signal 10
2 is used as a counter reset / counter start signal, and the received signal 106 is used as a counter stop signal. The unit of measurement of the counter is the number of minimum delay times in the variable delay circuit 3. The variable delay calculation circuit 52 receives the counter output signal 151, the reception signal 106, and the mode switching signal 109 as inputs, and outputs a variable delay control signal 108 as an output. The counter output signal 151 is used as a delay difference data signal, the reception signal 106 is used as an output select signal, and the mode switching signal 109 is used as an output enable signal.

FIGS. 1 and 2 show specific examples.
Will be described. Hereinafter, the delay value will be represented by the value of the variable delay amount control signal 108. Assuming that the delay in the variable delay circuit 3 is α and the delay for one way of the input / output buffer 6 and the transmission line 8 is β, the data path delay D is approximately D = α + β. Here, the target value of D is D
_Set to ₀ .

When the mode switching signal 109 is at a high level (delay adjustment mode), α ₀ is output from the variable delay amount control signal 108 in an initial state, and the variable delay amount is applied when a high level pulse is applied to the reception signal 106. Control signal 10
8 outputs α ₁ . Here, α ₀ is the initial value of the delay amount of the variable delay circuit 3, and α ₁ is the counter output signal 15
This is a value calculated from the value γ of 1 and has the relationship of Expression 4.

[0020]

Α ₁ = (α ₀ −γ) / 2 + D ₀ (4) When the mode switching signal 109 becomes low level (data transfer mode), the output selection by the reception signal 106 becomes invalid, and the variable delay amount control is performed. The signal 108 is held at the value immediately before the mode switching signal 109 switches from the high level to the low level.

When the mode switching signal 109 is set to the high level to set the delay adjustment mode, the selector output signal 102
Is a signal 101 for delay adjustment. Here, if the low level is continuously output from the delay adjustment signal generation circuit 1, after the signal reciprocates on the transmission line 8, the selector output signal 10
2 and the received signal 106 also go low. At this time, the variable delay amount control signal 108 becomes α ₀ , and the delay value of the variable delay circuit 3 is set to α ₀ .

Next, when a high level is output from the delay adjustment signal generating circuit 1 for about one cycle, the high level reaches the selector output signal 102 first, the count value of the counter 51 is reset, and counting starts simultaneously. . When the selector output signal 102 reciprocates on the transmission line 8 and reaches the reception signal 106 at a high level, the counter 51 stops counting. At this time, the counter output signal 15
1 indicates (α ₀ + 2β). This value is input to the variable delay amount calculation circuit 52 and becomes the following equation (5).

[0023]

Γ = α ₀ + 2β (5) Further, the variable delay amount calculation circuit 52 calculates α ₁ from Expression 4. Variable delay control signal 108 for high-level pulse is applied to the received signal 106 is alpha _1, and the delay value of the variable delay circuit 3 is set to α = α _1. As a result, the data path delay D becomes Equation 6, and can be set to the target delay value.

[0024]

D = α + β = α ₁ + β = {(α ₀ − (α ₀ + 2β)) / 2 + D ₀ } + β = D ₀ (6) Here, the mode switching signal 109 is set to low level, and the data transfer mode is set. When switched, the variable delay amount control signal 108
Is held and D = D ₀ . in this way,
It is also a feature of the present invention that the delay adjustment is completed in such a time that the delay adjustment signal 101 is reciprocated twice between the transmission side LSI 9 and the reception side LSI 10.

The initial value α of the delay amount of the variable delay circuit 3
₀ and the target data path delay D ₀ are given to the variable delay amount calculation circuit 52 in advance or can be set externally. Note that α ₀ = 0 may be used.

The data path delay D accurately includes delays in the selector 2 and the input buffer 7 in addition to α + β, but these are very small compared to α + β, and are ignored in the above calculation. Further, the delay of the input / output buffer 6 included in β differs between the input buffer time and the output buffer time.
However, these delays may be corrected when the variable delay amount calculation circuit 52 calculates the value of the variable delay amount control signal 108.

The variable delay circuit 3 and the minimum delay element of the counter 51 are formed by using the same one, for example, an inverter.

FIG. 3 is an excerpt of a signal transmitting / receiving portion of another embodiment. An input / output buffer 31 is used instead of the input buffer 7 of FIG. 1, and an input / output buffer switching signal 131 is input to change the mode of the input / output buffer 31. In the present embodiment, the signal 111 input from the input / output buffer 31 is output again using the input / output buffer 31 without using the reflection of the signal at the receiving-side LSI terminal 12 as means for reciprocating the signal to the transmission line 8. . This eliminates the need to control the impedance at the receiving LSI terminal 12 between the delay adjustment mode and the data transfer mode. A delay adjustment buffer may be inserted between the input / output buffer 31 and the signal 111. As a result, the time required for switching the input / output buffer 31 from the input mode to the output mode can be secured.

FIG. 4 is an excerpt of a signal transmission / reception part of still another embodiment. In this example, one signal transmission line is provided for transmission and one for reception, and an input buffer and an output buffer are also provided at both ends of each signal transmission line. In this case, there is no need to switch the mode of the input / output buffer, and the system construction becomes easier. However, it is necessary to mount the transmission line 8 and the transmission line 45 so that they have the same length as much as possible.

[0030]

According to the present invention, it is possible to automatically adjust the variation in signal transmission time of a long-distance signal transmission system such as between LSIs, and to perform stable high-speed transfer even when the clock cycle is short. Thus, a high-performance information processing device can be realized.

[Brief description of the drawings]

FIG. 1 is a block diagram of a delay adjustment circuit according to one embodiment of the present invention.

FIG. 2 is a block diagram of a variable delay amount control circuit according to one embodiment of the present invention.

FIG. 3 is a block diagram showing an excerpt of a signal transmission / reception part according to another embodiment of the present invention.

FIG. 4 is a block diagram showing an excerpt of a signal transmission / reception part according to still another embodiment of the present invention.

FIG. 5 is a block diagram showing an example of a conventional signal transmission system.

[Explanation of symbols]

1 ... Delay adjustment signal generation circuit, 2 ... Selector, 3 ...
Variable delay circuit, 5: variable delay amount control circuit, 6: input / output buffer, 7: input buffer, 8: transmission line, 9: transmission side L
SI, 10: LSI on the receiving side, 11: LSI terminal on the transmitting side,
12: receiving LSI terminal, 13: output flip-flop, 14: input flip-flop, 21: fixed delay circuit, 22: output buffer, 31: input / output buffer, 45
... Transmission line, 51 counter, 52 variable delay calculation circuit, 101 delay adjustment signal, 102 selector output signal, 103 signal, 104 signal, 105 signal,
106: reception signal, 107: input / output buffer switching signal,
108: variable delay amount control signal, 109: mode switching signal, 110: data signal, 111: signal, 131: input / output buffer switching signal, 151: counter output signal.

Claims (5)

[Claims] 1. A first unit for transmitting or receiving a signal, a second unit for receiving or transmitting a signal, and a signal transmission line connected between the first unit and the second unit. In the digital circuit, a variable delay circuit for adjusting a time for transmitting a signal from the first unit to the second unit; a variable delay amount control circuit for controlling a delay amount of the variable delay circuit; Transmitting a signal from the unit to the second unit;
A signal reciprocating means for transmitting a signal from the first unit to the first unit;
And the second signal transmitted by using the signal reciprocating means to transmit the first signal to the variable delay circuit. A delay adjustment circuit for determining a delay amount. 2. In the signal reciprocating means, a first transmission line for transmitting a signal from the first unit to the second unit, and transmitting a signal from the second unit to the first unit. 2. The delay adjustment circuit according to claim 1, wherein the second transmission line is the same as the second transmission line. 3. The signal reciprocating means reflects a signal transmitted from the first unit to the second unit at an input portion of the second unit, and reflects a reflected wave from the second unit to the second unit. 3. The delay adjustment circuit according to claim 2, wherein the signal is transmitted to a first unit. 4. In the signal reciprocating means, an input / output circuit capable of switching the functions of an input circuit and an output circuit is used for an input section of the second unit, and the input and output circuits are switched from the first unit to the second unit. A signal transmitted from the second unit to the first unit is received by receiving the transmitted signal as an input circuit of the input / output circuit of the second unit and further transmitting the received signal as an output circuit of the input / output circuit. 3. The delay adjusting circuit according to claim 2, wherein 5. In the signal reciprocating means, a first transmission line for transmitting a signal from the first unit to the second unit, and a signal for transmitting a signal from the second unit to the first unit. 2. The delay adjustment circuit according to claim 1, wherein the second transmission line is different from the second transmission line.