JPH11177540A - Data transfer system and its method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide the data transfer system and its method in which a limit of a data transfer speed is evaded and data are transferred at a higher speed by correcting a propagation delay time difference by a driver, a receiver and a transmission line among parameters giving hindrance to high speed transfer. SOLUTION: A test signal generating circuit 12 of a controller side 10 sends a test signal in an idle time when no image data signal is actually transferred, and a phase difference detector 23 of a printer side 20 detects a phase difference between test signals sent through a data line and a clock line, that is, a delay time difference. Then, a receiver side control section 24 informs a transmission side control section 11 of this detection result, and the transmitter side control section 11 sets and instructs a delay amount of a variable delay circuit 15a or 15b based on the informed detection result.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data transfer device in which a transmitting device and a receiving device are connected by a clock line and a data line, and data is transferred from the data line in synchronization with a clock transmitted by the clock line. More specifically, a data transfer device capable of avoiding the limit of the data transfer speed and performing higher-speed data transfer by correcting a propagation delay time difference between a driver, a receiver, and a transmission line among parameters that hinder high-speed operation. And methods.

[0002]

2. Description of the Related Art FIG. 3 is a block diagram showing a configuration of a conventional data transfer device. As shown in FIG. 1, on the transmission side, transmission data is a flip-flop (hereinafter, “FF”).
That. 1) The waveform is shaped by the clock by 1 and the transmission path is driven via the driver. On the receiving side, the received data is waveform-shaped by the FF2 with the clock inverted by the NOT circuit through the receiver via the transmission path.

Here, the NO inserted in the clock line
The T circuit shifts the phase of the clock so that the received data can be sampled by the FF2. Here, the T circuit has a general 180 degree.

FIG. 4 is a timing chart for explaining how the maximum data transfer rate in the conventional data transfer device is determined. The maximum data transfer rate in this case, as shown in FIG. 4, is represented by f = 1 / T = 1 / (ts + th + 2tsk + tdsk) (1).

[0005] As an example, a delay time difference between transmission lines is set to 0.3.
[Ns / m], transmission line length 10 [m], driver delay time difference 5 [ns], FF2 setup time 5 [ns], hold time 1 [ns], FF1
Assuming that the propagation delay time difference is 5 [ns], the maximum data transfer rate is f = 1 / T = 1 / ｛5 + 1 + 2 (0.3 × 1
0 + 5 + 5) +5｝ = 27 [MHz].

[0006]

As described above, in the above-mentioned conventional data transfer apparatus, the above-mentioned maximum data transfer rate is limited in consideration of the propagation delay time, and further high-speed transfer is impossible. Met.

Therefore, the present invention solves the above problem,
Provided is a data transfer apparatus and method capable of performing a higher-speed data transfer by avoiding a limit of a data transfer speed by correcting a propagation delay time difference between a driver, a receiver, and a transmission line among parameters that hinder speeding up. The purpose is to do.

[0008]

To achieve the above object, according to the first aspect of the present invention, a transmitting device and a receiving device are connected by a clock line and a data line, and are synchronized with a clock transmitted by the clock line. In a data transfer device for transferring data from the data line, a test signal sending unit for sending a test signal for each of the clock line and the data line, and a delay time difference between the clock line and the data line is detected from the test signal. A delay time difference detecting means, and a delay time variable control means for variably controlling a delay time for each of the clock line and the data line based on the detected delay time difference.

According to a second aspect of the present invention, in the first aspect of the present invention, the delay time difference detecting means is configured to compare and determine a phase difference between the test signal sent from the clock line and the test signal sent from the data line. It is characterized by comprising.

According to a third aspect of the present invention, in the first aspect of the invention, the variable delay time control means is configured to eliminate the delay time difference between the clock line and the data line based on the detected delay time difference. The delay time is variably controlled for each of the clock line and the data line.

According to a fourth aspect of the present invention, in the first aspect of the present invention, the variable delay time control means is provided in one of the transmitting device and the receiving device, and provided in the transmitting device. The receiving device includes a notifying unit that notifies the transmitting device of the delay time difference detected by the delay time difference detecting unit.

According to a fifth aspect of the present invention, there is provided a data transfer method in which a transmitting device and a receiving device are connected by a clock line and a data line, and data is transferred from the data line in synchronization with a clock transmitted by the clock line. Transmitting a test signal for each of the clock line and the data line, detecting a delay time difference between the clock line and the data line from the test signal, and based on the detected delay time difference,
The delay time is variably controlled for each of the clock line and the data line.

According to a sixth aspect of the present invention, in the fifth aspect of the invention, the delay time difference is detected by comparing and determining a phase difference between the test signal sent from the clock line and the test signal sent from the data line. Features.

According to a seventh aspect of the present invention, in the fifth aspect of the present invention, the variable control of the delay time is performed such that the delay time difference between the clock line and the data line is eliminated based on the detected delay time difference. The delay time is variably controlled for each of the clock line and the data line.

According to an eighth aspect of the present invention, in the invention of the fifth aspect, when the variable control of the delay time is performed by one of the transmitting device and the receiving device, and the transmitting device performs the control, The receiving device notifies the transmitting device of the detected delay time difference.

[0016]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, an embodiment of a data transfer apparatus and method according to the present invention will be described in detail with reference to the accompanying drawings.

FIG. 1 shows a data transfer apparatus 1 according to the present invention.
FIG. 1 is a diagram showing the overall configuration of the present embodiment, and is applied to data transfer between a laser printer and a printer controller in this example.

As shown in FIG. 1, this data transfer device 1
In the example, the transmitting side is the printer controller 10 and the receiving side is the printer 20. Further, a transmission path (L) 30 is provided between the transmission side and the reception side.

Here, the transmitting side (hereinafter referred to as “controller 1
0 ". ) Is a transmission-side control unit 11 for controlling the entire controller, and a test signal generation circuit 1 for transmitting a test signal used in a delay time difference correction process of the present invention described later.
2 and a D-type flip-flop on the receiving side (hereinafter, referred to as
It is called "Printer 20". ) 13 a and 13 b for shaping the waveform of the image data to be transmitted to
And a selection circuit 14 (SEL: select) which selectively outputs a test signal transmitted from the test signal generation circuit 12 and a normal signal including an output signal from the FFs 13a and 13b and a clock signal in accordance with an instruction of the transmission side control unit 11.
r) and variable delay circuits 15a to 15c (DL: delay li) that generate a delay according to the instruction of the transmission side control unit 11.
ne) and a driver (D) 16 for driving a transmission line, which is often of a differential type.

The variable range of the variable delay circuits 15a to 15c must be able to absorb the difference in propagation delay time between the predicted driver (D) 16, receiver (R) 21 and transmission path (L) 30, which will be described later. Must. Also,
In the present embodiment, the variable delay circuit 1 inserted into the clock line
5c is fixed at the center value of the variable range.

The printer 20 has a transmission path (L) 3
A receiver (R) 21 which receives a signal from 0 and converts it to an internal logic level; and FFs 22a and FFs which are D-type flip-flops for shaping image data by a clock.
22b, a phase difference detector (PD: phase detector) 2 for detecting a phase difference between the clock line and the data line
3 and a receiving side controller 24 for controlling the entire printer
FF22a, FF22
and a NOT circuit 25 for shifting b so that it can be sampled.

The controller 10 and the printer 20
EIA232C on both sides is a driver / receiver of the EIA232C standard, and the controller 10 and the printer 2
Between 0, communication means which is a serial line of the EIA232C standard is provided.

Incidentally, this communication line is generally a paper size,
This bidirectional communication line is used to check the remaining amount of paper. In this embodiment, the communication line is used to send a test signal transmission notification or a notification of a delay time difference notification and a detection result notification. Diverted as communication means.

In the above embodiment, the controller 1
When a test signal is transmitted from 0, the phase difference detected by the phase difference detector (PD) is determined by a driver,
In this embodiment, when the phase of the data line is advanced with respect to the clock line, "-" indicates that the phase is advanced, and when the phase is delayed, "+" indicates that the phase is related to the propagation delay difference between the transmission line and the receiver. The case is referred to as “0”, that is, “−” is “data line delay time <clock line delay time”, and “+” is “data line delay time> clock line delay time”. It is assumed that “0” is “data line delay time = clock line delay time”.

Although not shown in FIG. 1 in the above embodiment, a page synchronization signal and a line synchronization signal are generally sent from the printer 20 to the controller 10, and image data is transferred in response thereto. Things.

Next, the operation of the above configuration will be described.

FIG. 2 shows a data transfer apparatus 1 according to the present invention.
5 is a flowchart showing a flow of a correction delay time difference correction processing operation.

As shown in FIG. 2, first, on the controller side, the transmission-side control unit 11 transmits the test signal to the printer 20 using the EIA232C communication means (hereinafter simply referred to as "communication means"). Is sent (step 201).

On the other hand, if the printer 20 receives the test signal transmission notification during normal operation (step 301) (step 302 YES), the receiving side controller 24 receives the test signal transmission notification after the test signal transmission notification. The process shifts to the “image data ignore mode” in which the data thus determined is regarded as invalid data (step 303).

On the controller 10 side, after the above-mentioned step 201, the transmission side control section 11 switches the data to be sent out to the data line and the clock line from the normal data side (image signal and clock signal) to the test signal side. Therefore, a setting instruction is given to the selection circuit (SEL) 14 to switch to the test signal generation circuit 12 (step 202). Next, the transmission-side control unit 11 sets the variable delay circuits 15a and 1
An instruction is given to set the variable range of 5b to the minimum time (step 203). As a result, a test signal is transmitted from the test signal generation circuit 12 to each of the data line and the clock line, and the selection circuit 14, the variable delay circuits 15a and 15b, the driver (D) 16, and the transmission line (L) 3
0 to the printer 20 (step 2).
04).

After transmitting the test signal, the transmission side control unit 11 sends the test signal to the printer 20 using the communication means.
A notification request is made for the delay time difference between the data line and the clock line, that is, the delay time difference obtained from the phase difference between the test signals sent from the data line and the clock line (step 2).
05).

On the other hand, when the printer 20 receives this notification (YES in step 304), the receiving side control unit 24 executes the test transmitted from the data line and the clock line detected by the phase difference detector (PD). Information on the signal phase difference, that is, information on the delay time difference is notified to the controller 10 using the communication means (step 305).

On the other hand, when the controller 10 receives the notification of the delay time difference, the transmission-side control unit 11 sends the information on the received delay time difference to the controller 10.
"-", That is, when it is determined that "data line delay time difference <clock line delay time difference" (step 206Y
ES), and instructs the variable delay circuits 15a and 15b to increase the delay time by one step (step 2).
07). Then, again, using the communication means, the printer 2
A request for notification of the delay time difference is made to the 0 side (step 2).
08).

On the other hand, when the printer 20 receives this notification (step 304), it proceeds to step 305.
The same processing as is performed. Here, the detection result of the delay time difference is “0”, that is, “data line delay time difference = clock line delay time difference”, or “+”, that is, “data line delay time difference> clock line delay time difference”. Until
Steps 206, 207 and 20 described above
8, Step 304, Step 305, Step 206
Is repeated in the order of.

By repeatedly performing this process, the transmitting side control unit 11 transmits the notified delay time difference information to
“−”, That is, “data line delay time difference <clock line delay time difference”, that is, “0”, that is, “data line delay time difference = clock line delay time difference”, or “+”, that is, “data line delay time difference” When it is determined that “delay time difference> clock line delay time difference” (step 206N
O), the test signal generation circuit 12 stops sending the test signal (Step 209). Then, the transmission side control unit 1
1 instructs the selection circuit 14 to switch to the normal signal side (step 210). Thereafter, the transmission-side control section 11 notifies the printer 20 that the transmission of the test signal has been completed using the communication means (step 21).
1).

On the other hand, when the printer 20 receives this test signal transmission end notification (step 306Y).
ES), the subsequent received data is regarded as normal data,
Shift to "image data normal mode" (step 30)
7). Then, this process ends. In the above embodiment, since the image data is a 2-bit parallel signal, the phase difference between the data line for each bit and the clock line is obtained.

According to such a configuration, the maximum data transfer rate of the present invention is equal to tsk in equation (1) shown in the prior art.
(Propagation delay time difference between driver, receiver and transmission line)
Is replaced by ta (accuracy of a variable delay circuit), and the following expression is obtained: f ′ = 1 / T = 1 / (ts + th + 2ta + tdsk) (2) Here, ta indicates a correction result that eliminates (minimizes) a propagation delay time difference between the transmission line of the data line and the clock line, the driver, and the receiver by the correction processing operation of the above embodiment.

As an example of the above equation (2), ta (accuracy of the variable delay circuit) is 2 [n] by the correction processing of this embodiment.
s], the other values are the same as in the example shown in the above “Conventional Technology”, that is, the setup time of FF2 is 5 [ns], the hold time is 1 [ns],
If the propagation delay time difference of FF1 is 5 [ns],
f ′ = 1 / T = 1 / (5 + 5 + 2 × 2 + 5) = 66 [M
Hz]. In other words, high-speed transfer more than twice the conventional speed is possible.

That is, according to the present embodiment, the transmission delay, which is a bottleneck in determining the high-speed data transfer rate, is corrected so as to minimize (minimize) the propagation delay time difference between the driver and the receiver. The limitation of the conventional data transfer speed can be avoided, and higher-speed data transfer can be performed.

In actual use, it is necessary to consider delay variations of the selection circuit and the like.
It is needless to say that δ does not become “0” and the maximum data transfer rate is slightly lower than the value obtained by the above equation (2).

The correction process of the above embodiment is performed when normal data transfer is not performed, for example, during an initialization operation when power is turned on, or during an idle time when there is no data transfer request. In this way, high-speed data transfer can be always performed even under various conditions.

[0042]

As described above, according to the present invention,
A test signal is transmitted for each clock line and data line, a delay time difference between the clock line and the data line is detected from the test signal, and the delay time is variably controlled for each clock line and data line based on the detected delay time difference. I decided to
The limitation of the conventional data transfer speed can be avoided, and higher-speed data transfer can be performed.

[Brief description of the drawings]

FIG. 1 is a diagram showing an overall configuration of a data transfer device according to the present invention.

FIG. 2 is a flowchart showing a flow of a processing operation for correcting a propagation delay time difference of the data transfer device according to the present invention.

FIG. 3 is a block diagram showing a configuration of a conventional data transfer device.

FIG. 4 is a timing chart for explaining a maximum data transfer rate in a conventional data transfer device.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Data transfer apparatus, 10 ... Controller, 11 ... Transmission side control part, 12 ... Test signal generation circuit, 13a, 13b
... Flip-flop (FF), 14 ... Selector (SE)
L), 15a, 15b, 15c ... variable delay circuit, 16 ...
Driver (D), 20 printer, 21 receiver (R), 22a, 22b flip-flop (FF),
23: phase difference detector, 24: receiving side control unit, 25: NO
T circuit, 30 ... transmission line (L)

Claims (8)

[Claims] 1. A data transfer device for connecting a transmitting device and a receiving device by a clock line and a data line and transferring data from the data line in synchronization with a clock transmitted by the clock line, wherein the clock line and the data line A test signal transmitting unit for transmitting a test signal every time; a delay time difference detecting unit for detecting a delay time difference between the clock line and the data line from the test signal; and a clock line based on the detected delay time difference. And a delay time variable control means for variably controlling a delay time for each data line. 2. The data according to claim 1, wherein said delay time difference detecting means comprises means for comparing and judging a phase difference between said test signal sent from said clock line and said test signal sent from said data line. Transfer device. 3. The delay time variable control means, based on the detected delay time difference, varies a delay time for each of the clock line and the data line so as to eliminate a delay time difference between the clock line and the data line. 2. The data transfer device according to claim 1, wherein the data transfer is controlled. 4. The delay time variable control means is provided in one of the transmission device and the reception device. When the delay device is provided in the transmission device, the reception device is detected by the delay time difference detection means. 2. The data transfer device according to claim 1, further comprising a notification unit that notifies the transmission device of the delay time difference. 5. A data transfer method in which a transmitting device and a receiving device are connected by a clock line and a data line, and data is transferred from the data line in synchronization with a clock transmitted by the clock line. A test signal is transmitted every time, a delay time difference between the clock line and the data line is detected from the test signal, and a delay time is variably controlled for each of the clock line and the data line based on the detected delay time difference. A data transfer method. 6. The data transfer method according to claim 5, wherein the detection of the delay time difference compares and determines a phase difference between the test signal sent from the clock line and the test signal sent from the data line. 7. The variable control of the delay time, the variable control of the delay time for each of the clock line and the data line based on the detected delay time difference so as to eliminate the delay time difference between the clock line and the data line. 6. The data transfer method according to claim 5, wherein: 8. The variable control of the delay time is performed by one of the transmitting device and the receiving device. When the transmitting device performs the variable control, the receiving device determines the detected delay time difference by using the detected delay time difference. 6. The data transfer method according to claim 5, wherein the transmission device is notified.