JP2011082639A - Semiconductor integrated circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To perform wide-range and high-accuracy delay adjustment which is resistant to a variation in delay caused by a PVT variation. <P>SOLUTION: A semiconductor integrated circuit includes: a first DLL 101 for outputting a first control current I1; a second DLL 102 for outputting a second control current I2; a plurality of first variable delay elements 104 controlled by the first control current; a selector 106 for changing the number of stages of the plurality of the first variable delay elements, based on a control signal SEL; a current complementing circuit 103 for outputting a third control current I3 for complementing a value of the first control current and a value of the second control current based on the control signal SEL; and a plurality of second variable delay elements 105 controlled by the third control current I3. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a semiconductor integrated circuit, and to a delay adjustment circuit using a DLL circuit and a current interpolation circuit.

  In recent years, with the improvement of the operation speed of semiconductor integrated circuits, there is a demand for delay adjustment with higher accuracy and resistance to delay fluctuations caused by environments such as process fluctuations, voltage fluctuations, temperature fluctuations (also referred to as PVT fluctuations). Has been. For example, in the case of DDR-IF, synchronous transfer is performed in the entire transfer system of the device, transmission path, and DRAM. Therefore, when the transfer rate is high, the input / output delay is generally adjusted to the optimum point on the device side as initial training. Technology.

  Patent Document 1 uses two DLLs with different delays to be controlled, connects a plurality of delay elements controlled by the respective DLLs in series, and switches the number of passing stages, thereby realizing highly accurate delay adjustment. .

  Patent Document 2 discloses an example in which delay adjustment is performed by current control.

JP 2008-271533 A JP-A-8-255304

  Prior to the present application, the inventors of the present application examined a delay adjustment method that is highly accurate and resistant to PVT fluctuations. In order to follow the PTV fluctuation, a DLL circuit is generally used, but there is a method disclosed in Patent Document 1 as a typical method for improving the adjustment accuracy. As shown in FIG. 5, by controlling the number of passing stages of two types of delay elements having different delays to be controlled, the accuracy becomes the delay difference between the two delay elements. However, in the case of this method, it is necessary to implement complex decoding logic in order to correspond to the delay to be controlled and the control signal.

  An example of a representative one of the present invention is as follows. That is, based on a first control signal, a first DLL that outputs a first control current, a second DLL that outputs a second control current, a plurality of first variable delay elements controlled by the first control current, and a plurality of first control signals, A selector that switches the number of stages of the first variable delay element, and a current interpolation circuit that outputs a third control current for interpolating between the current value of the first control current and the current value of the second control current based on the second control signal; A plurality of second variable delay elements controlled by a third control current, and a third control based on a first variable delay element having a number of stages based on the first control signal and a second control signal. Output is delayed by a plurality of second variable delay elements controlled by current.

  According to the present invention, it is possible to realize delay adjustment that is wide-range, highly accurate, and resistant to PVT fluctuations.

It is an example of composition of the present invention. It is a structural example of a variable delay element. It is a structural example of a DLL circuit. It is a structural example of a current interpolation circuit. It is a graph which shows the relationship between the current value interpolated by the current interpolation circuit and the delay of the variable delay element controlled by the current. It is an example of control delay calculation.

  Hereinafter, embodiments of the present invention will be described with reference to FIGS.

  FIG. 1 shows an example of the overall configuration of the present invention. The delay circuit includes a variable delay element 104 controlled by a control current I1, a variable delay element 105 controlled by a control current I3, and a stage number switching selector 106 for controlling the number of passing stages of the variable delay element 104. Further, as a control circuit for the delay circuit, a first DLL 101 that generates a control current I1 with a delay per variable delay element tCK / M, and a control current I2 with a delay per variable delay element tCK / N. A second DLL 102 to be generated, and a current interpolation circuit 103 that generates a control current I3 from the control current I1 and the control current I2 are configured. However, tCK is the period of the reference clock CLK input from the outside, and M> N, that is, tCK / M <tCK / N. The path from the data input DIN to the data output DOUT in the figure is a path subject to delay control, and the number of stages of the variable delay element 104 is switched based on SEL [S: 0]. That is, rough delay adjustment is performed by adjusting the number of passing stages of the variable delay element 104, and highly accurate delay adjustment is realized by controlling the control current I3 from the current interpolation circuit 103. Further, since the adjusted delay is guaranteed by the control current from the DLLs 101 and 102, it has resistance to PVT fluctuation.

  FIG. 2 shows a configuration example of the variable delay elements 104 and 105. The delay from the data input DIN to the data output DOUT can be changed by the magnitude of the control current I.

  FIG. 3 is a configuration example of the DLLs 101 and 102. It is composed of a variable delay element 301 that controls a delay by a current, a phase comparison circuit 302, an UP / DOWN counter 303, and a DAC 304. The variable delay element is configured as shown in FIG. By inputting the clock CLK to the DLL, the phase comparison circuit 302 detects the phase difference between the clock that has passed through the variable delay element 301 and the clock that has not passed, and inputs the information to the UP / DOWN counter 303. The UP / DOWN counter 303 instructs the DAC 304 to UP (increase) and DOWN (decrease) the current I in the direction in which the phases match. The DAC 304 readjusts the amount of current based on the signal from the UP / DOWN counter, and distributes the current I to the variable delay element 304 and the output terminal. In other words, when the period of the input CLK is tCK and the number of variable delay elements 304 in the DLL circuit is X stages, the DLL circuit outputs a control current such that the delay of the variable delay element 304 is tCK / X. Become. Delay control can be performed by inputting this current I as a control current into a variable delay element that has been inserted in advance in a path where delay control is desired. Since the DLL is always operated during the operation of the chip, the current I follows the PVT variation, and the delay of the variable delay element can be made constant.

  FIG. 4 is a configuration example of the current interpolation circuit 103. The input currents I1 and I2 are calculated based on the value of the control signal SEL [2: 0], and the control current I3 is output. When the bit of SEL [2: 0] is 0, the MOS 401 based on the current I1 corresponding to that bit is turned on. When the bit of SEL [2: 0] is 1, the MOS 402 based on the current I2 corresponding to the bit is turned on. Further, the size of the MOS controlled by SEL [2: 0] differs for each bit, and the current value of the control current I3 is controlled by a combination of MOSs that are turned on.

In order to control the current value of the control current I3 with 3 bits of SEL [2: 0], assuming that I1> I2 and α = (I1−I2) / 2 ³ , in the configuration shown in FIG.
When SEL = k (0 ≦ k ≦ 2 ³ −1), I3 = I2 + (7−k) α
Thus, the control current I3 decreases linearly with respect to SEL [2: 0]. Note that the bit width and MOS size of the control signal SEL for controlling the control current I3 may be set to optimum values according to the delay accuracy to be controlled.

  FIG. 5 is a graph showing the control current value I3 and the delay of the variable delay element controlled by the current I3 when the current interpolation circuit 103 is configured as shown in FIG. The relationship between the control current I3 and the delay of the variable delay element is approximately inversely proportional, but there is no problem even if it is linearly approximated locally. That is, in the current correction circuit shown in FIG. 4, since the current decreases linearly with respect to SEL [2: 0], the relationship between SEL [2: 0] and the delay of the variable delay element increases linearly. become.

Here, in the configuration of FIG. 1, the relationship between SEL [S: 0] and the delay value to be controlled may be made linear as follows. Each bit of SEL [S: 0] controls the delay value of SEL [S: 3]: the number of passing stages of variable delay element D1 SEL [2: 0]: variable delay element D3. Here, it is assumed that the delay of the delay element D1 = tCK / M = Dm, the delay of the delay element D3 = tCK / N = Dn, and the delay element D3 is in the X stage. The increment A of the delay by incrementing 1 bit of SEL [2: 0] is A = X × (Dn−Dm) / 8 when linearly approximating the amount of change in the delay due to the control current.

Here, if 1 bit is increased from the state of SEL = 7,
SEL [2: 0] is changed from 7 to 0, the control current I3 is increased by 7α, and the delay reduction amount B controlled by the delay element D3 is B = 7A = 7X × (Dn−Dm) / 8. On the other hand, the increase amount C of the delay due to the increase of the delay element D3 by one step due to the increase of SEL [S: 3] by 1 bit is C = Dm. Here, if the delay when 1 bit is increased from the state of SEL = 7 is equal to the delay when SEL [2: 0] is increased by 1 bit, the delay is kept linear as a whole for SEL [S: 0]. Can do. That is, the relationship of C−B = A may be satisfied.

Therefore, Dm− (7X × (Dn−Dm) / 8) = (X × (Dn−Dm) / 8)
When this is transformed, Dm = X × (Dn−Dm)
Here, since Dm = tCK / M and Dn = tCK / N, X = N / (MN). The values may be determined so that X, M, and N are integers. In this case, the delay adjustment accuracy Z is Z = (tCK / M) / P, where P is the number of interpolation points of the current interpolation circuit 103 (8 in the configuration of the current interpolation circuit shown in FIG. 4). Note that various combinations of the numbers of tCK, M, N, P, and S are possible as long as the above-described predetermined relationship is satisfied. Considering the convenience of control, the delay accuracy to be controlled, the absolute value of the delay, etc., the optimum value may be applied to the apparatus.

  6 is an example of control delay calculation when tCK = 1500 ps, M = 16, N = 12, P = 8, and the number of stages of the variable delay element 105 controlled by I3 in FIG. 1 is three. A delay value for controlling SEL [S: 0] by assigning the lower 3 bits of SEL [S: 0] in FIG. 1 to the current interpolation circuit 103 and assigning the other upper bits to the switching of the number of passing stages of the variable delay element 104. Can be linear. The delay adjustment accuracy Z is Z = (1500/16) / (7 + 1) = 11.771875 ps≈11.72 ps.

  Various modifications can be made without departing from the spirit of the present invention. For example, SEL [S: 0] controls the current interpolation circuit 103 and the selector 106, but these circuits can be controlled by different control signals.

DESCRIPTION OF SYMBOLS 101 ... DLL (Delay Locked Loop), 102 ... DLL (Delay Locked Loop), 103 ... Current interpolation circuit, 104 ... Variable delay element, 105 ... Variable delay element, 106 ... Selector for number of stages switching, 301 ... Variable delay element, 302 ... Phase comparison circuit, 303 ... UP / DOWN counter, 304 ... DAC, 401 ... MOS switch, 402 ... MOS switch.

Claims (5)

A first DLL that outputs a first control current;
A second DLL that outputs a second control current;
A plurality of first variable delay elements controlled by the first control current;
A selector for switching the number of stages of the plurality of first variable delay elements based on a first control signal;
A current interpolation circuit for outputting a third control current for interpolating between the current value of the first control current and the current value of the second control current based on a second control signal;
A plurality of second variable delay elements controlled by the third control current,
The input signal is delayed by the first variable delay element having the number of stages based on the first control signal and the plurality of second variable delay elements controlled by the third control current based on the second control signal. Output semiconductor integrated circuit. In claim 1,
A reference clock with a period tCK is input,
The first DLL includes M stages of variable delay elements, and the first control current is a control current at which the delay of the variable delay elements is (tCK / M).
The second DLL includes an N-stage variable delay element, and the second control current is a control current at which the delay of the variable delay element is (tCK / N).
A semiconductor integrated circuit satisfying a relationship of N <M. In claim 2,
The second variable delay element has X stages,
A semiconductor integrated circuit which is an integer satisfying X = N / (MN). In claim 1,
The semiconductor integrated circuit, wherein the first control signal and the second control signal are given as upper bits and lower bits of one control signal. In claim 1,
The first variable delay element and the second variable delay element are semiconductor integrated circuits having the same circuit configuration.

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