JP2007228145A - Semiconductor integrated circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit capable of easily controlling the phases of respective clocks for operating a plurality of circuits without increasing a circuit scale. <P>SOLUTION: The semiconductor integrated circuit 40 comprises: a delay control means 41 for receiving a clock and finding out the number CT of in-phase delay element stages corresponding to one period of the clock; a number-of-delay-element-stages determination means 42 for determining the number of delay element stages DEGOUT1 to DEGOUTn for generating delay of prescribed quantity; and delay clock generation means 43<SB>1</SB>to 43<SB>n</SB>for delaying the clock by the number of delay element stages determined by the number-of-delay-element-stages determination means 42. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a semiconductor integrated circuit in which a plurality of circuits are operated by clocks having different phases.

  Conventionally, in a semiconductor integrated circuit, a plurality of circuits operate in synchronization with a clock. FIG. 1 shows a timing diagram of a semiconductor integrated circuit in which a plurality of conventional circuits operate in synchronization with a reference clock. As shown in FIG. 1, at the clock transition point, many elements operate simultaneously and current flows at the same time, so the peak current in the circuit increases, noise occurs in the power supply line and ground line, and performance It may cause deterioration and malfunction. The generation of noise due to this peak current is a major problem in the design of devices equipped with semiconductor integrated circuits.

Japanese Patent Laid-Open No. 2002-158286 (see Patent Document 1) discloses a semiconductor integrated circuit that can reduce the peak current by shifting the phase of each clock so that a plurality of circuits operate with independent clocks. A circuit is disclosed. FIG. 2 quotes a diagram illustrating an example of a circuit configuration of a phase separation unit that realizes the semiconductor integrated circuit disclosed in Patent Document 1. In FIG. In the phase separation unit shown in FIG. 2, a plurality of delay gates 21 are connected in series, and the output signal C _n is compared by the phase comparator 22 so that it is delayed by one cycle with respect to the input signal C ₀ . Adjust the delay amount of each delay gate. The signals C _{1 to} C _n−1 taken out between the delay gates are shifted in phase according to the delay set by the delay gate 21. Input signals _{C o} to be their signal and reference, respectively, it is supplied to the circuit block ₂₃ 1 ~ 23 _n to operate. However, the semiconductor integrated circuit described in Patent Document 1 has a problem that the delay varies due to process variations because the phase of the clock is shifted by the delay gate. In addition, when the clock frequency is high, there is a problem that adjustment is difficult.

With respect to the above problem, Japanese Patent Application Laid-Open No. 2004-145435 (see Patent Document 2) discloses a semiconductor integrated circuit capable of shifting the phase of a clock more easily and easily. FIG. 3 quotes a diagram illustrating an embodiment of the semiconductor integrated circuit disclosed in Patent Document 2. In FIG. The semiconductor integrated circuit shown in FIG. 3 has a clock generation circuit 30 that receives a reference clock having a period T and outputs a plurality of partial clocks C ₁₁ to C _1n each having a phase difference that is an integral multiple of the reference clock. and a clock control circuit 36 for controlling the period and the phase difference _{C 1n} from the clock _{C 11.} The clock generation circuit 30 uses the partial clock generation circuits 32 _{1 to} 32 _n from the partial clock C _{11 based} on the count value output from the counter 31 that counts the reference clock and the clock control signal output from the clock control circuit 36. C _1n is generated. The clock control circuit 36 generates a clock control signal based on signals output from the partial block state monitoring circuits 35 _{1 to} 35 _{n of} the circuit block state monitoring circuit 34 in accordance with the operation states of the circuit blocks 33 _{1 to} 33 _n. Generate.
JP 2002-158286 A JP 2004-145435 A

However, the semiconductor integrated circuit described in Patent Document 2 requires partial block state monitoring circuits 35 _{1 to} 35 _n for monitoring the operation state of each circuit block in order to control the clock. Therefore, there is a problem that the circuit scale of the entire semiconductor integrated circuit becomes large.

  In view of the above problems, an object of the present invention is to provide a semiconductor integrated circuit capable of easily controlling the phase of each clock for operating a plurality of circuits without increasing the circuit scale. To do.

  In order to achieve the above object, a semiconductor integrated circuit according to the present invention is provided with a delay control means for obtaining the number of common-mode delay element stages corresponding to one period of the clock, and a common-mode obtained by the delay control means. Delay element stage number determining means for determining the number of delay element stages for generating a predetermined amount of delay from the number of delay element stages, and delay clock generating means for delaying the clock by the number of delay element stages determined by the delay element stage number determining means It is characterized by having.

  As a result, there is no need to monitor a plurality of circuits operated by a clock, so that the phase of each clock for operating a plurality of circuits can be easily controlled without increasing the circuit scale. A circuit can be provided. In the semiconductor integrated circuit according to the present invention, since a plurality of circuits can be operated by clocks having different phases, peak current, power supply noise, and IR (current / resistance) drop can be suppressed. In addition, the semiconductor integrated circuit of the present invention can obtain an effect of reducing switching noise in the output cell.

  Alternatively, in order to achieve the above object, the integrated circuit of the present invention has a delay control means for receiving the first clock and obtaining the number of common-mode delay element stages corresponding to one period of the first clock; Delay element stage number determining means for determining the number of delay element stages for generating a predetermined amount of delay from the number of common-mode delay element stages determined by the delay control means, and a second element having a cycle that is an integral multiple of the first clock. A delay clock generating means for receiving a clock and delaying the basic clock by the number of stages of the delay elements determined by the delay element stage number determining means;

  As a result, it is possible to provide a semiconductor integrated circuit that can easily control the phase of each clock for operating a plurality of circuits and can reduce the number of common-mode delay element stages.

  In order to achieve the above object, the integrated circuit of the present invention is characterized in that the delay control means is a DLL.

  According to the present invention, it is possible to provide a semiconductor integrated circuit capable of easily controlling the phase of each clock for operating a plurality of circuits without increasing the circuit scale.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

  FIG. 4 is a block diagram showing an example of the circuit configuration of the semiconductor integrated circuit of the present invention.

4, the semiconductor integrated circuit 40 includes a delay control unit 41, a delay element stage number determination unit 42, n delay clock generation units 43 ₁ to 43 _n , and n circuit blocks 44 _{1 to} 44 _n . Have. The semiconductor integrated circuit 40 operates _n circuit blocks 44 _{1 to} 44 _n using clocks with different phases generated from the inputted reference clock.

  The delay control means 41 is a means for obtaining the number of in-phase delay element stages corresponding to the phase of one cycle of the input clock, and includes a delay array 411 and a control logic 412. The delay array 411 is constituted by a series connection of delay gates set with a predetermined delay amount. The control logic 412 controls the delay array 411 to obtain the in-phase delay element stage number CT corresponding to the phase of one cycle of the input clock, and outputs it to the delay element stage number determining means 42. The delay control means 41 having such a structure is generally called a DLL (Delay-Locked Loop).

The delay element stage number determination means 42 delays a reference clock, which is a clock reference for operating each circuit block, based on the common-mode delay element stage number CT output from the control logic 412 and an arbitrary gear ratio GR. This is means for determining and outputting the number of stages of delay elements DEGOUT1 to DEGOUTn required for the output. The delay clock generation means 43 ₁ to 43 _n are means for delaying the phase of the reference clock in accordance with the delay element stage numbers DEGOUT1 to DEGOUTn output from the delay element stage number determination means 42, respectively.

  Next, the phase delay operation of the semiconductor integrated circuit 40 with respect to the reference clock will be described.

The reference clock input to the semiconductor integrated circuit 40 is input to the control logic 412 of the delay control unit 41 and the delay clock generation units 43 ₁ to 43 _n .

  The control logic 412 inputs a reference clock or a signal having the same period as the reference clock to the delay array 411, and compares the phase difference between the feedback clock and the reference clock output with the phase delayed by the delay array 411. Then, the delay array 411 is controlled so as to insert a delay so that this phase difference corresponds to a delay of one period of the reference clock. The control logic 412 uses the common-mode delay element stage number CT, in which the phase difference between the reference clock and the feedback clock output from the delay array 411 corresponds to a delay of one period of the reference clock, as a binary signal, and the number of delay element stages. It outputs to the determination means 42.

The delay element stage number determination means 42 determines the delay element required for delaying the reference clock based on the common-mode delay element stage number CT output from the control logic 412 and the gear ratio GR set according to the register setting. The number of stages DEGOUT1 to DEGOUTn is determined. The delay element stage numbers DEGOUT1 to DEGOUTn determined by the delay element stage number determination unit 42 are input to the delay clock generation units 43 ₁ to 43 _n , respectively.

Further, as described above, the reference clock for operating the circuit block of the semiconductor integrated circuit 40 is input to the delay clock generation units 43 ₁ to 43 _n . The delay clock generation means 43 ₁ to 43 _n delay the phase of the reference clock in accordance with the delay element stage numbers DEGOUT 1 to DEGOUTn input from the delay element stage number determination means 42, and the phase of each of the circuit blocks 44 _{1 to} 44 _n has a phase. Different clocks C _{41 to} C _4n are supplied.

Here, assuming that one cycle is 360 degrees, the delay element stage number determining means 42 determines the delay element stage numbers DEGOUT1 to DEGOUTn by the following equation (1):
DEGOUT = CT × GR / 360 (1)
For example, when n = 3, that is, when the number of circuit blocks in the semiconductor integrated circuit 40 is 3, clocks C ₄₁ , C ₄₂ , and C 4 to be supplied to the circuit blocks 44 ₁ , 44 ₂ , 44 ₃ , respectively. _{Assume that} the gear ratio GT of C43 is set to 90 degrees, 180 degrees, and 270 degrees, respectively. Also, assuming that the value of the common-mode delay element stage number CT obtained by the control logic 412 is 100, each of the delay clock generation means 43 ₁ , 43 ₂ , 43 ₃ that generates the clocks C ₄₁ , C ₄₂ , C ₄₃ is provided. The number of input delay elements DEGOUT1, DEGOUT2, and DEOUT3 are obtained as 25, 50, and 75 from the equation (1), respectively.

The clock generators 43 ₁ , 43 ₂ , and 43 ₃ give delays corresponding to the delay element stages DEGOUT1, DEGOUT2, and DEOUT3 obtained as described above to the basic clock, respectively, and delay clocks C ₄₁ , C _42. , and outputs it as _{C 43.} FIG. 5 shows a timing chart of the semiconductor integrated circuit in this case. As shown in FIG. 5, the delay clocks C ₄₁ , C ₄₂ and C ₄₃ have a period of 1/4 (= 25/100), 1/2 (= 50/100), 3 /, respectively, with respect to the basic block. It is a signal delayed by 4 (= 75/100) periods. These clocks C ₄₁ , C ₄₂ and C ₄₃ having different phases are supplied to the circuit blocks 44 ₁ , 44 ₂ and 44 ₃ , respectively. Therefore, since the circuit blocks 44 ₁ , 44 ₂ , and 44 ₃ operate at different timings, the peak value of the operating current of the semiconductor integrated circuit 40 is the same as that of the conventional semiconductor integrated circuit shown in FIG. Smaller than the case.

  As described above, according to the present invention, the clock to be supplied to each circuit block can be easily controlled without monitoring the operation state of the circuit block.

  Alternatively, the common-mode delay element stage number CT may be determined based on a dedicated clock that is separately input instead of a reference clock for operating the circuit block. A circuit configuration of the semiconductor integrated circuit in this case is shown in FIG.

  The semiconductor integrated circuit 60 shown in FIG. 6 differs from the semiconductor integrated circuit 40 shown in FIG. 4 only in that a dedicated DLL clock is input to the delay control means 41 instead of a reference clock. The other components are the same in any semiconductor integrated circuit including the function. However, the DLL clock has a frequency that is an integral multiple of the reference clock. That is, the reference clock has a cycle that is an integral multiple of the DLL clock.

  The DLL clock input to the delay control unit 41 is input to the control logic 412. The control logic 412 inputs a DLL clock or a signal having the same period as the DLL clock to the delay array 411, and compares the phase difference between the feedback clock and the DLL clock that are output with the phase delayed by the delay array 411. Then, the delay array 411 is controlled so as to insert a delay so that this phase difference corresponds to a delay of one period of the DLL clock. The control logic 412 uses the in-phase delay element stage number CT in which the phase difference between the DLL clock and the feedback clock output from the delay array 411 corresponds to a delay of one period of the DLL clock as a binary signal, and the number of delay element stages. It outputs to the determination means 42.

The delay element stage number determination means 42 determines the delay element required for delaying the reference clock based on the common-mode delay element stage number CT output from the control logic 412 and the gear ratio GR set according to the register setting. The number of stages DEGOUT1 to DEGOUTn is determined. The delay element stage numbers DEGOUT1 to DEGOUTn determined by the delay element stage number determination means 42 are input to the delay clock generation means 43 ₁ to 43 _n , respectively.

Further, a reference clock for operating the circuit block of the semiconductor integrated circuit 60 is input to the delay clock generation means 43 ₁ to 43 _n . The delay clock generation means 43 ₁ to 43 _n delay the phase of the reference clock in accordance with the delay element stage numbers DEGOUT 1 to DEGOUTn input from the delay element stage number determination means 42, and the phase of each of the circuit blocks 44 _{1 to} 44 _n has a phase. Different clocks C _{41 to} C _4n are supplied.

Here, as in the first embodiment, the number of circuit blocks in the semiconductor integrated circuit 40 is 3, and the clocks C ₆₁ , C ₆₂ , C to be supplied to the circuit blocks 44 ₁ , 44 ₂ , 44 _{n respectively} . Consider a case where the gear ratio GT of C ₆₃ is set to 90 degrees, 180 degrees, and 270 degrees, respectively. In the first embodiment, the basic clock is input to the delay control means 41, and the value of the common-mode delay element stage number CT obtained by the control logic 412 at this time is set to 100. In this embodiment, instead of the basic clock, the DLL clock is input to the delay control means 41, and the DLL clock can have a frequency N times the basic clock (N is an integer). The value of is 100 / N. For example, when N = 5, the number of delay element stages DEGOUT1 and DEGOUT2 input to each of the delay clock generation means 43 ₁ , 43 ₂ , and 43 ₃ that generate clocks C ₆₁ , C ₆₂ , and C ₆₃ from the equation (1) DEOUT3 is obtained as 5, 10, and 15, respectively. Accordingly, by inputting a dedicated DLL clock having a frequency N times (N is an integer) of the basic block for operating each circuit block to the delay control means, the number of stages of delay elements to be used is It can be seen that 1 / N of the number of stages when the basic block is input to the delay control means.

The clock generation means 43 ₁ , 43 ₂ , 43 ₃ give the delays corresponding to the delay element stages DEGOUT1, DEGOUT2, DEOUT3 determined as described above to the basic clock, respectively, and delay clocks C ₆₁ , C ₆₂ , C ₆₃ . FIG. 7 shows a timing chart of the semiconductor integrated circuit in this case. As shown in FIG. 7, the delay clocks C ₆₁ , C ₆₂ , and C ₆₃ have a period of 1/20 (= 5/100), 1/10 (= 10/100), 3 / This is a signal delayed by 20 (= 15/100) periods. These clocks C ₄₁ , C ₄₂ and C ₄₃ having different phases are supplied to the circuit blocks 44 ₁ , 44 ₂ and 44 ₃ , respectively.

  Therefore, instead of the basic block for operating each circuit block, a dedicated DLL clock having a frequency that is an integral multiple of the basic block is input to the delay control means, thereby reducing the number of stages of delay elements to be used. it can.

  In addition, this invention is not limited to the Example mentioned above.

  For example, in the above-described embodiment, the common-mode delay element stage number CT obtained by the delay control means is output as a binary signal to the delay element stage number determination means, but if possible, it is output as another type of signal. May be.

FIG. 10 is a timing diagram of a semiconductor integrated circuit in which a plurality of conventional circuits operate in synchronization with a reference clock. It is a figure which shows an example of the circuit structure of the phase separation part which implement | achieves the semiconductor integrated circuit disclosed by Unexamined-Japanese-Patent No. 2002-158286. It is a figure which shows the Example of the semiconductor integrated circuit disclosed by Unexamined-Japanese-Patent No. 2004-145435. It is a block diagram which shows an example of the circuit structure of the semiconductor integrated circuit of this invention. FIG. 5 shows an example of a timing chart of the semiconductor integrated circuit of FIG. 4. It is a block diagram which shows the other example of the circuit structure of the semiconductor integrated circuit of this invention. FIG. 7 shows an example of a timing diagram of the semiconductor integrated circuit of FIG. 6.

Explanation of symbols

21 delay gate 22 phase comparators 23 ₁ to 23 _n , 33 _{1 to} 33 _n , 44 _{1 to} 44 _n circuit block 30 clock generation circuit 31 counter 32 _{1 to} 32 _n partial clock generation circuit 34 circuit block state monitoring circuit 35 ₁ to 35 _n partial block state monitoring circuit 36 the clock control circuit 40, 60 a semiconductor integrated circuit 41 the delay control unit 411 delays array 412 control logic 42 delay elements step number determination unit ₄₃ 1 ~ 43 _n delay clock generation means _C 0 _{~C n, C 11} ~ C _1n , C ₄₁ ~ C _4n , C ₆₁ ~ C _6n clock

Claims (3)

A delay control means for receiving a clock and calculating the number of common-mode delay element stages corresponding to one period of the clock;
Delay element stage number determining means for determining the number of delay element stages for generating a predetermined amount of delay from the number of common-mode delay element stages determined by the delay control means;
And a delay clock generating means for delaying the clock by the number of stages of delay elements determined by the delay element stage number determining means. Delay control means for receiving a first clock and calculating the number of common-mode delay element stages corresponding to one cycle of the first clock;
Delay element stage number determining means for determining the number of delay element stages for generating a predetermined amount of delay from the number of common-mode delay element stages determined by the delay control means;
Delay clock generating means for receiving a second clock having a period that is an integral multiple of the first clock and delaying the second clock by the number of delay element stages determined by the delay element stage number determining means. A semiconductor integrated circuit.   3. The semiconductor integrated circuit according to claim 1, wherein the delay control means is a DLL.

Images