JP2001236783A - Semiconductor integrated circuit device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit device provided with DLL of which the accuracy is high, the lock range is wade, and the lock-in time is shortened. SOLUTION: A variable delay circuit comprising plural variable delay elements having a control signal terminal varying a time from a time at which a signal is inputted to an input terminal to a time at which the signal is outputted from an output terminal is provided with a number of stages switching means selecting the number of stages of variable delay elements provided between the input terminal and the output terminal, a delay quantity control means forming a control signal supplied to the control signal terminal so that a phase of a first signal corresponding to a signal of the input terminal of the variable delay circuit is compared with a phase of a second signal corresponding to a delay signal of the output terminal and they are synchronized, and a number of stages control circuit detecting the number of stages by which a delay signal corresponding to one period of an input signal inputted to the input terminal is obtained out of delay signals of each stage corresponding to the variable delay circuit and indicating the number of stages of the variable delay circuit, and an internal clock signal is outputted from the variable delay circuit.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device, and more particularly to a semiconductor integrated circuit device having a clock recovery circuit for generating a clock signal corresponding to a clock signal supplied from an external terminal. The present invention relates to a technology effective for use in a type RAM (random access memory).

[0002]

2. Description of the Related Art A DLL circuit (delay locked loop) which changes the delay amount of a variable delay circuit by switching the number of stages of a digital circuit is disclosed in IEE Journal of Solid-State Circuits, Id. 33 volumes, number 11, pp.1697-1702, November,
1998 (IEEE JOURNAL OF SOLID-STATE CIRCUITS)
Is known. One that uses a variable delay circuit of the type that changes the amount of delay by changing the driving force, load, etc. of the circuit is IEE Journal of Solid-State Circuits, Vol. 33, No. 11,
pp.1703-1710, November, 1998 (IEEE JOURNAL OF
SOLID-STATE CIRCUITS). The variable delay circuit in which the number of stages of the variable delay circuit is switchable and the number of stages is determined by successive approximation is a system that uses an ISSC 99 / session 24 / paper WWTP 24.2 digest of Technical Pavers, February, 1999 pp.412-413 (ISSCC 9
9 / SESSION 24 / PAPER WP24.2DIGEST OF TECHNICAL PAPER
S).

[0003]

As a DLL used as a clock recovery circuit, one using a variable delay circuit of a type for switching the number of stages of the digital circuit (hereinafter referred to as a digital variable delay circuit) has a resolution of the variable delay circuit. Since the (time resolution) is coarse, there is a disadvantage that the accuracy of the DLL is poor. A circuit using a variable delay circuit of a type in which the amount of delay is changed by changing the driving force, load, etc. of the circuit (hereinafter referred to as an analog variable delay circuit) has a narrow variable delay range and a narrow lock range as a DLL. There are drawbacks. In order to improve both of these drawbacks, a variable delay circuit in which the number of stages of the analog variable delay circuit is switchable and the variable delay range is widened (hereinafter referred to as a stage number switchable analog variable delay circuit) has the following problem. Since successive approximation is used for the determination, there is a disadvantage that it takes time to lock in the DLL.

An object of the present invention is to provide a semiconductor integrated circuit device having a DLL with high accuracy, a wide lock range, and a short lock-in time. The above and other objects and novel features of the present invention will become apparent from the description of the present invention and the accompanying drawings.

[0005]

The following is a brief description of an outline of a typical invention among the inventions disclosed in the present application. That is, a variable delay circuit comprising a plurality of variable delay elements having a control signal terminal that changes the time from when a signal is input to the input terminal to when the signal is output from the output terminal, the input terminal and the output terminal Means for switching the number of stages of the variable delay element provided between the first and second stages, a first signal corresponding to a signal at an input terminal of the variable delay circuit, and a second signal corresponding to a delay signal at the output terminal of the variable delay circuit.
A delay amount control means for forming a control signal supplied to the control signal terminal so as to compare and synchronize the phase of the signal with the signal, and a delay signal of each stage corresponding to the variable delay circuit to the input terminal. A stage number control circuit for detecting the number of stages at which a delay signal corresponding to one cycle of the input signal is obtained and indicating the number of stages of the variable delay circuit is provided, and an internal clock signal is output from an output terminal of the variable delay circuit. .

[0006]

FIG. 1 is a block diagram showing an embodiment of a main part of a semiconductor integrated circuit device using a DLL circuit according to the present invention. The DLL according to this embodiment is of a frequency adaptive stage number switching type in order to achieve high accuracy, a wide lock range, and a short lock-in time. This embodiment DLL is mounted on a DDR (Double Data Rate) SDRAM (Synchronous Dynamic Random Access Memory) although there is no particular limitation.
Here, in the DDR SDRAM, the input clock is a differential input, but is represented by one input for simplification.

The DLL for DDR adjusts the phase of the internal clock so that the phase of the data output matches the phase of the input clock. That is, the input clock signal input from the clock input terminal is converted to an external clock signal (CKT, CKB) through the clock input buffer. The external clock signal (CKT, CKB) is delayed by a variable delay circuit on the one hand, and the internal clock signal (CK
O). This internal clock signal (CKO) is supplied to the clock terminal of the data output latch. As a result, the data output latch outputs the internal clock signal (CK).
The output data is captured in synchronization with O). The data taken into the data output latch is, for example, 1
When it consists of 6 bits, it is output from the output terminals DQ0 to DQ15 through the data output buffer.

[0008] The internal clock (CKO) is converted into an input clock signal ICLK through a frequency divider and a high-precision replica delay. The external clock signal (CKT,
CKB), on the other hand, is converted to an external clock signal ECLK through a frequency divider. The internal clock signal ICLK
And the external clock signal ECLK are compared by a phase comparator, and the variable delay circuit is analog-controlled in delay time by the control signal NBIAS formed here to make the two phases coincide. The phase comparator includes a control circuit that sets a loop sensitivity corresponding to the number of delay elements of the variable delay circuit in accordance with the number of stages determined by the number-of-stages measurement circuit.

The variable delay circuit includes a control signal NBIAS.
And a plurality of variable delay elements (differential inverter circuits) whose delay time can be changed in an analog manner. In this embodiment, the external clock signals (CKT, CKB) are supplied to a stage number measuring circuit to shorten the lock-in time. The number-of-stages measuring circuit is a stage-number-switching differential inverter-type variable delay, in which the number of stages of the plurality of variable delay elements constituting the variable delay circuit is optimal for obtaining a delay time corresponding to one cycle of the input clock signal. The number of stages of the delay element of the circuit is detected. On the one hand, the number of stages of the variable delay circuit is set, and on the other hand, the loop sensitivity in the phase comparator is set optimally.

Here, the delay amount of the clock input buffer is t1, the delay amount of the stage number switching type differential inverter type variable delay circuit is t2 (variable), the delay amount of the data output latch and the data output buffer is t3, and the high precision replica is used. Let the delay amount of the delay be (t1 + t3) and the delay amount of the frequency divider be tDIV.
Since the phase comparator controls the value of the delay amount t2 of the variable delay circuit so that the phases of both clock signals ECLK and ICLK match, the value of the delay amount t2 is calculated as follows.

Assuming that an external clock signal having a period tCK is input to the clock input terminal, the delay of the internal clock signal (CKO) with respect to the input clock signal is represented by t1 + t2 (1). The delay of the internal clock signal ICLK compared by the phase comparator is t1 + t2 + tDIV + (t1 + t3) (2). The delay of the external clock signal ECLK compared by the phase comparator is t1 + tDIV (Equation 3).

The phases of the two clock signals ICLK and EC
Since the phases of LK are equal, the following equation (4) holds. t1 + t2 + tDIV + (t1 + t3) = t1 + tDIV + n × tCK (Expression 4) By rearranging the above (Expression 4), (Expression 5) is obtained. t2 = n × tCK− (t1 + t3) (Equation 5) Therefore, the delay of the internal clock signal (CKO) is given by n × tCK−t3 (Equation 6). Since the delay is n × tCK (Equation 7), the phase of the data output is equal to the phase of the input clock.

[0013] As described above, n is a natural number, and is referred to as an nCK lock depending on the value of n and is distinguished. For example, n = 1
Is 1CK lock, and n = 2 is 2CK lock. Note that the total of the delay amount t2 of the variable delay circuit and the delay amount (t1 + t3) of the high-accuracy replica delay is n × tCK. n × tCK− (t1 + t3) + (t1 + t3) = n × tCK (Equation 8)

In the following, unless otherwise specified, n =
It is assumed that the lock is a 1,1CK lock. If the delay amount of the high-accuracy replica delay deviates from (t1 + t3), it appears as a phase error of the data output. Therefore, the high-accuracy replica delay must be as accurate as possible. That is, the high-accuracy replica delay is equal to the delay amount t.
1 and the same circuit (replica circuit) as the data output latch and data output buffer corresponding to the delay amount t3. In the same circuit formed in the semiconductor integrated circuit, since individual elements have similar process variations, the signal delay in both circuits can be made substantially equal.

FIG. 2 is a diagram for explaining the operation of the DLL variable delay circuit according to the present invention. In FIG.
A change in the delay amount of the stage number switching type differential inverter type variable delay circuit when the period tCK of the clock signal changes is shown. In the figure, n = 1, 1CK is locked. As described in (Equation 8), the sum of the delay amount of the stage number switching type differential inverter type variable delay circuit and the delay amount of the high precision replica delay is equal to n × tCK (= tCK). It can be seen that the amount of delay of the circuit must be changed greatly beyond the rate of change of tCK.

For example, in FIG. 2, the delay amount of the high-accuracy replica delay is 5 ns, and tCK is 7.5 ns.
(Clock frequency 133 MHz) to 15 ns (66 M
Hz), the delay amount t of the variable delay circuit
2 needs to be changed four times from 2.5 ns to 10 ns. That is, unless the maximum delay amount / minimum delay amount of the stage number switching type differential inverter type variable delay circuit is four times or more, the operating frequency of the DLL cannot cover 66 to 133 MHz.

In general, as the input / output data rate of the DDR SDRAM increases, a larger maximum delay / minimum delay is required. In order to realize such a wide lock range, in the present invention, as described below, a device is devised so as to determine the number of stages of the stage number switching type differential inverter type variable delay circuit to an appropriate value according to the frequency. ing.

FIG. 3 is a block diagram showing one embodiment of the DDL circuit according to the present invention. The variable delay circuit is
Variable delay element and output AMP for amplifying the output signal
(Amplifiers). That is, a plurality of the variable delay elements are connected in cascade. The output terminal of the variable delay element at each stage is provided with the output AMP. The output AMP outputs a small-amplitude delayed signal to a CMOS.
In addition to converting the signal into a large amplitude signal such as a level, it has a three-state output function of an output selection circuit, and has a function of selecting the number of delay stages by its selective operation.
As a result, the output terminals of the individual output AMPs are commonly connected to the output terminals of the variable delay circuits, and output the delayed internal clock signal CKO.

FIG. 4 shows the variable delay circuit and the output AMP.
The circuit diagram of one embodiment is shown. To simplify the circuit, the variable delay circuit has four variable delay elements and an output AMP1.
Are exemplarily shown as representatives. As shown in FIG. 4, a differential inverter circuit is used for the variable delay element.
That is, the variable delay elements are composed of the differential MOSFETs Q1 and Q2.
And a current source MOSFET provided on the common source side
Q3 and a load circuit provided at the drains of the differential MOSFETs Q1 and Q2. The above current source MOS
By changing the control voltage NBIAS at the gate of the FET Q3, the current driving force of the complementary output (OUTP, OUTN) changes, and the delay amount of the variable delay element changes.

In this embodiment, as a load circuit provided at the drain of each of the differential MOSFETs Q1 and Q2, a P-channel MOS having a gate and a drain connected to each other is provided.
The differential output (complementary output) OUTP (positive output) is obtained by connecting the P-channel MOSFETs Q6 and Q7 constituting the positive feedback circuit in parallel by connecting the gates of the FETs Q4 and Q5 crosswise to each other.
And the signal change of OUTN (negative output) is made steep. That is, since the output signal of the differential inverter circuit has a small signal amplitude, the latch type MOSF
Even if ETQ6 and ETQ7 are used, a latch operation like a CMOS latch circuit is not performed, and they operate as a variable impedance load, and operate so as to sharply change the output signal.

When a differential inverter circuit is used as in the variable delay element of this embodiment, since the amplitude of the output signal is small, the signal is amplified to the CMOS level by the output AMP and then selectively output. Output AMP is differential MOSFE
TQ8 and Q9, and MOSF provided in the common source
ETQ10, a differential amplifier circuit including current mirror type P-channel load MOSFETs Q11 and Q12 provided at the drains of the differential MOSFETs Q8 and Q9,
MOSFET Q that pulls up the output of the differential amplifier circuit
13, receiving the amplified signal of the differential amplifier circuit and
It comprises a clocked inverter circuit CN1 for sending an output signal to the APN, and an inverter circuit N1 for controlling its operation.

The gate of the MOSFET Q10, the pull-up MOSFET Q13 and the inverter circuit N1
Is supplied with a selection signal supplied from a selection terminal EN. When the selection signal is at a low level, the N-channel MOSFET Q10 is turned off,
Since the channel type pull-up MOSFET Q13 is turned on, the differential amplifier circuit stops the amplification operation, and the output terminal is fixed at a high level such as the power supply voltage. At this time, the clocked inverter circuit CN1 is brought into an output high impedance state by the high level of the output signal of the inverter circuit N1 and the low level of the selection signal EN.

When the number of stages of the variable delay elements in the variable delay circuit is eight as shown in FIG. 3, the output signal SEL <7: 0> from the stage number measurement circuit corresponding to the above number of stages.
Is formed, and the output AMP corresponding to each delay stage
Is input to the selection terminal EN. As described later, one of the output signals SEL <7: 0> is at a power supply voltage (VCC) level, and the other seven are at a ground (GND) level. Output A
MP performs an amplification operation when EN = VCC. EN = GN
In the case of D, the circuit operation is not performed, the output is high impedance, and the current consumption is almost zero. As shown in FIG. 3, the output terminals TAP0 to TAP7 of the output AMP of each stage are short-circuited, and the number of stages is changed by selecting one output AMP by SEL <7: 0>.

In FIG. 3, the multi-output fixed delay circuit of the stage number measuring circuit includes a variable delay element, an output AMP, and a delay amount fixed bias. The variable delay element and the output AMP constituting the multi-output fixed delay circuit of this embodiment are shown in FIG.
Is a circuit having the same circuit configuration and layout as those of the variable delay element. The variable delay element of the multi-output fixed delay circuit always has a fixed delay amount by a delay fixed bias circuit. That is, the current source MO shown in FIG.
The voltage NBIAS applied to the gate of the SFET Q3 is
Instead of changing like the variable delay element provided in the variable delay circuit, the voltage is fixed to a constant voltage, and the delay amount is the maximum delay amount and the minimum delay amount of the variable delay element provided in the variable delay circuit. Has been adjusted to an intermediate value. This fixed delay amount is defined as tD.

The input terminals of the multi-output fixed delay circuit include:
Through STEP output circuit and low precision replica delay,
The external clock signal CKT is supplied. The delay amount of the low precision replica delay is (t1 + t3 + tD / 2)
Is set as follows. The output of the multi-output fixed delay circuit is input to the stage number control circuit.

FIG. 5 is a circuit diagram showing one embodiment of the stage number control circuit. Each of the output signals ST0 to ST6 of the multi-output fixed delay circuit is a flip-flop circuit FF0.
FF6 to the input terminal D. Timing signals STR are supplied to clock terminals of these flip-flop circuits FF0 to FF6. The output signal Q of the flip-flop circuit FF0 is output as a stage number detection signal SEL <0> through an inverter circuit. Output signals Q of the flip-flop circuits FF1 to FF6 of the second and subsequent stages
Of the stage number detection signals SEL <1>-
Output as SEL <6>. The output signal of the last flip-flop circuit FF6 is output as a stage number detection signal SEL <7> through the output circuit.

The logic of the output signal Q of the flip-flop circuits FF1 to FF6 of the second and subsequent stages and the output signal of the corresponding preceding flip-flop circuit is such that the preceding signal is at a high level (logic 1). The selection signals SEL <1> to SEL <1> to the condition that the stage signal is at a low level (logic 0)
An AND gate circuit that sets SEL <6> to a high level is used.

FIG. 6 is a timing chart for explaining an example of the operation of the stage number control circuit. Although the input timing signal STEP and the output signal REP of the low-accuracy replica delay are differential signals in FIG. 3, only positive logic is shown in FIG. 3 for simplicity. First, after the input timing signal STEP is output, STX (X = 0 to 6)
The delay amount until is output is t1 + t3 + tD / 2 + tDX (X + 1) (9)

Next, the timing signal STR is output one cycle after the input timing signal (start signal) STEP is output. If the delay signal STX (X = 0 to 6) corresponding to the input timing signal one cycle earlier than the one-cycle delay timing signal STR rises earlier, the flip-flop FFX (X = 0 to 6) sets QX (X
= 0 to 6). For example, as shown in FIG. 6, after the delay signal ST3 rises, the delay signal ST4
If the timing signal STR delayed by one cycle rises before the rise of the signal, Q0 to Q3 = 1 and Q4 to Q6 =
0 is output. These signals Q0 to Q3 = 1, Q4 to
By passing Q6 = 0 through the above-described logic gate, SEL <4> = 1 in SEL <7: 0>, and 0 is output in all other SEL <7: 0>.

Next, the clock cycle tCK and SEL <4>
Consider the relationship First, it is assumed that SEL <4> = 1 is determined. This means that the input timing signal TR which is delayed by one cycle from the rise of the fourth-stage delay signal ST3 to the rise of the fifth-stage delay signal ST4 rises. Therefore, the following equation (10) holds. t1 + t3 + tD × 5−tD / 2 <tCK <t1 + t3 + tD × 5 + tD / 2 (10)

From (Equation 10) and (Equation 5) (n = 1), D
The delay amount t2 of the variable delay circuit in the LL section is as follows: tD × 5−tD / 2 <t2 <tD × 5 + tD / 2 (11) Here, tD is the delay amount for one stage of the delay element, and its value is controlled to an intermediate value between the maximum delay amount and the minimum delay amount. Therefore, it is understood that the optimal number of stages of the variable delay circuit is five. As described above, the optimal number of stages of the variable delay circuit according to tCK can be measured by the stage number measuring circuit, and a wider lock range can be obtained as compared with the method of fixing the number of stages. Further, in the present invention, the determination of the number of stages is completed in about 1CK (one clock), so that the lock can be performed in a shorter lock-in cycle as compared with the method of determining the number of stages by successive comparison as described above.

Since it is not necessary to operate the above stage number control circuit after determining the number of circuit stages, it is desirable to stop the circuit and reduce the current consumption. This operation is stopped by setting the delay amount fixed bias to a low level and setting the MOSFET corresponding to the MOSFET Q3 of the variable delay element shown in 4 above.
Can be turned off, and the output AMP can be easily realized by adding a simple circuit because the MOSFET corresponding to MOSFET Q10 is turned off and the output is set to high impedance.

FIG. 7 is a diagram for explaining the operation of the DDL according to the present invention. For the initial phase error, the first 1
By the operation for determining the number of stages in the clock period, the coarse adjustment up to the phase error up to tD is completed as described above.
After that, since it is only finely adjusted by the phase comparator,
The lock-in state can be set within a short time. On the other hand, in the method of determining the number of stages by successive approximation as described above, since the initial phase error must be corrected stepwise by successive approximation for each clock as shown by a dotted line, the lock range is reduced. If it is widened, the time required for lock-in becomes longer correspondingly.

FIG. 8 is a circuit diagram of an embodiment of a control circuit provided in the phase comparator. Generally, a control circuit provided in the phase comparator looks at the phases of ICLK and ECLK, controls the voltage value of the control signal NBIAS, and changes the delay amount of the variable delay circuit. However, since this circuit has a variable number of stages, the amount of change in the delay amount with respect to the amount of change in the control signal NBIAS is proportional to the number of stages. For example, when the number of stages is increased to N stages as compared with the case of one stage, the same control signal N
If N stages are selected with respect to the change in BIAS, the phase changes by N times, and the loop gain may exceed 1 and the circuit operation may become unstable.

Therefore, in this embodiment, a function of correcting the number of stages is added to the control circuit. The stage number correction function is performed by the stage number selection signal SEL <7: 0> input.
N-channel type M for generating reference current of charge pump
The switching of the OSFETs Q20 to Q27 changes the current driving force of the charge pump, and changes the amount of charge charged to the capacitor by one control. The channel width W of the N-channel MOSFETs Q20 to Q27 that generate the reference current is Q20: Q21: Q22: Q23: Q24: Q
25: Q26: Q27 = 1: 1/2: 1/3: 1/4:
1/5: 1/6: 1/7: 1/8 (the channel length L is constant), and the control signal NBIAS is obtained even when the number of stages is changed.
Is corrected so that the amount of change of the delay amount with respect to the amount of change of

Needless to say, even when the combination of the number of stages of the variable delay circuit is different from that of this embodiment, the control signal NBIAS can be obtained by appropriately setting the ratio of the N-channel MOSFETs Q20 to Q27 forming the reference current.
Can be kept constant regardless of the number of stages. In the present embodiment, the current driving force of the charge pump is changed by changing the channel width W. However, a change in the channel L, a change in the gate voltage, or the like may be used.

The reference current formed as described above is caused to flow through the diode-type P-channel MOSFET Q28, and the MOSFET Q28 and the MOSFET
TQ32 is in current mirror form and MOSFET Q3
An up-current for charging up the capacitor C is formed from the drain of the second transistor. The above MOSFETs Q28 and M
OSFET Q29 is in current mirror form and the MO
N-channel type MOSF at the drain of SFET Q29
A current mirror circuit including ETQ30 and Q31 is provided, and a down current for discharging the capacitor C from the drain of the MOSFET Q31 is formed.

Between the MOSFET Q32 and the capacitor C, a P-channel MOSFET Q14 and an N-channel MOSFET Q14 controlled by a charge-up signal formed by a phase comparison circuit.
A CMOS switch circuit including a channel type MOSFET Q16 is provided. A P-channel MOSFET controlled by a charge-down signal formed by a phase comparison circuit between the MOSFET Q31 and the capacitor C
C consisting of Q15 and N-channel MOSFET Q16
A MOS switch circuit is provided. The charge-up signal and the charge-down signal correspond to an external clock signal ECL.
It is formed by a phase comparator including flip-flop circuits FF10 and FF11 receiving K and the internal clock signal ICLK and a logic gate circuit G1, and a charge-up or charge-down signal is formed corresponding to the phase difference between the two. The voltage NBIAS held in the capacitor C is a control voltage for controlling the delay time of the variable delay element.

FIG. 9 shows a DDR to which the present invention is applied.
SDRAM (Double Data Rate Synchronous Dynamic R
An overall block diagram of one embodiment of the andom Access Memory is shown. Although the DDR SDRAM of this embodiment is not particularly limited, four memory arrays 200A to 200D are provided corresponding to four memory banks. The memory arrays 200A to 200D respectively corresponding to the four memory banks 0 to 3 include dynamic memory cells arranged in a matrix, and according to the drawing, the selection terminals of the memory cells arranged in the same column are words for each column. The data input / output terminals of the memory cells arranged on the same row are connected to complementary data lines (not shown) for each row.

One word line (not shown) of the memory array 200A is driven to a selected level in accordance with a result of decoding a row address signal by a row decoder (Row DEC) 201A. Complementary data lines (not shown) of the memory array 200A are coupled to I / O lines of a sense amplifier (Sense AMP) 202A and a column selection circuit (Column DEC) 203A. The sense amplifier 202A is an amplifier circuit that detects and amplifies a minute potential difference appearing on each complementary data line by reading data from a memory cell. The column selection circuit 203A includes a switch circuit for selecting each of the complementary data lines individually and conducting to the complementary I / O line. The column switch circuit is a column decoder 203A
Is selected in accordance with the result of decoding of the column address signal.

Similarly, memory arrays 200B to 200D also have row decoders 201B to 201D and sense amplifiers 203.
B to D and column selection circuits 203B to 203D are provided.
The complementary I / O line is shared by each memory bank, and has a data input circuit (Din Buffer) having a write buffer.
The output terminal 210 is connected to an input terminal of a data output circuit (Dout Buffer) 211 including a main amplifier. Although not particularly limited, the terminal DQ is a data input / output terminal for inputting or outputting data D0 to D15 consisting of 16 bits. The DQS buffer (DQS Buffer) 215 forms a data strobe signal of data output from the terminal DQ.

The address signals A0 to A14 supplied from the address input terminals are used as address buffers (Address Buffer).
er) 204, of which the row address signal is held in a row address buffer 205, and the column address signal is held in a column address buffer (Column).
(Address Buffer) 206. A refresh counter 208 generates a row address at the time of Automatic Refresh and Self Refresh.

The output of the column address buffer 206 is a column address counter (Column Address Counter) 20.
The column address counter 207 supplies the column address signal as the preset data or a value obtained by sequentially incrementing the column address signal as the preset data in a burst mode specified by a command or the like described later. 203A
To 203D.

Mode Register 213
Holds various operation mode information. The above row decoder
As for (Row Decoder) 201A to 201D, only those corresponding to the bank specified by the bank select (Bank Select) circuit 212 operate, and the word line is selected.
The control circuit (Control Logic) 209 includes, but is not limited to, clock signals CLK and / CLK (symbol / means that a signal attached thereto is a row enable signal), a clock enable signal CKE, and a chip select signal. / CS, column address strobe signal /
External control signals such as CAS, row address strobe signal / RAS, and write enable signal / WE;
M and DQS and an address signal via the mode register 213 are supplied, and an internal timing signal for controlling the operation mode of the DDR SDRAM and the operation of the circuit block based on a change in the level or timing of the signal. , Each having an input buffer equal to the signal.

The clock signals CLK and / CLK are supplied to the DLL circuit 21 as described above via a clock buffer.
4 and an internal clock is generated. The internal clock is not particularly limited.
And DQS buffer 215 as input signals.
The clock signal via the clock buffer is supplied to the data input circuit 210 and a clock terminal supplied to the column address counter 207.

Other external input signals are made significant in synchronization with the rising edge of the internal clock signal. The chip select signal / CS instructs the start of a command input cycle by its low level. Chip select signal / C
When S is at the high level (the chip is not selected) and other inputs have no meaning. However, internal operations such as a memory bank selection state and a burst operation, which will be described later, are not affected by the change to the chip non-selection state. / RAS, / CA
The S and / WE signals have different functions from the corresponding signals in a normal DRAM, and are significant signals when defining a command cycle described later.

The clock enable signal CKE is a signal for indicating the validity of the next clock signal.
If E is at the high level, the next rising edge of the clock signal CLK is valid, and if it is at the low level, it is invalid. In the read mode, when an external control signal / OE for controlling output enable for the data output circuit 211 is provided, the signal / O
E is also supplied to the control circuit 209, and when the signal is at a high level, for example, the data output circuit 211 is brought into a high output impedance state.

The row address signal is a clock signal C
It is defined by the levels of address signals A0 to A12 in a row address strobe / bank active command cycle described later, which is synchronized with the rising edge of LK (internal clock signal).

Address signals A13 and A14 are regarded as bank selection signals in the row address strobe / bank active command cycle. That is, A13
And A14, four memory banks 0 to
One of the three is selected. The selection control of the memory bank is not particularly limited, but only the row decoder of the selected memory bank is activated, all the column switch circuits of the unselected memory bank are not selected, the data input circuit 210 and the data of only the selected memory bank are selected. This can be performed by processing such as connection to an output circuit.

When the column address signal has a configuration of 256 Mbits × 16 bits as described above, a read or write command (column address / read command described later) synchronized with the rising edge of the clock signal CLK (internal clock) is used. , Column address / write command) cycle. The column address defined in this way is used as a start address for burst access.

Next, the SDR specified by the command
The main operation mode of the AM will be described. (1) Mode register set command (Mo) This command is for setting the mode register 30. The command is specified by / CS, / RAS, / CAS, / WE = low level, and the data to be set (register set data ) Are provided via A0-A11. Although not particularly limited, the register set data is set to a burst length, a CAS latency, a write mode, or the like. Although not particularly limited, the settable burst length is set to 2, 4, and 8, and the settable CA
The S latency is 2,2.5, and the settable write modes are burst write and single write.

In the read operation specified by a column address read command to be described later, the above CAS latency is caused by the fall of / CAS from the output buffer 21.
This indicates how many cycles of the internal clock signal are to be consumed before the output operation of 1. Until the read data is determined, an internal operation time for data read is required, and this is set in accordance with the operating frequency of the internal clock signal. In other words, when using a high-frequency internal clock signal, set the CAS latency to a relatively large value, and when using a low-frequency internal clock signal, set the CAS latency to a relatively small value. I do.

(2) Row address strobe / bank active command (Ac) This is an instruction of a row address strobe and A13 and A1.
/ CS, / RAS = low level, / CAS, / WE
= High level, then A0-A12
Are supplied as row address signals to A1
3 and the signals supplied to A14 are taken in as memory bank selection signals. The fetch operation is performed in synchronization with the rising edge of the internal clock signal as described above.
For example, when the command is specified, a word line in the memory bank specified by the command is selected, and the memory cells connected to the word line are electrically connected to the corresponding complementary data lines.

(3) Column Address Read Command (Re) This command is a command necessary for starting a burst read operation and a command for giving an instruction of a column address strobe, and / CS, / CAS =
Instructed by low level, / RAS, / WE = high level. At this time, the column address supplied to A0 to A8 (in the case of a × 16 bit configuration) is taken in as a column address signal. The fetched column address signal is supplied to the column address counter 207 as a burst start address.

In the burst read operation designated thereby, the memory bank and the word line in the memory bank are selected in the row address strobe / bank active command cycle, and the memory cell of the selected word line is The data is sequentially selected according to the address signal output from the column address counter 207 in synchronization with the internal clock signal, and is continuously read. The number of data to be continuously read is the number specified by the burst length. The start of reading data from the output buffer 211 is performed after waiting for the number of cycles of the internal clock signal defined by the CAS latency.

(4) Column Address Write Command (Wr) This command is specified by / CS, / CAS, / WE = low level and / RAS = high level. At this time, the address supplied to A0 to A8 is a column. Captured as an address signal. The column address signal thus captured is supplied to the column address counter 207 as a burst start address in burst write. The procedure of the burst write operation instructed in this way is performed in the same manner as the burst read operation. However,
There is no CAS latency in the write operation, and the capture of write data is started one clock after the column address / write command cycle.

(5) Precharge command (Pr) This is a command to start a precharge operation for the memory bank selected by A13 and A14, and / C
S, / RAS, / WE = low level, / CAS = high level.

(6) Auto-refresh command This command is a command required to start auto-refresh, and includes / CS, / RAS, / CA
Instructed by S = low level, / WE, CKE = high level.

(7) No operation command (No
p) This is a command instructing that no substantial operation is performed, / CS = low level, / RAS, / CAS, / W
It is indicated by the high level of E.

In the DDR SDRAM, when a burst operation is performed in one memory bank, another memory bank is designated in the middle of the burst operation and a row address strobe / bank active command is supplied. The operation of the row address system in the other memory bank is enabled without affecting the operation in the other memory bank.

Therefore, as long as the data D0 to D15 do not collide at the data input / output terminal of, for example, 16 bits, during execution of a command whose processing has not been completed, the command being executed is different from the memory bank to be processed. The internal operation can be started in advance by issuing a precharge command and a row address strobe / bank active command to the memory bank. The DDR SDRAM of this embodiment performs memory access in units of 16 bits as described above, and A0 to A12 ×
It has about 4M address by A0-A8 address,
Since it is composed of four memory banks, it has a storage capacity of about 256 Mbits (4 M × 4 banks × 16 bits) as a whole.

The outline of the read operation of the DDR SDRAM is as follows. Chip select / CS, / RA
Each signal of S, / CAS and write enable / WE is CL
It is input in synchronization with the K signal. A row address and a bank selection signal are input at the same time as / RAS = 0, and are held by the row address buffer 205 and the bank select circuit 212, respectively. The row decoder 210 of the bank specified by the bank select circuit 212 decodes the row address signal, and data of the entire row is output from the memory cell array 200 as a minute signal. The output small signal is amplified and held by the sense amplifier 202. The designated bank becomes active.

After 3 CLK from the input of the row address, CAS =
At the same time as 0, a column address and a bank selection signal are input, and these are held by the column address buffer 206 and the bank selection circuit 212, respectively. If the designated bank is active, the held column address is output from the column address counter 207, and the column decoder 203 selects a column. The selected data is stored in the sense amplifier 202
Output from The data output at this time is for two sets (8 bits in the × 4 bit configuration, 32 bits in the × 16 bit configuration).

Data output from sense amplifier 202 is output from data output circuit 211 to the outside of the chip. The output timing is synchronized with both the rising and falling edges of QCLK output from DLL 214. At this time,
As described above, the data of two sets is converted from parallel to serial, and becomes data of one set × 2. At the same time as the data output, the data strobe signal D
QS is output. When the burst length stored in the mode register 213 is 4 or more, the column address counter 207 automatically increments the address, and
The next column data is read.

The role of the DLL 214 is as follows: the data output circuit 211 and the operation clock QC of the DQS buffer 215.
Generate LK. The data output circuit 211 and the DQS buffer 215 take time from the input of the internal clock signal QCLK generated by the DLL 214 to the actual output of the data signal or the data strobe signal. Therefore, the phase of the internal clock signal QCLK is changed to the external CL using the high-precision replica delay circuit as described above.
By proceeding beyond K, the phases of the data signal and the data strobe signal are made to coincide with the external clock CLK. Therefore, in this case, the data signal and the data strobe signal are brought into phase with the external clock signal.

The operation and effect obtained from the above embodiment are as follows. (1) A variable delay circuit comprising a plurality of variable delay elements having a control signal terminal for changing a time from when a signal is input to an input terminal to when a signal is output from an output terminal, the input terminal and the output terminal Means for switching the number of stages of the variable delay element provided between the first and second signals, a first signal corresponding to a signal at an input terminal of the variable delay circuit, and a second signal corresponding to a delay signal at the output terminal of the variable delay circuit. And a delay amount control means for forming a control signal supplied to the control signal terminal so as to synchronize the phases with each other, and a delay signal of each stage corresponding to the variable delay circuit, which is input to the input terminal. A stage number control circuit for detecting the number of stages at which a delay signal corresponding to one cycle of the input signal is obtained and indicating the number of stages of the variable delay circuit, and outputting an internal clock signal from an output terminal of the variable delay circuit DL with high accuracy, wide lock range, and short lock-in time
The effect that L can be obtained is obtained.

(2) In addition to the above, a monitor delay circuit in which a fixed signal is supplied to the control signal terminal corresponding to the variable delay circuit is used as the stage number control circuit, and one or more cycles of the input signal are used. By detecting the number of delay stages at which a delay signal corresponding to the above is obtained, the effect that the lock-in time can be shortened can be obtained.

(3) In addition to the above, as the delay amount control means, by setting the control sensitivity to the phase comparison output signal in inverse proportion to the number of delay stages detected by the delay stage number control circuit, high precision is achieved. And a stable lock-in state can be secured.

Although the invention made by the inventor has been specifically described based on the embodiments, the invention of the present application is not limited to the above embodiments, and various modifications can be made without departing from the gist of the invention. Needless to say. For example, the multi-output fixed delay circuit of the number-of-stages measuring circuit in the frequency-adaptive stage number switching type DLL may use a digital circuit to generate an appropriate delay amount and measure the number of stages without using a variable delay element.
Also, the entire stage number measurement circuit can be configured using a delay circuit with reset and an RS flip-flop.
Further, the circuit to be adapted can be adapted not only to the DLL but also to the PLL. In other words, a ring oscillator using the variable delay element as an oscillation circuit constituting a PLL circuit is used, and the free-run frequency is switched by switching the number of stages, thereby providing high accuracy, a wide lock range, and a lock-in time. Can be obtained.

The clock generation circuit according to the present invention includes a clock generation circuit (or a reproduction circuit) in addition to the above-described synchronous DRAM of DDR, and is applicable to various digital semiconductor integrated circuit devices having a synchronous input / output. Can be widely used.

The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows. A variable delay circuit comprising a plurality of variable delay elements having a control signal terminal for changing a time from when a signal is input to the input terminal to when a signal is output from the output terminal, between the input terminal and the output terminal Means for selecting the number of stages of the variable delay elements provided in the variable delay circuit, and a phase comparison between a first signal corresponding to the signal at the input terminal of the variable delay circuit and a second signal corresponding to the delay signal at the output terminal Delay amount control means for forming a control signal supplied to the control signal terminal so as to synchronize the input signal, and an input signal input to the input terminal from delay signals of respective stages corresponding to the variable delay circuit By providing a stage number control circuit for detecting the number of stages at which a delay signal corresponding to one cycle is obtained and indicating the number of stages of the variable delay circuit, and outputting an internal clock signal from the variable delay circuit, Degree is high, it is possible to lock range is wide, and obtain the DLL short for lock-in time.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of a main part of a semiconductor integrated circuit device using a DLL circuit according to the present invention.

FIG. 2 is an operation explanatory diagram of a DLL variable delay circuit according to the present invention;

FIG. 3 is a block diagram showing one embodiment of a DDL circuit according to the present invention.

FIG. 4 is a circuit diagram showing one embodiment of a variable delay circuit and an output AMP of FIG. 3;

FIG. 5 is a circuit diagram showing one embodiment of a stage number control circuit of FIG. 3;

FIG. 6 is a timing chart for explaining an example of the operation of the stage number control circuit of FIG. 3;

FIG. 7 is an explanatory diagram of the operation of the DDL according to the present invention.

FIG. 8 is a circuit diagram showing one embodiment of a control circuit provided in the phase comparator of FIG. 3;

FIG. 9 is an overall block diagram showing an embodiment of a synchronous DRAM to which the present invention is applied.

[Explanation of symbols]

FF0 to FF6, FF10, FF11 ... flip-flop circuit, Q1 to Q32 ... MOSFET, 200A to D ...
Memory array, 201A-D ... row decoder, 202A
~ D: sense amplifier, 203A ~ D: column decoder,
204: address buffer, 205: row address buffer, 206: column address buffer, 207: column address counter, 208: refresh counter,
209: control circuit, 210: data input circuit,
211 data output circuit, 212 bank select circuit, 213 mode register, 214 DLL, 214
... DQS buffer

 ────────────────────────────────────────────────── ─── Continuing on the front page (72) Inventor Masashi Horiguchi 5-2-1, Kamizuhoncho, Kodaira-shi, Tokyo F-term in Hitachi Semiconductor Group 5B024 AA03 AA15 BA21 CA11 5B079 BA20 BB10 BC03 CC02 CC14 DD03 DD06 DD20 5J106 CC21 CC52 CC59 DD05 DD24 DD26 DD42 KK03 KK05 KK08

Claims (3)

[Claims] 1. A variable delay circuit comprising a plurality of variable delay elements having a control signal terminal for changing a time from when a signal is input to an input terminal to when a signal is output from an output terminal; A stage number switching means for selecting the number of stages of the variable delay element provided between the input terminal and the output terminal; a first signal corresponding to the signal of the input terminal of the variable delay circuit; and a delay signal of the output terminal. Delay amount control means for forming a control signal supplied to the control signal terminal so as to compare the phases of the second signal and the two signals so that the two signals coincide with each other; A stage number control circuit for detecting the number of stages from which a delay signal corresponding to one or more cycles of the input signal input to the input terminal is obtained, and instructing the stage number switching means of the number of the variable delay circuits. And a clock recovery circuit for outputting an internal clock signal from an output terminal of the variable delay circuit. 2. The circuit according to claim 1, wherein the number-of-stages control circuit corresponds to the variable delay circuit and uses a monitor delay circuit in which a fixed signal is supplied to the control signal terminal. A semiconductor integrated circuit device for detecting the number of delay stages at which a delay signal corresponding to the above is obtained. 3. The delay amount control means according to claim 1, wherein the delay amount control means sets the control sensitivity to the phase comparison output signal in inverse proportion to the number of delay stages detected by the delay stage number control circuit. Semiconductor integrated circuit device.