JP2006031933A - Dynamic type semiconductor memory apparatus, double data rate synchronous dynamic type random access memory, semiconductor memory circuit apparatus, and semiconductor integrated circuit apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a dynamic type semiconductor memory apparatus or the like provided with a DLL in which clock generating operation is stable, high accuracy and low power consumption are realized. <P>SOLUTION: This apparatus is a dynamic type semiconductor memory apparatus including a semiconductor chip. The semiconductor chip has a first power source pad for supplying a first power source potential to a clock generating circuit, a second power source pad for supplying a second power source potential having a lower potential than the first power source potential to the clock generating circuit, a third power source pad for supplying a third power source potential to an internal circuit, and a fourth power source pad for supplying a fourth power source potential having a lower potential than the third power source potential to the clock generating circuit. Further, the apparatus includes a first terminal coupled to the first power source pad, a second terminal coupled to the second power source pad, a third terminal coupled to the third power source pad and being different from the first terminal, and a fourth terminal coupled to the fourth power source pad and being different from the second terminal. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a dynamic semiconductor memory device, a double data rate synchronous dynamic random access memory, a semiconductor memory circuit device, and a semiconductor integrated circuit device, and a clock corresponding to a clock signal supplied from an external terminal The present invention relates to a semiconductor integrated circuit device provided with a clock generation circuit for generating a signal, mainly related to a technique effective when used for a synchronous dynamic RAM (random access memory).

In a semiconductor integrated circuit device having a digital circuit that operates with a clock signal supplied from an external terminal, timing margin deterioration due to a delay between the clock signal supplied from the external terminal and the clock signal supplied to the internal circuit is reduced. In order to prevent this and achieve a higher frequency of the clock signal, a DLL (Delay Locked Loop) is known as a circuit for synchronizing the clock signal supplied from the external terminal and the internal clock signal. The DLL includes a variable delay circuit that changes the delay amount and a control circuit that controls the delay amount. Regarding DLL, for example, there is JP-A-08-130464.
Japanese Patent Laid-Open No. 08-130464

  The DLL variable delay circuit includes a digital variable delay circuit that changes the delay amount by switching the number of stages of the circuit and an analog variable delay circuit that changes the delay amount by changing the drive current and load of the delay element. It is done. As a circuit for controlling the delay amount of the analog DLL using the analog variable delay circuit, a digital system that performs digital control and an analog system that uses a charge pump or the like can be considered. The DLL performance by each combination tends to be as follows.

(1) Digitally controlled digital DLL: high power consumption, precision coarse lock-in cycle, short noise resistance
(2) Digitally controlled analog DLL: high power consumption, precision, fine lock-in cycle, short noise resistance
(3) Analog control analog DLL: Low power consumption Precision fine Lock-in cycle length Noise immunity

  The above three types of DLLs have the characteristics as described above, and an analog control analog DLL is obtained when the performance of power consumption and accuracy is followed. However, the analog control DLL has a problem that a lock-in cycle is long and noise resistance is relatively poor. However, even in the digital control DLL, since the variable delay circuit is subject to fluctuations due to noise, noise resistance is not particularly good, and it is beneficial to improve it. In analog control, the control circuit is also affected by noise, so it is presumed to be inferior in noise resistance compared to digital control.

  In the future, in a semiconductor integrated circuit device in which an internal digital circuit is operated by a clock signal supplied from an external terminal, as represented by a synchronous DRAM (dynamic random access memory), the bandwidth, that is, data Therefore, there is room for improvement in accuracy, noise resistance, and lock-in cycle for DLLs employing any of the above-described methods.

  An object of the present invention is to provide a dynamic semiconductor memory device, a double data rate synchronous dynamic random access memory, a semiconductor memory, which realizes a stable clock generation operation, high accuracy and low power consumption and has a DLL. A circuit device and a semiconductor integrated circuit device are provided. The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  A typical outline of the invention disclosed in the present application will be briefly described as follows. That is, a dynamic semiconductor memory device including a semiconductor chip including a DLL circuit and a clock generation circuit for generating a clock signal and an internal circuit whose operation is controlled by the clock signal. The semiconductor chip is coupled with the clock generation circuit, and is coupled with the first power supply pad for supplying the first power supply potential to the clock generation circuit, and the clock generation circuit, and has a potential lower than the first power supply potential. A second power supply pad for supplying a second power supply potential to the clock generation circuit; a third power supply pad coupled to the internal circuit for supplying the third power supply potential to the internal circuit; A fourth power supply pad coupled to the internal circuit and for supplying a fourth power supply potential having a potential lower than the third power supply potential to the internal circuit; A first terminal coupled to the first power pad; a second terminal coupled to the second power pad; a third terminal coupled to the third power pad and different from the first terminal; A fourth terminal coupled to the power supply pad is different from the second terminal.

  A stable clock generation operation and a highly accurate DLL can be obtained.

  FIG. 1 is a schematic layout diagram of an embodiment of a dynamic RAM to which the present invention is applied. Each circuit block shown in the figure is formed on one semiconductor substrate such as single crystal silicon by a known semiconductor integrated circuit manufacturing technique. Each circuit in the figure is drawn almost in accordance with the geometrical arrangement on the semiconductor substrate. In this embodiment, the memory cell array (Memoey Cell Array) 1 is divided into four as a whole in the same manner as described above to constitute memory banks (Bank 0 to Bank 3).

  A peripheral circuit (Peripheral Circuits) 12, a data input circuit (Din Buffer) 10, a data output circuit (Dout Buffer) 7, a DQS including an address input circuit, a decoder circuit, a control circuit, etc. in a central portion along one direction of the chip. A buffer (DQS buffer) 8 and a bonding pad row 11 are provided. The data input circuit 10 and the data output circuit 7 are also included in the peripheral circuit 12 in a broad sense. That is, it should be understood that the data input circuit 10, the data output circuit 7, and the DQS buffer 8 are exemplarily shown as representative peripheral circuits. In this embodiment, the peripheral circuit in the broad sense as described above is arranged so that the peripheral circuit and the bonding pad row are arranged in order to rationalize the layout of each circuit including the random logic circuit and the like. The

  For example, when the bonding butt row and the peripheral circuit are arranged linearly in the central portion along one direction of the semiconductor chip, the number of bonding pads is limited, and the connection between the bonding pads and the peripheral circuit is limited. Will increase the distance. In this embodiment, the peripheral circuit and the bonding pad row are arranged side by side. In this configuration, the bonding pad row is arranged at a position deviated from the center line along one direction of the semiconductor chip. As a result, a relatively large grouped area can be secured in the central portion of the semiconductor chip along the one direction, which is advantageous in designing the layout of circuit elements. In other words, the configuration in which the peripheral circuit and the bonding pad row are arranged side by side as in the present application is more highly integrated and faster than the case where the peripheral circuit is arranged to the left and right with the bonding pad as the center. It will be suitable.

  The dynamic RAM of this embodiment is directed to a double data rate (DDR) synchronous DRAM (SDRAM) as will be described later, and the peripheral circuit 12 is exemplarily shown as a representative as described above. In addition to the data output circuit 7, the DQS output circuit 8 and the data input circuit 10, the following circuits are included. The booster circuit uses a charge pump circuit to form a boosted voltage VPP that has been raised to the power supply voltage VDD or higher. The operation voltage of the selection circuit for the word line to which the memory cells are connected or the selection circuit for the shared switch MOSFET is used. And a control circuit that determines the selection level and controls the operation of the booster circuit.

  The VDD / 2 circuit forms a voltage obtained by dividing the power supply voltage VDD by 1/2 to form a reference voltage for an input buffer composed of a differential circuit. The output control circuit performs operation control corresponding to the CAS latency of the data output circuit 7. The Y predecoder decodes the Y address signal to form a predecode signal. The read / write buffer performs operation control of the main amplifier and operation of the runt amplifier.

  The address-related input circuit is provided with an address buffer, an X address latch circuit, and a Y address latch circuit. The Y clock generation circuit receives a clock signal supplied from an external terminal and generates a clock signal corresponding to a Y-system operation. The mode decoder / clock buffer and the command circuit form an operation control signal. A Y counter and its control circuit are provided to generate a Y-system address signal in the Barth mode. The refresh control circuit performs an auto / self refresh operation and includes a refresh address counter. A bonding option circuit and a power-on detection circuit are also provided.

  Bonding pads are formed substantially linearly along the plurality of circuit blocks as described above. In this configuration, the signal transmission path in each circuit block is undesirably lengthened in order to avoid the boarding pad, as compared to the peripheral circuit being separated from the left and right with the bonding pad interposed therebetween. However, since it can be formed with a short length, the operation speed can be increased. Since one circuit block can be formed in a concentrated area, the layout of circuit elements in consideration of automatic wiring as described later is facilitated.

  In this embodiment, a clock generation circuit (DLL Analog) 3 is provided almost at the center of the memory chip. The clock generation circuit 3 is composed of an analog circuit as will be described later, and is provided with a circuit for supplying an input signal and a control signal to the analog circuit and a digital circuit 4 for outputting an internal clock signal.

  In this embodiment, each of the four memory cell arrays (Memory Cell Array) 1 as described above, as shown by hatching, is provided in the triple WELL, so that the substrate is separated from the peripheral circuit 12 and the like. The voltage is set, the threshold voltage of the N-channel MOSFET constituting the address selection MOSFET of the memory cell in the memory cell array 1 is controlled, the leakage current is reduced, the data retention time of the memory cell is secured and the fluctuation is suppressed. It is what you want to do.

  The memory cell array 1 as described above is provided with a sense amplifier (Sense AMP) 2, and this sense amplifier 2 is also present in the triple well where the memory cell array 1 is formed. The geometric position of the sense amplifier on the semiconductor substrate is not at one place as shown in the figure, but the memory cell array is actually divided into a plurality corresponding to the hierarchical word line and hierarchical IO line systems. Sense amplifiers are distributed and arranged corresponding to each divided subarray. The DLL analog unit 3 is provided in the triple WELL at the center of the memory chip. The triple WELL of the DLL analog unit 3 is separated from the triple WELL including the memory cell array 1 and the sense amplifier 2. A DLL digital unit 4 is provided adjacent to the DLL analog unit 3 so as to exist outside the triple WELL.

  In this embodiment, a pair of dedicated DLL power supply pads 5 are provided in the vicinity of the DLL analog unit 3. The DLL dedicated power supply pad 5 is connected only to the DLL analog unit 3 to prevent intrusion of power supply noise from other circuit blocks through the power supply path. That is, since the DLL dedicated power supply pad 5 is connected only to the DLL analog section 3, the power supply wiring and the GND wiring for supplying operation voltages of other circuits such as the peripheral circuit 12, the data output circuit 7, and the sense amplifier 2 are used. To prevent the entry of noise.

  A DQS buffer 8 is provided adjacent to the data output circuit (Dout Buffer) 7. A replica delay circuit (Replica Delay) 9 is provided adjacent to the output buffer 7. As will be described later, this replica circuit is used as a delay circuit for accurately synchronizing a clock signal passed through the DQS buffer and a clock signal supplied from an external terminal.

FIG. 2 shows a layout diagram of an embodiment of the DLL analog unit 3. The DLL analog unit 3 is formed in an independent triple well. In the figure, the peripheral portion of the DLL analog portion 3 is hatched to indicate that it is formed in one triple well. The DLL analog unit 3 includes a dedicated power supply pad VDD that supplies operating voltages such as VDD and VSS. DLL (PAD) and VSS DLL (PAD) is provided and corresponds to the pad 5 shown in FIG.

  Although the variable delay circuit 303 is not particularly limited, the variable delay circuit 303 is configured by an analog delay circuit in which a delay time is changed by changing an operation current by an analog control voltage. The variable delay circuit 303 includes a plurality of stages of delay circuits, and an output amplifier (AMP) 305 is provided. The variable delay circuit 303 includes six sets of output taps, each of which is connected to an input terminal of another output amplifier 305. Only one of the six output amplifiers 305 is always operating, and the output of the output amplifier 305 when not operating is high impedance. Therefore, the output terminals of the six output amplifiers 305 are connected in common, and only the output signal of the operating output amplifier 305 is valid. The number of output taps and output amplifiers is not limited to 6 as described above, and can be set arbitrarily.

  In this embodiment, although not particularly limited, a plurality of PMOS capacitors configured using P-channel MOSFETs are provided on the outer periphery of the DLL analog unit 3. These PMOS capacitors are used for control voltage holding, power supply VDD-GND smoothing, and spare. That is, in the figure, the PMOS capacitors formed so as to sandwich the variable delay circuit 303 and the output amplifier 305 are connected in parallel by the wiring shown by the solid line in the figure, and are charged and discharged by the charge pump 307. The delay voltage of the variable delay circuit is controlled by the control voltage VB.

  Except for the PMOS capacitor used for the charge pump 307, the PMOS capacitor provided outside the DLL analog unit 3 is used as a smoothing capacitor for the power supply VDD-VSS (GND). As a result, it is possible to stabilize the power supply voltage VDD and the ground potential VSS applied to each circuit constituting the DLL analog unit 3. In other words, the smoothing capacitor is connected between the VDD_DLL pad and the VSS_DLL pad of the DLL dedicated power supply pad.

  In this embodiment, an input buffer 301 for receiving a control signal supplied from the outside of the DLL analog unit 3 is provided in the triple WELL. An input buffer 302 for supplying a clock input signal ECLK supplied from an external terminal to the variable delay circuit 303 is also provided in the triple WELL. A CLK output buffer 304 for outputting the clock output QCLK from the selected output amplifier 305 to the data output circuit 7 is provided in the triple well. With the above configuration, the phase of the QCLK is controlled by the control voltage VB output when the control signal drives the charge pump 307.

  In this embodiment, the variable delay circuit 303 and the charge pump 307 that are vulnerable to noise are disposed in the center of the triple WELL, and are separated from the surrounding noise sources to prevent noise from entering. The control signal from the outside is temporarily buffered inside the DLL analog unit 3 to prevent intrusion of noise transmitted from the control signal. Since the DLL dedicated power source is connected only to the DLL analog unit 3, it is possible to prevent intrusion of noise from the power source wiring and the VSS (GND) wiring. As described above, the variable delay circuit 303 is provided with six output taps, and by selecting one of the six output amplifiers 305, the number of variable stages of the variable delay circuit can be selected. Thereby, even if the variable delay range deviates from the design value, it can be adjusted.

  FIG. 3 shows a schematic element structure sectional view of one embodiment of a semiconductor integrated circuit device according to the present invention. This figure shows the a-a 'cross-sectional view of FIG. As shown in the figure, the DWELL including the memory cell array 1 and the DWELL including the DLL analog unit 3 are electrically insulated by PN junction isolation. Accordingly, it is possible to prevent, for example, noise from the sense amplifier 2 which is a large noise source from entering through the substrate PSUB, although the above circuits are formed on the same P substrate PSUB.

  In addition, the DWELL including the memory cell array 1 and the DWELL including the DLL analog unit 3 have separate substrate power supplies with dedicated bonding pads and leads, and noise generated in the power supply path invades. There is no. Specifically, the power supply pad and the VSS pad are provided exclusively for the DLL analog unit 3, and such a pad is wire-bonded to a dedicated external lead. When the DLL analog unit 3 uses a step-down power supply, a power circuit dedicated to the DLL analog unit is provided in addition to the power supply pads and leads as described above.

  FIG. 4 shows a schematic element structure sectional view of one embodiment of a semiconductor integrated circuit device according to the present invention. This figure shows a cross-sectional view taken along the line b-b 'of FIG. The peripheral circuit 12 including the DLL digital unit 4 is formed in the well regions NWELL and PWELL on the P-type substrate PSUB outside the triple WELL, and noise due to the operation of the digital signal enters the DLL analog unit 3 through the substrate PSUB. Is prevented. In this embodiment, the signal from the DLL digital unit 4 to the DLL analog unit 3 is buffered by the input buffer of the DLL analog unit, and the noise component contained in the digital signal enters the charge pump and the variable delay circuit. It is preventing.

  FIG. 5 shows a schematic element structure sectional view of another embodiment of the semiconductor integrated circuit device according to the present invention. This figure is a modification corresponding to b-b 'in FIG. In this embodiment, contrary to FIG. 4, the peripheral circuit 12 including the DLL digital unit 4 is disposed inside the triple WELL, and the DLL analog unit 3 is disposed outside the triple WELL. Since the peripheral circuit and the substrate of the DLL analog unit 3 are insulated by the element isolation technique using the triple well, intrusion of noise can be prevented also in this case. That is, the above-described embodiments are the same in the sense that the peripheral circuit including the DLL digital unit 4 and the DLL analog unit 3 are electrically separated using a device isolation technique using a triple well. In this case, the triple WELL including the memory cell array 1 is separated from the triple WELL including the peripheral circuit. This is because the memory cell array 1 is arranged inside the triple well because the substrate potential is given independently rather than noise countermeasures.

  In the analog control analog DLL as in this embodiment, the variable delay circuit 303 and the charge pump (analog control circuit) 307 are vulnerable to noise. Therefore, the two circuits are separated from the surrounding noise sources. Especially in DRAM, there are many noise sources in the surroundings including a sense amplifier (Sense AMP), so that the noise isolation effect as in this embodiment is great. Then, as will be described later, a new drive system for the charge pump, which is an analog control circuit, is adopted, and the dead zone, which is a disadvantage of the conventional drive system, is eliminated, and the lock-in cycle can be shortened. Is.

  Separation of the DLL circuit from other circuits can be expected to have a particularly remarkable effect in the analog control analog DLL. However, in the digital control digital DLL and the digital control analog DLL, noise generated inside the chip can be effectively cut off. Therefore, the noise resistance of the DLL can be improved. That is, even in the digital DLL, when the operating voltage applied to the inverter circuit constituting the delay circuit fluctuates due to the power supply noise, the charge-up current and the discharge current for the capacitive load change correspondingly and the delay time fluctuates. End up.

  That is, since the power supply voltage VDD and the ground voltage VSS are the substrate bias voltage of the MOSFET, the threshold voltage is changed and the input signal supplied between the gate and the source of the MOSFET is changed. Thus, since both the input voltage and the threshold voltage as described above are subject to fluctuations due to the power supply voltage and the noise of the ground line, the delay time fluctuates in the conventional digital DLL, resulting in the output clock signal. This causes jitter (phase fluctuation). Therefore, by applying the present invention to a clock generation circuit using a DLL, it is possible to improve the noise resistance of the DLL, reduce the jitter of the DLL under the same noise condition, or increase the jitter of other circuits. Can be absorbed.

  FIG. 6 shows an overall block diagram of an embodiment of a DDR SDRAM (Double Data Rate Synchronous Dynamic Random Access Memory) to which the present invention is applied. Although the DDR SDRAM of this embodiment is not particularly limited, four memory arrays 200A to 200D are provided corresponding to four memory banks. The memory arrays 200A to 200D respectively corresponding to the four memory banks 0 to 3 are provided with dynamic memory cells arranged in a matrix, and according to the figure, the selection terminals of the memory cells arranged in the same column are the word for each column. Data input / output terminals of memory cells coupled to a line (not shown) and arranged in the same row are coupled to a complementary data line (not shown) for each row.

  One word line (not shown) of the memory array 200A is driven to a selected level according to the decoding result of the row address signal by the row decoder (Row DEC) 201A. Complementary data lines (not shown) of the memory array 200A are coupled to I / O lines of a sense amplifier (Sense AMP) 202A and a column selection circuit (Column DEC) 203A. The sense amplifier 202A is an amplifier circuit that detects and amplifies a minute potential difference appearing on each complementary data line by reading data from the memory cell. In this case, the column selection circuit 203A includes a switch circuit for selecting the complementary data lines individually and conducting them to the complementary I / O lines. The column switch circuit is selectively operated according to the decoding result of the column address signal by the column decoder 203A.

  Similarly, the memory arrays 200B to 200D are also provided with row decoders 201B to 201D, sense amplifiers 203B to 203D, and column selection circuits 203B to 203D. The complementary I / O line is shared by each memory bank, and is connected to an output terminal of a data input circuit (Din Buffer) 210 having a write buffer and an input terminal of a data output circuit (Dout Buffer) 211 including a main amplifier. Connected. The terminal DQ is not particularly limited, but is a data input / output terminal that inputs or outputs 16-bit data D0 to D15. A DQS buffer (DQS Buffer) 215 forms a data strobe signal of data output from the terminal DQ.

  Address signals A0 to A14 supplied from address input terminals are temporarily held in an address buffer 204, and among the address signals input in time series, a row address signal is a row address buffer (Row Address buffer). The column address signal is held in a column address buffer 206. A refresh counter 208 generates a row address at the time of automatic refresh (automatic refresh) and self refresh (self refresh).

  For example, when having a storage capacity of 256 Mbits, an address terminal for inputting an address signal A14 is provided as a column address signal when memory access is performed in units of 2 bits. In the x4 bit configuration, the address signal A11 is valid, in the x8 bit configuration, the address signal A10 is valid, and in the x16 bit configuration, the address signal A9 is valid. In the case of a storage capacity of 64 Mbits, the address signal A10 is valid in the x4 bit configuration, the address signal A9 is valid in the x8 bit configuration, and in the x16 bit configuration as shown in the figure. Up to the address signal A8 is valid.

  The output of the column address buffer 206 is supplied as preset data of a column address counter 207, and the column address counter 207 receives the column address signal as the preset data in a burst mode specified by a command to be described later. Alternatively, a value obtained by sequentially incrementing the column address signal is output to the column decoders 203A to 203D.

  A mode register (Mode Register) 213 holds various operation mode information. Of the row decoders 201A to 201D, only those corresponding to the bank designated by the bank select circuit 212 operate, and the word line is selected. The control circuit (Control Logic) 209 is not particularly limited, but includes a clock signal CLK, / CLK (the symbol / means that a signal to which this is attached is a low enable signal), a clock enable signal CKE, and a chip select signal. External control signals such as / CS, column address strobe signal / CAS, row address strobe signal / RAS, and write enable signal / WE, and address signals via / DM and DQS and mode register 213 are supplied. An internal timing signal for controlling the operation mode of the DDR SDRAM and the operation of the circuit block is formed based on a change in signal level, timing, and the like, and each has an input buffer corresponding to the signal.

  The clock signals CLK and / CLK are input to the DLL circuit 214 as described above via the clock buffer, and an internal clock is generated. The internal clock is not particularly limited, but is used as an input signal for the data output circuit 211 and the DQS buffer 215. The clock signal via the clock buffer is supplied to the data input circuit 210 and a clock terminal supplied to the column address counter 207.

  Other external input signals are made significant in synchronization with the rising edge of the internal clock signal. The chip select signal / CS instructs the start of the command input cycle according to its low level. When the chip select signal / CS is at a high level (chip non-selected state) or other inputs are meaningless. However, internal operations such as a memory bank selection state and a burst operation, which will be described later, are not affected by the change to the chip non-selection state. Each of the signals / RAS, / CAS, / WE has a function different from that of a corresponding signal in a normal DRAM, and is a significant signal when defining a command cycle to be described later.

  The clock enable signal CKE is a signal that indicates the validity of the next clock signal. The rising edge of the next clock signal CLK is valid if the signal CKE is high level, and invalid when the signal CKE is low level. In the read mode, when the external control signal / OE for controlling the output enable for the data output circuit 211 is provided, the signal / OE is also supplied to the control circuit 209. When the signal is at a high level, for example. The data output circuit 211 is set to a high output impedance state.

  The row address signal is defined by the levels of A0 to A11 in a later-described row address strobe / bank active command cycle synchronized with the rising edge of the clock signal CLK (internal clock signal).

  The address signals A12 and A13 are regarded as bank selection signals in the row address strobe / bank active command cycle. That is, one of the four memory banks 0 to 3 is selected by a combination of A12 and A13. The selection control of the memory bank is not particularly limited, but only the row decoder on the selected memory bank side is activated, all the column switch circuits on the non-selected memory bank side are not selected, the data input circuit 210 and the data only on the selected memory bank side This can be done by processing such as connection to an output circuit.

  When the column address signal is 256 M bits and × 16 bits as described above, a read or write command synchronized with the rising edge of the clock signal CLK (internal clock) (column address / read command, column address described later) Write command) Defined by the levels of A0 to A9 in the cycle. The column address thus defined is used as a burst access start address.

Next, main operation modes of the SDRAM indicated by the command will be described. (1) Mode register set command (Mo)
This is a command for setting the mode register 30, and is designated by / CS, / RAS, / CAS, / WE = low level, and data to be set (register set data) is given via A0 to A11. . The register set data is not particularly limited, but is set to burst length, CAS latency, write mode, or the like. Although not particularly limited, the settable burst length is 2, 4, 8, the settable CAS latency is 2,2.5, and the settable write mode is burst write and single write. .

  The CAS latency indicates how many cycles of the internal clock signal are spent from the fall of / CAS to the output operation of the output buffer 211 in a read operation instructed by a column address read command to be described later. . An internal operation time for reading data is required until the read data is determined, and is used for setting it according to the use frequency of the internal clock signal. In other words, the CAS latency is set to a relatively large value when an internal clock signal with a high frequency is used, and the CAS latency is set to a relatively small value when an internal clock signal with a low frequency is used. To do.

(2) Row address strobe / bank active command (Ac)
This is a command for validating the instruction of the row address strobe and the selection of the memory bank by A12 and A13, and is indicated by / CS, / RAS = low level, / CAS, / WE = high level, and at this time, A0 to A9. The address supplied to A is taken as a row address signal, and the signals supplied to A12 and A13 are taken as memory bank selection signals. The capturing operation is performed in synchronization with the rising edge of the internal clock signal as described above. For example, when the command is designated, the word line in the memory bank designated by the command is selected, and the memory cells connected to the word line are respectively conducted to the corresponding complementary data lines.

(3) Column address / read command (Re)
This command is a command necessary for starting a burst read operation, and a command for giving an instruction of a column address strobe, which is indicated by / CS, / CAS = low level, / RAS, / WE = high level, At this time, the column address supplied to A0 to A9 (in the case of x16 bit configuration) is taken in as a column address signal. The column address signal thus fetched is supplied to the column address counter 207 as a burst start address.

  In the burst read operation instructed thereby, the memory bank and the word line in the row address strobe / bank active command cycle are selected before that, and the memory cell of the selected word line receives the internal clock signal. Are sequentially selected according to the address signal output from the column address counter 207 and read continuously. The number of data continuously read out is the number specified by the burst length. Data read from the output buffer 211 is started after waiting for the number of cycles of the internal clock signal defined by the CAS latency.

(4) Column address / write command (Wr)
This command is instructed by / CS, / CAS, / WE = low level, / RAS = high level, and at this time, the address supplied to A0 to A9 is taken in as a column address signal. The column address signal thus fetched is supplied to the column address counter 207 as a burst start address in burst write. The procedure of the burst write operation instructed thereby is performed in the same manner as the burst read operation. However, there is no CAS latency in the write operation, and the capture of the write data is started one clock after the column address / write command cycle.

(5) Precharge command (Pr)
This is a command for starting a precharge operation for the memory bank selected by A12 and A13, and is designated by / CS, / RAS, / WE = low level and / CAS = high level.

(6) Auto-refresh command This command is required to start auto-refresh, and is designated by / CS, / RAS, / CAS = low level, / WE, CKE = high level.

(7) No operation command (Nop)
This is a command for instructing that no substantial operation is performed, and is designated by / CS = low level, / RAS, / CAS, / WE high level.

  In a DDR SDRAM, when a burst operation is performed in one memory bank, if another memory bank is specified in the middle and a row address strobe / bank active command is supplied, The row address operation in another memory bank can be performed without affecting the operation in the memory bank.

  Therefore, for example, when data D0 to D15 do not collide at a 16-bit data input / output terminal, during execution of a command that has not been processed, the command being executed is different from the memory bank to be processed. It is possible to start the internal operation in advance by issuing a precharge command and a row address strobe / bank active command. The DDR SDRAM of this embodiment performs memory access in units of 16 bits as described above, and has about 4M addresses by the addresses A0 to A11, and is composed of four memory banks. The storage capacity is 256M bits (4M × 4 banks × 16 bits).

  The detailed read operation of the DDR SDRAM is as follows. Chip select / CS, / RAS, / CAS, and write enable / WE signals are input in synchronization with the CLK signal. At the same time as / RAS = 0, a row address and a bank selection signal are input and held in the row address buffer 205 and the bank select circuit 212, respectively. The row decoder 210 of the bank designated by the bank select circuit 212 decodes the row address signal, and the data of the entire row is output from the memory cell array 200 as a minute signal. The output minute signal is amplified and held by the sense amplifier 202. The specified bank becomes active.

  After 3 CLK from the row address input, a column address and a bank selection signal are input simultaneously with CAS = 0, and are held in the column address buffer 206 and the bank select circuit 212, respectively. If the designated bank is active, the held column address is output from the column address counter 207, and the column decoder 203 selects a column. The selected data is output from the sense amplifier 202. The data output at this time is two sets (8 bits in the x4 bit configuration, 32 bits in the x16 bit configuration).

  Data output from the sense amplifier 202 is output from the data output circuit 211 to the outside of the chip. The output timing is synchronized with both rising and falling edges of QCLK output from the DLL 214. At this time, as described above, the two sets of data are converted from parallel to serial to become one set × 2 data. Simultaneously with the data output, a data strobe signal DQS is output from the DQS buffer 215. When the burst length stored in the mode register 213 is 4 or more, the column address counter 207 automatically increments the address and reads the next column data.

  The role of the DLL 214 is to generate the data output circuit 211 and the operation clock QCLK of the DQS buffer 215. The data output circuit 211 and the DQS buffer 215 take time from when the internal clock signal QCLK generated by the DLL 214 is input until a data signal or a data strobe signal is actually output. For this reason, the phase of the internal clock signal QCLK is advanced from that of the external CLK by using a replica circuit as will be described later, so that the phase of the data signal or the data strobe signal is matched with that of the external clock CLK. Therefore, in this case, the data signal and the data strobe signal are matched in phase with the external clock signal.

  FIG. 7 shows an overall block diagram of an embodiment of a DLL according to the present invention. In the figure, an overall view of the DLL centering on the DLL digital unit 4 is shown. The DLL digital unit 4 controls the DLL analog unit 3 so that the external clock signal ECLK_T and the internal clock signal ICLK input via the clock input circuit 2091 have the same phase.

  In the DLL of this embodiment, in order to prevent harmonic lock, the external clock signal ECLK_T and the internal clock signal ICLK are each divided by 4 by the frequency dividing circuit 401. As described above, the phase comparator 402 compares the phases of ECLK4 obtained by dividing the external clock signal ECLK_T by 4 and ICLK4 obtained by dividing the internal clock signal ICLK by 4. The state control circuit 403 outputs the TURBO signal and the TURBO1 signal by looking at the waveform of EARLY_INT, which is the result of the phase comparison. The pulse generation circuit 404 outputs an up (UP) signal and a down (DOWN) signal to control the operation of the charge pump provided in the DLL analog unit 3.

  In this embodiment, a charge pump test pulse generation circuit 405 is provided, and a CP_PULSE signal, which will be described later, output from this circuit is provided in the DLL analog unit 3 in place of the up signal UP and the down signal DOWN. The charge pump is controlled to perform the test. For simplification of the drawings, detailed control signals that are not directly related to the present invention are omitted.

The frequency dividing circuit 401 has a clock signal ECLK passed through the clock input circuit 2091. T and an internal clock signal ICLK through a replica (Replica Delay) 406 are supplied. As a result, ECLK4 and ICLK4 each divided by 4 are phase-compared by the phase comparator 402. The replica circuit 406 is a delay circuit composed of the same circuit as the clock input circuit 2091 and the data output circuit 211 or the DQS buffer (output circuit) 215. Since the internal clock signal QCLK having a phase advanced by the circuit 2091 and the data output circuit 211 (or the DQS buffer 215) is generated, the external clock signal CLK T and the data signal that has passed through the data output circuit 211 or the clock signal that has been output through the DQS buffer 215, for example, have the same phase.

  FIG. 8 shows a circuit diagram of an embodiment of a variable delay circuit included in the DLL analog unit 3. The variable delay circuit 303 includes a variable delay element and a bias circuit. The variable delay element has a configuration in which two differential inverters are connected in series, and the amount of delay is varied by controlling the current of the current source with NBIAS. The circuit of the above two differential inverters is shown and will be described by taking as an example the preceding circuit to which the circuit symbol is attached. The common source of the N-channel type differential MOSFETs Q1 and Q2 and the ground potential of the circuit N-channel MOSFETs Q7 and Q8 are provided in parallel as variable current sources whose current can be changed by the NBIAS.

  Between the drains of the differential MOSFETs Q1 and Q2 and the power supply voltage VDD, diode-connected P-channel MOSFETs Q3 and Q4 are provided as load circuits, respectively. In order to make the change in the differential output signal steep, latch-type P-channel MOSFETs Q5 and Q6, whose gates and drains are connected to each other, are provided in parallel to the diode-connected MOSFETs Q3 and Q4. . The drain outputs of the differential MOSFETs Q1 and Q2 are supplied to the gates of the differential MOSFETs as input signals for the next stage circuit. A variable delay circuit 303 is formed by connecting the two differential inverters as described above in a plurality of stages, and output taps TAPN0, TAPP0 to TAPPNN, and TAPPN are provided in a plurality of 0 to N from the last stage. In the embodiment of FIG. 2, there are six output taps.

  The bias circuit converts the control voltage VB into a current signal by the MOSFET Q9 and is connected to the current source MOSFET of each differential inverter using a simple current mirror, but corrects the control voltage-delay amount characteristic. A buffer circuit or the like may be used. The output of the variable delay circuit is provided with a plurality (for example, six sets) of output taps as described above, and the number of stages of the variable delay circuit can be changed by selecting one of these outputs. I can do it.

  FIG. 9 shows a circuit diagram of an embodiment of the charge pump circuit included in the DLL analog unit 3. In the charge pump circuit of this embodiment, in order to shorten the DLL lock-in cycle, a ΔDelay small-mode current source including a P-channel MOSFET Q11 to which the signal ENB is supplied to the gate is supplied, and the signal TURBO is supplied to the gate. ΔDelay medium mode current source composed of an N-channel MOSFET Q22, ΔDelay large mode current source composed of a P-channel MOSFET Q21 whose gate is supplied with a signal TURBO1B, and a current mirror bias Q12 for transmitting the current of the ΔDelay small mode current source. To Q20 and bidirectional switches Q23 to Q26.

  When the signal ENB is at high level and the ENT is at low level, the switch MOSFETs Q15 and Q16 are turned off and the switch MOSFETs Q17 and Q18 are turned on when the DLL is not operating. The operation of the circuit is stopped and a low power consumption operation is performed. At this time, MOSFETs Q22 and Q21 are turned off by signals TURBO and TURBO1B. The high-speed lock-in cycle operation using these three ΔDelay small mode current source, ΔDelay medium mode current source, and ΔDelay large mode current source will be described later with reference to waveform diagrams.

  FIG. 10 shows a circuit diagram of an embodiment of an output amplifier included in the DLL analog unit 3. Since the output signal of the variable delay circuit using the differential inverter as shown in FIG. 8 has a small amplitude instead of VDD, the amplitude must be amplified to the full amplitude of the operating voltage such as VDD. For this purpose, an output amplifier 305 is required. The output amplifier is composed of two combinations of a current mirror amplifier composed of MOSFETs Q30 to Q35 and a clocked inverter composed of MOSFETs Q37 to Q40. When the control signal ENT = VDD and ENB = 0 (VSS or GND), the current mirror amplifier operates and the output becomes valid, but when ENT = 0 and ENB = VCC, the current mirror amplifier does not operate. The output becomes high impedance.

  In FIG. 2, the outputs of the six output amplifiers are connected in common, but only one of the six output amplifiers is an effective output by the signals ENT and ENB as described above. It is also used to switch the number of stages of the variable delay circuit together with the signal amplification.

  FIG. 11 shows a circuit diagram of an embodiment of a control voltage fixing circuit included in the DLL analog unit 3. When measuring the control voltage-delay amount characteristic of the variable delay circuit as described above, the value of the control voltage must be given from the outside. The control voltage may be fixed from the outside with a probe, but if it can be measured without a probe, a large-scale device is not required, and measurement according to actual conditions (packaging, mounting, etc.) can be performed. There is an advantage that noise is not mixed.

  The control voltage fixing circuit includes switch MOSFETs Q50 to Q52, a voltage dividing resistor circuit, and a bidirectional switch. When the ON signal becomes VDD, the MOSFET Q52 is turned on, a current flows through the series resistance circuit, and voltages V0 to V6 appear due to resistance voltage division. Only one of the signals SET0-6 is set to a high level such as VDD, one of the bidirectional switches is turned on, and the voltages V0 to V6 are connected to the control voltage VB so that a variable delay circuit is provided. The control voltage VB can be fixed.

  FIG. 12 is a waveform diagram for explaining an example of the operation of the clock generation circuit according to the present invention. When the DLL is reset, the initial phase error is made to advance in phase. For this reason, charge-down control in the large ΔDelay mode is started. In this ΔDelay large mode, since the phase error is advanced, the phase comparison output becomes high level, and two charge-up control signals are formed for one phase comparison operation. By this charge-up control signal, the phase error changes sharply toward the target value.

In other words, referring to the circuit of FIG. 9, the signal TURBO1B is at a low level, and the P-channel MOSFET Q21 that flows a large current is turned on. Therefore, the high level of the down signal DOWN and DOWN Due to the low level of B, the N-channel MOSFET Q24 and the P-channel MOSFET Q26 are turned on, and the signals DOWN and DOWN In response to B, the control voltage VB is increased stepwise. As the control voltage VB increases as described above, the current formed by the P-channel MOSFET Q9 in FIG. 8 decreases, the operating current of the differential inverter constituting the variable delay circuit decreases, and the delay time increases. Change the direction to delay the advance of the phase.

  When the phase error exceeds the target phase error of 0, the mode is switched to the medium delay mode. Since the ΔDelay large mode is only charge-down control, only the charge-up control is performed in the ΔDelay medium mode. Therefore, unlike the embodiment of FIG. 9, the ΔDelay large mode charge-up current source and the ΔDelay medium mode charge-down current source are not prepared. Of course, depending on how the initial phase error is given, both may be required. In that case, it is necessary to prepare them.

Referring to the circuit of FIG. 9, in order to correct the phase error delayed beyond the delay error 0 by the ΔDelay large mode, the signal TURBO goes high and the N-channel MOSFET Q22 that passes a medium current is turned on. To be. Therefore, in order to correct the delay, the phase comparison output becomes low level, and the high level and UP of the up signal UP formed thereby Due to the low level of B, the N-channel MOSFET Q23 and the P-channel MOSFET Q25 are turned on, and the signals UP and UP In response to B, the control voltage VB is decreased in a stepwise manner. As the control voltage VB decreases as described above, the current formed by the P-channel MOSFET Q9 in FIG. 8 increases, and the delay current is decreased by increasing the operating current of the differential inverter constituting the variable delay circuit. To change the direction to correct the phase delay.

  When the phase error exceeds the target phase error 0 in the ΔDelay medium mode, the mode is switched to the ΔDelay small mode. In the ΔDelay small mode, charge-up control and charge-down control by a small current formed by the MOSFET Q11 are performed corresponding to the phase comparison output. At this time, instead of forming two pulses (UP / DOWN) as in the ΔDelay large mode and ΔDelay medium mode, one pulse is generated for one phase comparison result. Thereby, in the ΔDelay small mode, the error with respect to the phase error 0 is made as small as possible.

  In this embodiment, there are current sources and bias circuits that are not required depending on the mode, such as the large ΔDelay mode and the middle ΔDelay mode as described above, so the TURBO signal, the TURBO_B signal, the TURBO1 signal, the TURBO1_B signal, the ENT signal, The circuit is turned on and off by the ENB signal. The signal values in each mode are as follows. The power-off mode is a mode in which the operation of the charge pump is stopped to suppress current consumption.

TURBO TURBO_B TURBO1 TURBO1_B ENT ENB
Large mode VDD 0 VDD 0 VDD 0
Medium mode VDD 0 0 VDD VDD 0
Small mode 0 VDD 0 VDD VDD 0
Off mode 0 VDD 0 VDD 0 VDD

  In the DLL of this embodiment, since the variable delay circuit is set to the minimum delay time immediately after resetting, the initial phase error always comes out to the advance side. In order to quickly bring the initial phase error immediately after reset to the vicinity of the phase error 0, the large ΔDelay mode is set to take a large phase control amount ΔDelay from the phase comparison time to the next phase comparison time. Furthermore, in order to increase the phase control amount, not only the charge pump current is increased, but the number of times of control is set to two. Since the initial phase error appears on the advance side, the output of the phase comparator is at a high level such as VDD. ΔDelay When the control is performed several times in the large mode, the phase error exceeds 0 and overshoots. At the next phase comparison time after overshoot, the output of the phase comparator changes to zero. At this time, a transition is made from the large ΔDelay mode to the medium ΔDelay mode.

  In ΔDelay medium mode, the charge pump current is slightly reduced to operate without changing the number of controls. If the control is performed several times in the ΔDelay medium mode, the phase error again exceeds 0 and undershoots this time. At the next phase comparison time undershooted, the output of the phase comparator changes to VDD. At this time, the mode shifts from the medium delay mode to the small delay mode. ΔDelay In the small mode, the charge pump current is reduced and the number of controls is reduced to one. As a result, the delay control amount in one phase comparison becomes the minimum setting. In the ΔDelay small mode, after the phase error exceeds 0, the charge-down control signal and the charge-up control signal are output almost alternately, and the phase error oscillates near 0. This state is a lock-in state. Therefore, if attention is paid only to the output waveform of the phase comparator, the lock-in cycle is from the DLL reset until the phase comparator output changes from VDD to 0 twice.

  In this embodiment, a new driving method in a charge pump which is an analog control circuit is shown. The dead zone, which is a disadvantage of the PFD that is a conventional driving method, can be eliminated, and the lock-in cycle can be shortened. In the dead zone, the phase comparator determines only the phase advance and delay, and the control voltage VB is changed as described above by the phase comparison output. As a result, the delay amount is reversed when the phase error exceeds the target value of zero. This is realized by a simple control method of changing the direction. Since the dead zone as described above depends on the performance of the transistor and the wiring length, the elimination of such a dead zone facilitates the design independent of the process and layout.

  FIG. 13 is a waveform diagram for explaining an example of the operation of the clock generation circuit according to the present invention. In this embodiment, the state during lock-in in the constant ΔDelay method is shown. In FIG. 12, it has been described that the charge-down control signal and the charge-up control signal are output almost alternately. Since the charge pump is an analog circuit, the charge-up amount and the charge-down amount cannot be exactly matched. Therefore, ΔDelay (Down) and ΔDelay (Up) have a slight imbalance as shown in the figure. This imbalance increases the phase error with time, and finally one of the control signals is output twice in succession (control signal output twice in succession). Therefore, the magnitude of jitter is 2 × ΔDelay. In the example of the figure, the case of ΔDelay (Down)> ΔDelay (Up) is taken up, but the reverse case is also the same.

FIG. 14 is a state transition diagram of the state control circuit included in the clock generation circuit according to the present invention. The state control circuit 403 is included in the DLL digital circuit section of FIG. 7 and forms signals TRBO and TRBO1 supplied to the DLL analog section 3. When DLL_EN = 0V (VSS), it enters the state in which DLL is stopped, and when DLL_EN = VDD, the phase comparison output EARLY output from the phase comparator 402 The following state control is performed by looking at the change in INT.

ΔDelay large mode TURBO = VDD TURBO1 = VDD
Mode during ΔDelay TURBO = VDD TURBO1 = 0
ΔDelay small mode TURBO = 0 TURBO1 = 0

  FIG. 15 shows a circuit diagram of an embodiment of the phase comparator and state control circuit. The phase comparator 402 may be a general flip-flop circuit as shown in the figure. If the internal clock signal ICLK4 rises before the external clock signal ECLK4, VDD is output as the phase comparison output EARLY_INT. If the external clock signal ELCK4 rises before the internal clock signal ICLK4, the phase comparison output EARLY_INT is 0 (low level). Is output.

  In the state control, when the DLL_EN signal is 0, all flip-flop circuits are set to VDD (high level). Thereafter, every time EARLY_INT changes, the outputs Q of the flip-flop circuits FF2 to FF4 sequentially become 0, and the TURBO signal and the TURBO1 signal are output. If the last LOCK signal becomes VDD, it can be determined that the DLL has shifted to the locked state.

  FIG. 16 shows a circuit diagram of an embodiment of the pulse generating circuit. The pulse generation circuit 404 is a circuit that generates an UP signal and a DOWN signal based on the phase comparison output EARLY_INT signal. The pulse generation circuit 404 can output with a stable pulse width by synchronizing with ECLK_T, but cannot output a pulse shorter than the clock cycle. ECLK2 is a signal obtained by dividing ECLK_T by two.

  FIG. 17 shows a circuit diagram of another embodiment of the pulse generating circuit. In this embodiment, the delay circuit is used to output an arbitrary pulse width. The pulse width is designed to be “phase difference + 3.0 ns” because the pull-in of the initial phase error is delayed with a pulse having a very narrow width. In the pulse generation circuit of this embodiment, ΔDelay is not constant, but the main point of the constant ΔDelay control is that there is no problem because ΔDelay ≠ 0 even at the phase difference = 0.

  FIG. 18 shows a circuit diagram of an embodiment of the divide-by-4 circuit. The divide-by-4 circuit of this embodiment is of a 1ck lock 2ck lock switching type. Since the DLL of this embodiment employs 2ck lock, it is necessary to prevent harmonic lock by dividing ECLK_T and ICLK by 4 before performing phase comparison. Therefore, if the phases of ECLK_T and ICLK are the same, the reset is performed so that the phase of ICLK4 advances by 720 ° from ECLK4.

  Thereafter, by delaying the phase of ICLK by 720 ° (2 ck) with the variable delay circuit and the replica circuit (Replica Delay), ECLK4 and ICLK4 are in phase and locked. At this time, if the phase advance of ICLK4 is 360 ° instead of 720 °, 1ck lock is performed. Therefore, 1ck lock and 2ck lock can be performed by one circuit. Unlike a general flip-flop circuit, the flip-flop circuit used in the above-mentioned quadrant divider has both a set terminal and a reset terminal. The phase immediately after the reset signal falls can be changed by the 1CK_LOCK signal. The change in phase immediately after reset due to the change in 1CK_LOCK is as follows.

CK_LOCK value Phase of ECLK4 Phase of ICLK4 0 0 ° -720 °
10 ° -360 °

  FIG. 19 is a circuit diagram showing one embodiment of the charge pump test pulse generating circuit. It is difficult for an analog control type DLL to test the state of an internal circuit from the outside as compared with a digital control type. One of the difficulties is the operation of the charge pump. A pulse generation circuit is required to test how much the delay amount of the variable delay circuit changes when the charge pump operates once. The charge pump test pulse generation circuit is a circuit that outputs the number of pulses CP_PULSE (width is tCK / 2) set by CP_SET0-3. By operating the charge pump with this pulse, it is possible to test the operation of the charge pump with CP_SET0-3 which is an external setting. The output of CP_PULSE starts when the signal PULSEEN goes high.

  FIG. 20 is a plan view of one embodiment showing the relationship between the memory chip and the lead frame in the semiconductor integrated circuit device according to the present invention. The memory chip has several VDD and VSS pads. DLL, VSS DLL is one of them. However, VDD DLL, VSS A dedicated bonding pad and lead frame are assigned to the DLL to prevent noise from entering the power supply wiring.

  FIG. 21 is a circuit diagram showing one embodiment of the electrostatic protection circuit in the semiconductor integrated circuit device according to the present invention. In this embodiment, as described above, dedicated pads VDD_DLL and VSS_DLL for supplying an operating voltage to the DLL such as a variable delay circuit are provided. The following elements are provided as ESD countermeasures for these dedicated pads VDD_DLL and VSS_DLL.

A diode D70 and a diode-connected MOSFET Q70 are provided in parallel between the VDD_DLL pad and the VSS wiring, and diode-shaped MOSFETs Q71 and Q72 are provided in parallel between the VDD wiring. Similarly, VSS For the DLL pad, diodes D72 and D73 are provided in parallel between the VSS wiring and a diode-shaped MOSFET Q73 and diode D71 are provided in parallel between the VDD wiring.

  As described above, in the semiconductor integrated circuit device, an electrostatic protection circuit is provided in order to prevent internal elements from being destroyed by static electricity generated when the device is transported or handled during assembly. Accordingly, the power supply pads VDD_DLL and VSS_DLL, which are independently formed as described above, via the electrostatic protection circuit are also broadly or formally electric in terms of VDD and VSS that supply operating voltages to other internal circuits. It can be said that it is connected to.

  However, these electrostatic protection circuits cannot be said to be electrically connected because no current flows in the normal operation state of the semiconductor integrated circuit device. That is, the power supply noise generated in the VDD and VSS and the voltage variation thereof are not transmitted to the VDD_DLL and VSS_DLL. Therefore, when viewed from the operation of the clock generation circuit according to the present invention, it can be said that the VDD and VSS are electrically separated from the VDD_DLL and VSS_DLL.

The effects obtained from the above embodiment are as follows.
(1) The phase of the signal formed on the basis of a delay signal that has passed through a variable delay circuit that receives an input clock signal input from an external terminal and the input clock signal are compared, and the variable delay is set so that they match. In a semiconductor integrated circuit device having a clock generation circuit including a control circuit for controlling a delay time of the circuit to form an internal clock signal, the variable delay circuit and its delay control signal are formed in the clock generation circuit. Changes in the substrate potential caused by the operation of the digital circuit by electrically separating the element formation region constituting the circuit from the element formation region constituting the digital circuit formed on the same semiconductor substrate by an element isolation technique Thus, it is possible to realize a highly accurate phase synchronization by a delay operation without obtaining the influence of the above.

(2) In addition to the above, each of the variable delay circuit and the charge pump circuit is formed on the well region of the second conductivity type formed at a deep depth on the common semiconductor substrate of the first conductivity type. By using a triple well element isolation technique that is formed in each well region of the first conductivity type or the second conductivity type formed to a shallow depth, it can be realized by a simple manufacturing process.

(3) In addition to the above, by operating the variable delay circuit and the charge pump circuit with an operating voltage via a dedicated bonding pad and leads different from the power supply terminal that supplies the operating voltage supplied to the digital circuit. Further, it is possible to achieve higher accuracy by a more stable delay operation of the variable delay circuit without being affected by noise and voltage fluctuations from the power supply path.

(4) In addition to the above, a MOS capacitance element is formed in the periphery of the second conductivity type well region formed at the deep depth, and is used as a stabilization capacitor for the operating voltage, thereby providing a semiconductor integrated circuit device. Further, it is possible to absorb noise through a common power supply line on the mounting board side on which is mounted, so that higher accuracy can be realized by a more stable delay operation of the variable delay circuit.

(5) In addition to the above, a clock input buffer for capturing an input clock signal input to the variable delay circuit, and a clock output buffer for outputting a delay signal are further provided, and the clock input buffer and the clock output buffer are provided. By forming on the well region of the second conductivity type formed at the deep depth, the variable delay circuit and its delay control signal are not affected by the noise included in the signal transmission path, and more stable. Higher accuracy can be realized by the delay operation of the variable delay circuit.

(6) In addition to the above, the first divider circuit that divides the input clock signal is reset at the start of the operation of the clock generation circuit, and the second divider circuit that divides the internal clock signal is selectively By giving a predetermined initial value, it is possible to select either a clock signal delayed by two clocks or a clock signal delayed by one clock of the external clock which takes phase synchronization.

(7) In addition to the above, the first and second frequency divider circuits, the replica delay circuit, and the phase comparison circuit are formed in the element formation region in which the variable delay circuit and the circuit that forms the delay control signal are formed. By forming it in an electrically isolated element formation region, it is possible to prevent power noise generated in a digital circuit operating at full amplitude from being transmitted to the analog circuit part, and more stable variable delay Higher precision can be realized by the delay operation of the circuit.

(8) In addition to the above, a plurality of word lines each having a plurality of dynamic memory cell address selection terminals connected thereto and a plurality of pairs of complementary memory cells each having a plurality of dynamic memory cells connected to each other. The clock generation circuit is provided in a dynamic RAM including a bit line pair and a sense amplifier including a plurality of latch circuits each of which is supplied with an operation voltage corresponding to an operation timing signal and amplifies the signal of the complementary bit line pair. A dedicated bonding pad and lead different from the power supply terminal for supplying the operating voltage to be supplied to the sense amplifier are provided for the variable delay circuit and the circuit for forming the delay control signal that are included in the clock generation circuit. Is affected by large noise from the sense amplifier. Ku, it is possible to realize a further higher accuracy by delay operation stable variable delay circuit.

(9) The phase of the signal formed based on the delay signal of the variable delay circuit that delays the input clock signal input from the external terminal and the input clock signal are compared, and the variable delay circuit is set so that they match. In a semiconductor integrated circuit device including a clock generation circuit having a control circuit for controlling the delay time and forming an internal clock signal, at least the variable delay circuit among the clock generation circuits is a digital signal formed on the same substrate. By providing dedicated bonding pads and leads that are different from the circuit's operating voltage supply path and supplying the operating voltage, it is possible to stably delay operation without being affected by changes in the power supply voltage generated by the operation of the digital circuit. High-precision phase synchronization can be realized.

(10) In addition to the above, a plurality of word lines each having a plurality of dynamic memory cell address selection terminals connected thereto and a plurality of pairs of complementary memory cells each having a plurality of dynamic memory cells connected thereto The clock generation circuit is provided in a dynamic RAM including a bit line pair and a sense amplifier including a plurality of latch circuits each of which is supplied with an operation voltage corresponding to an operation timing signal and amplifies the signal of the complementary bit line pair. By mounting and supplying an operating voltage to at least the variable delay circuit of the clock generating circuit by providing a dedicated bonding pad and lead different from the power supply terminal that supplies the operating voltage supplied to the sense amplifier, Stable variable delay circuit without being affected by large noise from the sense amplifier It is possible to realize a further higher accuracy by extending operation.

(11) In addition to the above, the digital circuit further includes an input circuit for receiving an input signal supplied from an external terminal and an output circuit for sending an output signal to the external terminal. A dedicated bonding pad and lead different from the power supply terminal for supplying the operating voltage supplied to the clock generating circuit and the sense amplifier are provided to supply the operating voltage, thereby enabling the clock generating circuit and the sense amplifier to be supplied. Each of the delay operations and the sense amplifier operations of the stable variable delay circuit can be performed without being affected by large noise from the output circuit.

(12) The delay signal of the variable delay circuit that delays the input clock signal input from the external terminal and the input clock signal are phase-compared by the phase comparison circuit, and the delay time of the variable delay circuit is set so that they match. And a control circuit that controls the internal clock signal to control the control circuit, and the control circuit returns the delay amount in the reverse direction when the variable delay time exceeds a target value. By controlling the variable delay circuit, it is possible to eliminate the dead zone, which is a disadvantage of the conventional drive method PFD. By eliminating this dead zone, the phase error is not affected by transistor performance and wiring length, and design is easy. Can be.

(13) In addition to the above, by making the change amount of the delay time of the variable delay circuit for each phase comparison operation by the phase comparison circuit substantially constant, the phase error in the lock-in state can be doubled up to the maximum. Can be made smaller.

(14) By changing the amount of change in the delay time of the variable delay circuit for each phase comparison operation by the phase comparison circuit in accordance with the operation state, optimum responsiveness and stability according to each operation state The effect that can be realized is obtained.

(15) In addition to the above, the change amount of the delay time of the variable delay circuit is large in the first period from the start of the operation of the clock generation circuit to exceeding the target value, and the delay time from the first period to the target value In the second period until it becomes smaller, it is smaller than the amount of change in the delay time in the first period, and after the second period, it is set smaller than the second period, thereby locking from the beginning of the DLL operation. Stabilization in the lock-in state can be achieved while shortening the lock-in cycle leading to in.

(16) In addition to the above, the amount of change in the delay time of the variable delay circuit is reduced every time the delay time of the variable delay circuit exceeds the target value within a range that does not impair the phase synchronization operation. While improving, stabilization in the lock-in state can be achieved.

(17) In addition to the above, the phase comparison circuit forms a high-level or low-level phase comparison signal corresponding to the phase difference, and a charge-up current is supplied to the charge pump circuit corresponding to the phase comparison signal. Alternatively, by forming a pulse signal for causing a discharge current to flow, the responsiveness can be switched by the output pulse of the pulse generation circuit while simplifying the circuit.

(18) In addition to the above, the delay time amount of the variable delay circuit can be set to a desired response flexibly by a simple circuit by combining the number of the pulse signals and the charge current value of the charge pump circuit by the pulse signals. The stability can be achieved while realizing the performance.

  The invention made by the inventor has been specifically described based on the embodiments. However, the invention of the present application is not limited to the embodiments, and various modifications can be made without departing from the scope of the invention. Nor. For example, the DLL may be a digital control digital DLL or a digital control analog DLL. Even in these variable delay circuits of DLL, when the power supply voltage changes, the voltage supplied to the gate of the MOSFET changes correspondingly, so that the flowing current changes, and when the substrate voltage changes, the MOSFET is caused by the substrate effect. The threshold voltage of each of the transistors changes, causing each drain current to fluctuate. Therefore, by applying the present invention, even in these DLLs, the variable delay circuit and its control signal can be stabilized, so that the jitter of the output clock signal can be reduced.

  The technology for electrically separating the variable delay circuit constituting the DLL and the circuit forming the control signal from other digital circuits may use an SOI (Silicon On Insulator) structure.

  With the increase in the speed of semiconductor integrated circuit devices, the frequency of clock signals has been increased, and one clock cycle becomes increasingly shorter. Therefore, reducing the jitter, which is the phase fluctuation of the clock signal, reduces the time margin included in one clock cycle, which is a very useful technique for increasing the clock frequency.

  The clock generation circuit according to the present invention is widely used in various digital semiconductor integrated circuit devices having a clock input circuit (or reproduction circuit) in addition to the synchronous DRAM as described above and having a synchronous input / output. it can.

1 is a schematic layout diagram showing one embodiment of a dynamic RAM to which the present invention is applied. It is a layout figure which shows one Example of a DLL analog part. 1 is a schematic element structure sectional view showing an embodiment of a semiconductor integrated circuit device according to the present invention; 1 is a schematic element structure sectional view showing an embodiment of a semiconductor integrated circuit device according to the present invention; It is a schematic element structure sectional view showing other examples of a semiconductor integrated circuit device concerning this invention. 1 is an overall block diagram showing an embodiment of a synchronous DRAM to which the present invention is applied. It is a whole block diagram which shows one Example of DLL which concerns on this invention. It is a circuit diagram which shows one Example of the variable delay circuit contained in a DLL analog part. It is a circuit diagram which shows one Example of the charge pump circuit contained in a DLL analog part. It is a circuit diagram which shows one Example of the output amplifier contained in a DLL analog part. It is a circuit diagram which shows one Example of the control voltage fixing circuit contained in a DLL analog part. It is a waveform diagram for explaining an example of the operation of the clock generation circuit according to the present invention. It is a waveform diagram for explaining an example of the operation of the clock generation circuit according to the present invention. It is a state transition diagram of a state control circuit included in the clock generation circuit according to the present invention. A circuit diagram showing an embodiment of the DLL phase comparator and state control circuit is shown. It is a circuit diagram which shows one Example of the said pulse generation circuit of DLL. It is a circuit diagram which shows another Example of the said pulse generation circuit of DLL. It is a circuit diagram which shows one Example of the said 4 frequency dividing circuit of DLL. It is a circuit diagram which shows one Example of the charge pump test pulse generation circuit of the said DLL. 4 is a plan view illustrating the relationship between the memory chip and the lead frame in the semiconductor integrated circuit device according to the present invention. FIG. 1 is a circuit diagram showing one embodiment of an electrostatic protection circuit in a semiconductor integrated circuit device according to the present invention. FIG.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Memory cell array, 2 ... Sense amplifier, 3 ... DLL analog part, 4 ... DLL digital part, 5 ... Dedicated bonding pad, 6, 11, 13 ... Bonding pad row, 7 ... Data output circuit, 8 ... DQS buffer, 9 ... replica circuit, 10 ... data input circuit, 12 ... peripheral circuit,
301 ... Input buffer 302 ... CLK input buffer 303 ... Variable delay circuit 304 ... CLK output buffer 305 ... Output amplifier 306 ... PMOS capacitor 307 ... Charge pump
200A to D ... Memory array, 201A to D ... Row decoder, 202A to D ... Sense amplifier, 203A to D ... Column decoder, 204 ... Address buffer, 205 ... Row address buffer, 206 ... Column address buffer, 207 ... Column address counter 208 ... Refresh counter 209 ... Control circuit 210 ... Data input circuit 211 ... Data output circuit 212 ... Bank select circuit 213 ... Mode register 214 ... DLL 214 ... DQS buffer 401 ... 4 frequency divider circuit 402 ... Phase comparator, 403 ... State control circuit, 404 ... Pulse generation circuit, 405 ... Charge pump pulse generation circuit, 2091 ... Clock input circuit.

Claims (42)

A dynamic semiconductor memory device including a semiconductor chip including a DLL circuit and a clock generation circuit for generating a clock signal, and an internal circuit whose operation is controlled by the clock signal,
The semiconductor chip is
A first power supply pad coupled to the clock generation circuit for supplying a first power supply potential to the clock generation circuit;
A second power supply pad coupled to the clock generation circuit for supplying a second power supply potential having a potential lower than the first power supply potential to the clock generation circuit;
A third power supply pad coupled to the internal circuit for supplying the third power supply potential to the internal circuit;
A fourth power supply pad coupled to the internal circuit and for supplying a fourth power supply potential having a potential lower than the third power supply potential to the internal circuit;
The dynamic semiconductor memory device is
A first terminal coupled to the first power pad;
A second terminal coupled to the second power pad;
A third terminal coupled to the third power pad and different from the first terminal;
A dynamic semiconductor memory device having a fourth terminal coupled to the fourth power supply pad and different from the second terminal. In claim 1,
The internal circuit is
A plurality of word lines, a plurality of data lines, a plurality of dynamic memory cells coupled to the plurality of word lines and the plurality of data lines;
A plurality of sense amplifiers respectively coupled to the plurality of data lines;
A data output circuit coupled to the outputs of the plurality of sense amplifiers;
The data output circuit outputs a signal read from the dynamic memory cell to the outside of the dynamic semiconductor memory device in synchronization with both rising and falling of the clock signal generated from the clock generating circuit. A dynamic semiconductor memory device characterized in that the output is output. In claim 2,
The internal circuit further includes
A strobe signal output circuit for generating a data strobe signal in synchronization with the data output from the data output circuit;
The dynamic semiconductor memory device, wherein the strobe signal output circuit operates in response to the clock signal generated from the clock generation circuit. In claim 1,
The clock generator circuit
A delay circuit for receiving a first clock signal and outputting a second clock signal obtained by delaying the first clock signal by a predetermined delay time;
A phase comparison circuit that compares the phase of the third clock signal formed based on the second clock signal and the first clock signal and outputs a control signal;
A control circuit for controlling the delay circuit so that the phase of the first clock signal and the phase of the third clock signal coincide with each other based on the control signal;
The internal circuit is controlled in operation by the second clock signal,
The dynamic semiconductor memory device, wherein the delay circuit is coupled to the first power supply pad and the second power supply pad. In claim 4,
2. The dynamic semiconductor memory device according to claim 1, wherein the first and third power supply potentials are substantially equal, and the second and fourth power supply potentials are substantially equal. Double data rate synchronous dynamic random comprising a semiconductor chip having a clock generation circuit using a DLL including a delay circuit and an internal circuit whose operation is controlled by a clock signal generated from the clock generation circuit Access memory,
The internal circuit is
A plurality of word lines, a plurality of data lines, a plurality of dynamic memory cells coupled to the plurality of word lines and the plurality of data lines;
A plurality of sense amplifiers respectively coupled to the plurality of data lines;
The signal read from the dynamic memory cell is synchronized with both the rising edge and the falling edge of the clock signal generated from the clock generation circuit coupled to the outputs of the plurality of sense amplifiers. A data output circuit that outputs to the outside of the dynamic random access memory;
A DQS output circuit that operates in response to the clock signal generated from the clock generation circuit and generates a data strobe signal in synchronization with the data output from the data output circuit;
The semiconductor chip is
A first pad for supplying a power supply voltage to the delay circuit;
A second pad for supplying a ground voltage to the delay circuit;
A third pad different from the first pad for supplying a power supply voltage to the data output circuit;
A fourth pad different from the second pad for supplying a ground voltage to the data output circuit;
The double data rate synchronous dynamic random access memory is
A first terminal coupled to the first pad;
A second terminal coupled to the second pad;
A third terminal coupled to the third pad and different from the first terminal;
A double data rate synchronous dynamic random access memory coupled to the fourth pad and having a fourth terminal different from the second terminal. In claim 6,
The clock generator circuit
The delay circuit receiving a first clock signal and outputting a second clock signal obtained by delaying the first clock signal by a predetermined delay time;
A phase comparison circuit that compares the phase of the third clock signal formed based on the second clock signal and the first clock signal and outputs a control signal;
A control circuit for controlling the delay circuit so that the phase of the first clock signal and the phase of the third clock signal coincide with each other based on the control signal;
The internal circuit is controlled in operation by the second clock signal as the clock signal,
The double data rate synchronous dynamic random access memory, wherein the delay circuit is coupled to the first pad and the second pad. A double data rate synchronous dynamic random access memory comprising a semiconductor chip comprising a clock generation circuit and an internal circuit whose operation is controlled by a clock signal generated from the clock generation circuit,
The internal circuit is
A plurality of word lines, a plurality of data lines, a plurality of dynamic memory cells coupled to the plurality of word lines and the plurality of data lines;
A plurality of sense amplifiers respectively coupled to the plurality of data lines;
The signal read from the dynamic memory cell is coupled to the outputs of the plurality of sense amplifiers and synchronized with both rising and falling edges of the clock signal generated from the clock generation circuit. A data output circuit for outputting to the outside of the dynamic random access memory;
A DQS output circuit that operates in response to the clock signal generated from the clock generation circuit and generates a data strobe signal in synchronization with the data output from the data output circuit;
The clock generator circuit
A delay circuit for receiving a first clock signal and outputting a second clock signal which is the clock signal obtained by delaying the first clock signal by a predetermined delay time;
A phase comparison circuit that compares the phase of the third clock signal formed based on the second clock signal and the first clock signal and outputs a control signal;
A control circuit that controls the delay circuit based on the control signal so that the phase of the first clock signal and the phase of the third clock signal coincide with each other;
The semiconductor chip is
A first power supply pad for supplying a first power supply potential to the delay circuit;
A second power supply pad for supplying a second power supply potential different from the first power supply potential to the delay circuit;
A third power supply pad for supplying a third power supply potential to the data output circuit;
A fourth power supply pad for supplying a fourth power supply potential different from the third power supply potential to the data output circuit;
The double data rate synchronous dynamic random access memory is
A first terminal coupled to the first power pad;
A second terminal coupled to the second power pad;
A third terminal coupled to the third power pad and different from the first terminal;
A fourth terminal coupled to the fourth power pad and different from the second terminal;
The first power supply path to the delay circuit is the first terminal, the first power pad, the second power pad, and the second terminal.
The second power supply path to the internal circuit is the third terminal, the third power pad, the fourth power pad, and the fourth terminal different from the first power supply path. Double data rate synchronous dynamic random access memory. In claim 8,
The connection between the first terminal and the first power supply pad is connected via a first wire,
The connection between the second terminal and the second power supply pad is connected via a second wire,
The connection between the third terminal and the third power supply pad is connected via a third wire,
The double data rate synchronous dynamic random access memory is characterized in that the fourth terminal and the fourth power supply pad are connected via a fourth wire. A double data rate synchronous dynamic random access memory comprising a semiconductor chip comprising an internal circuit whose operation is controlled by a clock signal generated from a clock generation circuit;
The internal circuit is
A plurality of word lines, a plurality of data lines, a plurality of dynamic memory cells coupled to the plurality of word lines and the plurality of data lines;
A plurality of sense amplifiers respectively coupled to the plurality of data lines;
Coupled to the outputs of the plurality of sense amplifiers, in synchronization with both rising and falling edges of the clock signal generated from the clock generation circuit, amplifies the signal read from the dynamic memory cell and A data output circuit for outputting to the outside of the synchronous dynamic random access memory;
A data input circuit for receiving data to be written to the dynamic memory cell from the outside of the synchronous dynamic random access memory;
A DQS output circuit that operates in response to the clock signal generated from the clock generation circuit and generates a data strobe signal in synchronization with the data output from the data output circuit;
The clock circuit
The delay circuit for receiving a first clock signal and outputting a second clock signal which is the clock signal obtained by delaying the first clock signal by a predetermined delay time;
A phase comparison circuit that compares the phase of the third clock signal formed based on the second clock signal and the first clock signal and outputs a control signal;
A control circuit that controls the delay circuit based on the control signal so that the phase of the first clock signal and the phase of the third clock signal coincide with each other;
The semiconductor chip is
A first power supply pad for supplying a first power supply potential to the delay circuit;
A second power supply pad for supplying a second power supply potential different from the first power supply potential to the delay circuit;
A third power supply pad for supplying a third power supply potential to the data output circuit;
A fourth power supply pad for supplying a fourth power supply potential different from the third power supply potential to the data output circuit;
The double data rate synchronous dynamic random access memory is
A first terminal coupled to the first power pad;
A second terminal coupled to the second power pad;
A third terminal coupled to the third power pad and different from the first terminal;
A double data rate synchronous dynamic random access memory coupled to the fourth power pad and having a fourth terminal different from the second terminal. In claim 10,
The connection between the first terminal and the first power supply pad is connected via a first wire,
The connection between the second terminal and the second power supply pad is connected via a second wire,
The connection between the third terminal and the third power supply pad is connected via a third wire,
The double data rate synchronous dynamic random access memory is characterized in that the fourth terminal and the fourth power supply pad are connected via a fourth wire. In claim 11,
The first power supply path to the delay circuit is the first terminal, the first wire, the first power pad, the second power pad, the second wire, and the second terminal.
The second power supply path to the internal circuit is different from the first power supply path in the third terminal, the third wire, the third power pad, the fourth power pad, the fourth wire, and the fourth wire. A double data rate synchronous dynamic random access memory characterized by being a terminal. A double data rate synchronous dynamic random access memory comprising a semiconductor chip,
The semiconductor chip is
A delay circuit that receives the first clock signal and outputs a second clock signal obtained by delaying the first clock signal by a predetermined delay time; a third clock signal formed based on the second clock signal; and the first clock signal A phase comparison circuit that compares the phase of the clock signal and outputs a control signal; and a control that controls the delay circuit so that the phase of the first clock signal and the phase of the third clock signal coincide with each other based on the control signal A clock generation circuit including a circuit;
A memory array including a dynamic memory cell, a word line coupled to the dynamic memory cell, and a data line coupled to the dynamic memory cell;
A sense amplifier coupled to the data line;
The signal read from the dynamic memory cell is amplified by being coupled to the output of the sense amplifier and in synchronization with both rising and falling edges of the second clock signal generated from the clock generation circuit. A data output circuit for outputting to the outside of the double data rate synchronous dynamic random access memory;
A data input circuit for receiving data to be written to the dynamic memory cell from outside the double data rate synchronous dynamic random access memory;
A DQS output circuit that operates in response to the second clock signal generated from the clock generation circuit and generates a data strobe signal in synchronization with a data output from the data output circuit;
A first pad for supplying a first power supply potential to the delay circuit;
A second pad for supplying a second power supply potential different from the first power supply potential to the delay circuit;
A third pad for supplying a third power supply potential to the data output circuit;
A fourth pad for supplying a fourth power supply potential different from the third power supply potential to the data output circuit;
The double data rate synchronous dynamic random access memory is
A first terminal coupled to the first pad;
A second terminal coupled to the second pad;
A third terminal coupled to the third pad and different from the first terminal;
The double data rate synchronous dynamic random access memory according to claim 1, wherein the double data rate synchronous dynamic random access memory is coupled to the fourth pad and has a fourth terminal different from the second terminal. In claim 13,
The pad rows of the first pad, the second pad, the third pad, and the fourth pad are disposed in a central portion along one direction of the semiconductor chip,
The memory array is disposed between the pad row and one side corresponding to one direction of the semiconductor chip, and between the pad row and another side corresponding to one direction of the semiconductor chip,
The data input circuit, the data output circuit, and the DQS output circuit are disposed between the pad row and the one side of the semiconductor chip, and are a double data rate synchronous dynamic type Random access memory. In claim 14,
The connection between the first terminal and the first pad is connected via a first wire,
The connection between the second terminal and the second pad is connected via a second wire,
The connection between the third terminal and the third pad is connected via a third wire,
The double data rate synchronous dynamic random access memory is characterized in that the fourth terminal and the fourth pad are connected via a fourth wire. A semiconductor memory circuit device,
A delay circuit that receives the first clock signal and outputs a second clock signal obtained by delaying the first clock signal by a predetermined delay time; a third clock signal formed based on the second clock signal; and the first clock signal A phase comparison circuit that compares the phase of the clock signal and outputs a control signal; and a control that controls the delay circuit so that the phase of the first clock signal and the phase of the third clock signal coincide with each other based on the control signal A clock generation circuit including a circuit;
In response to the second clock signal, a plurality of word lines, a plurality of complementary bit line pairs, and a plurality of storage information holding operations connected to the plurality of word lines and the plurality of complementary bit line pairs are required. An internal circuit including a memory cell and a sense amplifier connected to each of the plurality of complementary bit line pairs and amplifying a signal appearing in the plurality of complementary bit line pairs;
A first lead supplied with a first power supply potential which is a first potential from the outside of the semiconductor memory circuit device;
A first supply unit for receiving the first power supply potential supplied to the first lead;
A second lead which is supplied with a second power supply potential, which is a first potential, from the outside of the semiconductor memory circuit device and is different from the first lead;
A second supply unit that receives the second power supply potential supplied to the second lead;
The internal circuit receives the first potential supplied from the first supply unit,
The semiconductor memory circuit device, wherein the delay circuit receives the first potential supplied from the second supply unit. In claim 16,
The semiconductor memory circuit device further includes a third lead supplied with a third power supply potential that is a second potential from the outside of the semiconductor memory circuit device;
A third supply unit for receiving the second power supply potential supplied to the third lead;
A fourth lead supplied from the outside of the semiconductor memory circuit device to a fourth power supply potential, which is a second potential, and different from the third lead;
A fourth supply unit for receiving the second power supply potential supplied to the fourth lead,
The internal circuit receives the second potential supplied from the third supply unit,
The semiconductor memory circuit device, wherein the delay circuit receives the second potential supplied from the fourth supply unit. In claim 17,
2. A semiconductor memory circuit device according to claim 1, wherein an element formation region constituting the delay circuit is separated from an element formation region constituting the internal circuit, the phase comparison circuit, and the control circuit. In claim 17,
The clock generation circuit includes an input circuit that receives an input signal and an output circuit that sends an output signal.
The semiconductor memory circuit device, wherein the input circuit and the output circuit are supplied with the first potential from the second supply unit and supplied with the second potential from the fourth supply unit. A semiconductor memory circuit device,
A delay circuit that receives the first clock signal and outputs a second clock signal obtained by delaying the first clock signal by a predetermined delay time; a third clock signal formed based on the second clock signal; and the first clock signal A phase comparison circuit that compares the phase of the clock signal and outputs a control signal; and a control that controls the delay circuit so that the phase of the first clock signal and the phase of the third clock signal coincide with each other based on the control signal A clock generation circuit including a circuit;
A plurality of word lines and a plurality of pairs of complementary bit lines connected to a plurality of dynamic memory cells in response to the second clock signal; and a sense amplifier for amplifying the signals of the pair of complementary bit lines, respectively. Including an internal circuit,
A first supply unit including a first terminal electrically connectable to the outside of the semiconductor memory circuit device, to which a first power supply potential that is a first potential is supplied from the outside of the semiconductor memory circuit device;
A second power supply potential that is electrically connectable to the outside of the semiconductor memory circuit device and includes a second terminal that is different from the first terminal and that is the first potential is supplied from the outside of the semiconductor memory circuit device. A second supply unit,
The internal circuit receives the first potential supplied from the first supply unit,
The semiconductor memory circuit device, wherein the delay circuit receives the first potential supplied from the second supply unit. In claim 20,
The semiconductor memory circuit device further includes a third terminal that can be electrically connected to the outside of the semiconductor memory circuit device, and is supplied with a third power supply potential that is a second potential from the outside of the semiconductor memory circuit device. 3 supply units;
A fourth power supply potential that is electrically connectable to the outside of the semiconductor memory circuit device and includes a fourth terminal that is different from the third terminal and that is the second potential is supplied from the outside of the semiconductor memory circuit device. A fourth supply unit,
The internal circuit receives the second potential supplied from the third supply unit,
The semiconductor memory circuit device, wherein the delay circuit receives the second potential supplied from the fourth supply unit. In claim 21,
2. A semiconductor memory circuit device according to claim 1, wherein an element formation region constituting the delay circuit is separated from an element formation region constituting the internal circuit, the phase comparison circuit, and the control circuit. In claim 21,
The clock generation circuit includes an input circuit that receives an input signal and an output circuit that sends an output signal.
The semiconductor memory circuit device, wherein the input circuit and the output circuit are supplied with the first potential from the second supply unit and supplied with the second potential from the fourth supply unit. A semiconductor integrated circuit device,
A delay circuit that receives the first clock signal and outputs a second clock signal obtained by delaying the first clock signal by a predetermined delay time; a third clock signal formed based on the second clock signal; and the first clock signal A phase comparison circuit that compares the phase of the clock signal and outputs a control signal; and a control that controls the delay circuit so that the phase of the first clock signal and the phase of the third clock signal coincide with each other based on the control signal A clock generation circuit including a circuit;
An internal circuit responsive to the second clock signal;
A first supply unit including a first terminal electrically connectable to the outside of the semiconductor memory circuit device, to which a first power supply potential that is a first potential is supplied from the outside of the semiconductor memory circuit device;
A second power supply potential that is electrically connectable to the outside of the semiconductor memory circuit device and includes a second terminal that is different from the first terminal and that is the first potential is supplied from the outside of the semiconductor memory circuit device. A second supply unit,
The internal circuit receives the first potential supplied from the first supply unit,
The semiconductor integrated circuit device, wherein the delay circuit receives the first potential supplied from the second supply unit. In claim 24,
The internal circuit includes a plurality of word lines, a plurality of complementary bit line pairs, a plurality of memory cells connected to the plurality of word lines and the plurality of complementary bit line pairs, and the plurality of complementary bit line pairs. A semiconductor integrated circuit device comprising: a sense amplifier which is connected and amplifies a signal of the complementary bit line pair. In claim 25,
The semiconductor integrated circuit device further includes a third terminal that can be electrically connected to the outside of the semiconductor integrated circuit device, and is supplied with a third power supply potential that is a second potential from the outside of the semiconductor memory circuit device. 3 supply units;
A fourth power supply potential that is electrically connectable to the outside of the semiconductor memory circuit device and includes a fourth terminal that is different from the third terminal and that is the second potential is supplied from the outside of the semiconductor memory circuit device. A fourth supply unit,
The internal circuit receives the second potential supplied from the third supply unit,
The semiconductor integrated circuit device, wherein the delay circuit receives the second potential supplied from the fourth supply unit. In claim 25,
An element forming region constituting the delay circuit is separated from an element forming region constituting the internal circuit, the phase comparison circuit, and the control circuit. In claim 26,
The clock generation circuit includes an input circuit that receives an input signal and an output circuit that sends an output signal.
The semiconductor memory circuit device, wherein the input circuit and the output circuit are supplied with the first potential from the second supply unit and supplied with the second potential from the fourth supply unit. A semiconductor memory circuit device,
A delay circuit that receives the first clock signal and outputs a second clock signal obtained by delaying the first clock signal by a predetermined delay time; a third clock signal formed based on the second clock signal; and the first clock signal A phase comparison circuit that compares the phase of the clock signal and outputs a control signal; and a control that controls the delay circuit so that the phase of the first clock signal and the phase of the third clock signal coincide with each other based on the control signal A clock generation circuit including a circuit;
A plurality of word lines and a plurality of pairs of complementary bit lines connected to a plurality of dynamic memory cells in response to the second clock signal; and a sense amplifier for amplifying the signals of the pair of complementary bit lines, respectively. Including an internal circuit,
A first supply unit for supplying a first power supply potential;
A semiconductor chip comprising a second supply section for supplying a second power supply potential different from the first power supply potential;
A first terminal that is electrically connectable to the outside of the semiconductor memory circuit device and supplies the first power supply potential, which is a first potential from the outside of the semiconductor memory circuit device, to the first supply unit;
The first terminal that can be electrically connected to the outside of the semiconductor memory circuit device and supplies the second power supply potential, which is the first potential from the outside of the semiconductor memory circuit device, to the second supply unit is different. Two terminals,
The internal circuit receives the first power supply potential supplied from the first supply unit,
The semiconductor memory circuit device, wherein the delay circuit receives the second power supply potential supplied from the second supply unit. In claim 29,
The semiconductor chip further includes a third supply unit for supplying a third power supply potential;
A fourth supply unit for supplying a fourth power supply potential different from the third power supply potential;
A third terminal that is electrically connectable to the outside of the semiconductor memory circuit device and supplies the third power supply potential, which is a second potential from the outside of the semiconductor memory circuit device, to the third supply unit;
The third terminal that is electrically connectable to the outside of the semiconductor memory circuit device and supplies the fourth power supply potential, which is the second potential from the outside of the semiconductor memory circuit device, to the fourth supply unit is different. 4 terminals,
The internal circuit receives the second power supply potential supplied from the third supply unit,
The semiconductor memory circuit device, wherein the delay circuit receives the second power supply potential supplied from the fourth supply unit. In claim 30,
An electrical connection between the first supply unit and the first terminal; an electrical connection between the second supply unit and the second terminal; and an electrical connection between the third supply unit and the third terminal. The semiconductor memory circuit device is characterized in that the electrical connection between the fourth supply section and the fourth terminal is made via a wire. In claim 30,
2. A semiconductor memory circuit device according to claim 1, wherein an element formation region constituting the delay circuit is separated from an element formation region constituting the internal circuit, the phase comparison circuit, and the control circuit. In claim 30,
The clock generation circuit includes an input circuit that receives an input signal and an output circuit that sends an output signal.
The semiconductor memory circuit device, wherein the input circuit and the output circuit are supplied with the first potential from the second supply unit and supplied with the second potential from the fourth supply unit. A semiconductor memory circuit device,
A delay circuit that receives the first clock signal and outputs a second clock signal obtained by delaying the first clock signal by a predetermined delay time; a third clock signal formed based on the second clock signal; and the first clock signal A phase comparison circuit that compares the phase of the clock signal and outputs a control signal; and a control that controls the delay circuit so that the phase of the first clock signal and the phase of the third clock signal coincide with each other based on the control signal A clock generation circuit including a circuit;
A plurality of word lines and a plurality of pairs of complementary bit lines connected to a plurality of dynamic memory cells in response to the second clock signal; and a sense amplifier for amplifying the signals of the pair of complementary bit lines, respectively. Including an internal circuit,
A first supply unit for supplying a first power supply potential;
A second supply section for supplying a second power supply potential different from the first power supply potential;
A third supply unit for supplying a third power supply potential;
A semiconductor chip comprising a fourth supply section for supplying a fourth power supply potential different from the third power supply potential;
A first terminal that is electrically connectable to the outside of the semiconductor memory circuit device and supplies the first power supply potential, which is a first potential from the outside of the semiconductor memory circuit device, to the first supply unit;
The first terminal that can be electrically connected to the outside of the semiconductor memory circuit device and supplies the second power supply potential, which is the first potential from the outside of the semiconductor memory circuit device, to the second supply unit is different. Two terminals,
A third terminal that is electrically connectable to the outside of the semiconductor memory circuit device and supplies the third power supply potential, which is a second potential from the outside of the semiconductor memory circuit device, to the third supply unit;
The third terminal that is electrically connectable to the outside of the semiconductor memory circuit device and supplies the fourth power supply potential, which is the second potential from the outside of the semiconductor memory circuit device, to the fourth supply unit is different. 4 terminals,
The internal circuit receives the first power supply potential supplied from the first supply unit and the second power supply potential supplied from the third supply unit,
The semiconductor memory circuit device, wherein the delay circuit receives the first power supply potential supplied from the second supply unit and the second power supply potential supplied from the fourth supply unit. In claim 34,
An electrical connection between the first supply unit and the first terminal; an electrical connection between the second supply unit and the second terminal; and an electrical connection between the third supply unit and the third terminal. The semiconductor memory circuit device is characterized in that the electrical connection between the fourth supply section and the fourth terminal is made via a wire. In claim 34,
2. A semiconductor memory circuit device according to claim 1, wherein an element formation region constituting the delay circuit is separated from an element formation region constituting the internal circuit, the phase comparison circuit, and the control circuit. In claim 34,
The clock generation circuit includes an input circuit that receives an input signal and an output circuit that sends out an output signal.
The semiconductor memory circuit device, wherein the input circuit and the output circuit are supplied with the first potential from the second supply unit and supplied with the second potential from the fourth supply unit. A dynamic semiconductor memory device including a semiconductor chip including a DLL circuit and a clock generation circuit for generating a clock signal, and an internal circuit whose operation is controlled by the clock signal,
The semiconductor chip is
A first power supply pad coupled to the clock generation circuit for supplying a first power supply potential to the clock generation circuit;
A second power supply pad coupled to the clock generation circuit for supplying a second power supply potential having a potential lower than the first power supply potential to the clock generation circuit;
A plurality of third power supply pads coupled to the internal circuit for supplying the third power supply potential to the internal circuit;
A plurality of fourth power supply pads coupled to the internal circuit and for supplying a fourth power supply potential having a potential lower than the third power supply potential to the internal circuit;
The dynamic semiconductor memory device is
A first terminal coupled to the first power pad;
A second terminal coupled to the second power pad;
A plurality of third terminals coupled to the plurality of third power pads and different from the first terminal;
A dynamic semiconductor memory device comprising a plurality of fourth terminals coupled to the plurality of fourth power supply pads and different from the second terminals. In claim 38,
The internal circuit is
A plurality of word lines, a plurality of data lines, a plurality of dynamic memory cells coupled to the plurality of word lines and the plurality of data lines;
A plurality of sense amplifiers respectively coupled to the plurality of data lines;
A data output circuit coupled to the outputs of the plurality of sense amplifiers;
The data output circuit outputs a signal read from the dynamic memory cell to the outside of the dynamic semiconductor memory device in synchronization with both rising and falling of the clock signal generated from the clock generating circuit. A dynamic semiconductor memory device characterized in that the output is output. In claim 39,
The internal circuit further includes
A strobe signal output circuit for generating a data strobe signal in synchronization with the data output from the data output circuit;
The dynamic semiconductor memory device, wherein the strobe signal output circuit operates in response to the clock signal generated from the clock generation circuit. In claim 38,
The clock generator circuit
A delay circuit for receiving a first clock signal and outputting a second clock signal obtained by delaying the first clock signal by a predetermined delay time;
A phase comparison circuit that compares the phase of the third clock signal formed based on the second clock signal and the first clock signal and outputs a control signal;
A control circuit for controlling the delay circuit so that the phase of the first clock signal and the phase of the third clock signal coincide with each other based on the control signal;
The internal circuit is controlled in operation by the second clock signal,
The dynamic semiconductor memory device, wherein the delay circuit is coupled to the first power supply pad and the second power supply pad. In claim 41,
2. The dynamic semiconductor memory device according to claim 1, wherein the first and third power supply potentials are substantially equal, and the second and fourth power supply potentials are substantially equal.

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