JPH0963272A - Semiconductor integrated circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To stabilize supply of an operation power source for burn-in by providing a source supply unit provided with a boosting circuit and a source supplying transistor operating synchronizing with period signals with phases different from each other. SOLUTION: Plural boosting circuits 30 in the source supply unit perform boosting operation synchronizing with the period signals N1-N4 formed based on an oscillation output of an oscillation circuit 32. Then, the outputs of these boosting circuits 30 are made gate control voltage VPG2 of operation source supplying N channel MOS transistors Q63. By such a constitution, since any boosting circuit 30 performs the boosting operation always, the source supply operation is performed continuously by the transistor Q63. Thus, it is prevented that the voltage of a source supply line WDP is lowered unexpectedly even when a word driver is fluctuated remarkably in a load.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a boosting technique using a charge pump and a technique for supplying an operating voltage for burn-in to an internal circuit. For example, a CMOS whose operating voltage is lowered for high integration. Type DRAM (Dynamic Random Access Memory) is effectively applied.

[0002]

2. Description of the Related Art In a semiconductor integrated circuit, there are cases where defects which are hard to find in a functional test and which have not been made apparent at the manufacturing stage are inherent. For example, if the wiring is not broken but the wiring is abnormally thin, it is expected that the wiring will be broken relatively early due to electromigration, etc., and if the gate oxide film is cracked. Therefore, the gate oxide film may be destroyed early. Therefore, by operating the semiconductor integrated circuit by giving a power supply voltage higher than usual, stress on the internal circuit is increased, and a defect such as an initial operation defect that has not yet been revealed is revealed. Accelerated test) can be performed. Incidentally, as an example of a document describing burn-in, there are three kinds of documents, November 3, 59:
"LSI Handbook" published by Ohmsha Co., Ltd.
There is page 684.

[0003]

However, in burn-in, even if a relatively high voltage is applied to the external power supply terminal, there is an internal circuit in which it is difficult to apply a correspondingly high voltage. For example, the present inventor has found that the word line is a DRAM word driver in which the operating voltage of the sense amplifier is lowered. .

That is, the inventor of the present invention has developed an MO memory cell transistor or the like in order to increase the storage capacity of the DRAM.
Since the gate oxide film is thinned as the gate length of the MOS transistor is reduced by downsizing the S-transistor, the operating voltage has been lowered. Especially DR
It is necessary for the AM to perform high-level writing (charging operation for the storage capacity of the memory cell) without reducing the high-level reading operation efficiency (or making the high-level reading operation margin relatively large). , In that case, increase the selection level of the word line,
It is effective to lower the voltage of the data line to which the data input / output terminal of the memory cell is coupled (the level of the data line reached by the amplifying operation of the sense amplifier). In the case where the gate oxide film of the MOS transistor is thin, if the voltage level of the word line is unnecessarily raised, the gate oxide film is easily broken, which is not preferable in terms of reliability of the DRAM. Under such circumstances, it is inevitable to reduce the voltage of the data line. When the voltage of the data line is lowered in this way, it impedes high-speed operation of the sense amplifier. That is, when the voltage of the operating power supply of the sense amplifier is lowered, the current flowing through the sense amplifier is reduced, and when the charge information of the memory cell is read to the data line, the speed of amplifying the minute potential difference formed on the complementary data line. Will be lowered.

Therefore, the sense amplifier overdrive technique is applied as a technique for operating the sense amplifier at a high speed under a low voltage. For example, when the sense amplifier is configured in the CMOS static latch form, the P-channel type M
To the source of the OS transistor, the external power supply voltage VDD is applied at the beginning of the sense amplifier activation timing, and then the voltage VDL obtained by stepping down the external power supply voltage VDD is applied to the source of the OS transistor through the drive line common to the sense amplifier, and the sense amplifier is activated. While operating at high speed, the potential reached on the high potential side is converged to the step-down voltage VDL.

At this time, the step-down voltage VDL needs to be stable. Therefore, for example, the threshold voltage of the MOS transistor is used, and the reference voltage having a small dependency on the fluctuation of the power supply voltage is used as the reference voltage. A MOS that is generated by a generation circuit, is applied to the non-inverting input terminal (+) of the operational amplifier as a control voltage, and is switch-controlled by the output of the operational amplifier.
The potential of the connection point of the series circuit of the transistor and the high resistance is feedback-connected to the inverting input terminal (-) of the operational amplifier, and the reference voltage is matched with the connection point of the MOS transistor and the high resistance by the negative feedback control of the operational amplifier. A stepped down voltage VDL is formed. Also, regarding the word line selection level, in order to improve the stability, the step-down voltage VDL
The word driver is driven by using the boosted voltage as the operating power supply.

However, in the above-mentioned technique, even if the power supply voltage is set higher than usual for burn-in, the word line selection level is not increased in proportion thereto, and for burn-in exceeding the allowable normal power supply voltage. It is expected that the operating characteristics of the reference voltage generation circuit, step-down circuit, and step-up circuit will vary relatively from chip to chip with respect to the power supply voltage, and the voltage actually applied to the word line during burn-in will vary from chip to chip. Moreover, it became impossible to grasp it externally, and it was clarified that the reliability of burn-in might be deteriorated and the device under test might be uselessly destroyed.

Therefore, the inventor of the present invention switches the supply line of the operating power supply to a circuit such as a word driver with a switch MOS.
It was considered to connect to the power supply voltage via a transistor and control the switch MOS transistor to be in the ON state in the burn-in mode to adopt the external power supply voltage as the operating power supply of the word driver. At this time, if the switch MOS transistor is configured as an enhancement N-channel type as a measure against latch-up, it is necessary to boost its gate voltage to a voltage higher than the power supply voltage and control it to be in the ON state.
For example, when a charge pump circuit is used to boost the gate control voltage, the boosting operation by the boosting operation is intermittent according to the cycle of the periodic signal. Only turned on. Therefore, in order to prevent the voltage of the operating power supply from being undesirably lowered due to a large load change in a circuit such as a word driver, the current supply capability of the switch MOS transistor is increased during gate control. I found that I had to devise. In this respect, the booster circuit forming the word line selection level in the normal mode should be similarly considered. When the switch MOS transistor is of depletion N-channel type, it is necessary to form a voltage for cutting off the switch MOS transistor in the normal operation.

An object of the present invention is to construct a MOS transistor for supplying operating power to a driver in an N-channel type to prevent latch-up in a CMOS type semiconductor integrated circuit and to charge the gate control voltage of the MOS transistor. The gate control voltage is formed so that the ON operation period of the MOS transistor can be lengthened to stabilize the supply of the operating power when the voltage is raised to a level higher than the operating power by the pump.

Another object of the present invention is to prevent a large load fluctuation in a circuit which uses a voltage from a MOS transistor switch-controlled by receiving a boosted voltage formed by a boosting circuit such as a charge pump at its gate as an operating power source. It is to provide a technique in which the voltage of the operating power supply does not undesirably drop even if it occurs.

Another object of the present invention is to provide a technique capable of efficiently supplying an operating power supply for burn-in to a circuit such as a word driver from the outside.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0013]

The following is a brief description of an outline of a typical invention among the inventions disclosed in the present application.

That is, word drivers (WD0 to WD)
In order to supply an operating power supply for burn-in to a circuit such as 7), periodic signals (N1 to N) having different phases from each other are supplied.
4) A plurality of booster circuits (3
0) and the power supply voltage (VD
D) and an operating power supply line (WDP) common to the word drivers are arranged in a one-to-one correspondence with the booster circuits, and N-channel type power supply for receiving the output of the corresponding booster circuit at its gate. MOS transistor (Q63)
Is provided.

According to a mode in which the operating power is supplied to the drivers (WD0 to WD7) such as the word driver in the normal mode, the plurality of power supply circuits for supplying the operating power to the plurality of drivers are provided. And a boosted voltage (VPP) formed by boosting the internal voltage (VDL) when the external power supply voltage is lower than a predetermined value (normal mode). A power supply unit (2) for the normal mode to be applied, and a power supply unit (2) for the burn-in mode to apply the external power voltage to the power supply line in a state (burn-in mode) where the external power voltage (VDD) is higher than a predetermined value. 3) and The burn-in power supply unit supplies a plurality of power supply MOS transistors (Q6) with boosted outputs of a plurality of booster circuits that individually perform boosting operations according to the periodic signals whose phases are different from each other.
3) will be turned on at different timings.

Also for the power supply unit for the normal mode, it is possible to employ a configuration in which a plurality of booster circuits (20) are boosted and driven by a periodic signal with a phase shift. That is, a plurality of first booster circuits (20) that perform boosting operations in synchronization with periodic signals having different phases formed based on the oscillation output of the oscillator circuit (22), and the first booster circuit and the first booster circuit 1 An N-channel type boosted voltage supply MOS transistor (Q62) arranged on the power supply line (WDP) in a one-to-one correspondence and receiving at its gate the output of the corresponding first booster circuit;
The boosted voltage, which is provided in a one-to-one correspondence with the first booster circuit and is formed in synchronization with the boosting operation of the corresponding first booster circuit, is supplied to the gate of the corresponding boosted voltage supply MOS transistor. A second booster circuit (21) can be provided.

Precursor power supply MOS transistor (Q6
In place of 3), a depletion type N-channel MOS transistor (Q65) is adopted, and the depletion type N-channel MOS transistor is turned on by the power supply voltage when the external power supply voltage is higher than a predetermined value (burn-in mode). When the external power supply voltage is lower than a predetermined value (normal mode), the depletion type N-channel MOS transistor is controlled to the off state by the negative voltage, so that the power supply voltage with a high burn-in level can be efficiently supplied to the driver. Can be supplied. CMOS
Type negative voltage formed in the substrate bias voltage generation circuit provided in the semiconductor integrated circuit of the type can be used.

[0018]

When a MOS transistor for supplying operating power to the driver is formed of an N-channel type as a countermeasure against latch-up in a CMOS circuit and the gate control voltage of the MOS transistor is boosted to a level higher than the operating power supply, A plurality of booster circuits that perform boosting operations in synchronism with cycles of periodic signals having mutually different phases are employed, and a MOS transistor for operating power supply that receives the output of these booster circuits as a gate control voltage is paired with the booster circuit. By providing one corresponding one, any booster circuit always performs boosting operation, so the power supply operation by the power supply MOS transistor is performed without interruption, and the power supply is always supplied regardless of a large load fluctuation in the driver. The situation in which the voltage of the supply line is undesirably lowered is prevented.

When the MOS transistor is applied to a structure for supplying a high power supply voltage for burn-in to a word driver, the word driver is supplied with an operating power supply for burn-in with an internal boosted voltage similar to that in the normal mode. In this case, even if the power supply voltage is higher than usual due to burn-in, the word line selection level (word driver power supply voltage) is not raised in proportion to it, and the normal power supply voltage is exceeded. In addition, it is possible to avoid a situation in which the internal boosted voltage is relatively large with respect to the power supply voltage for burn-in and it becomes impossible to grasp it externally.

An M for supplying operating power for burn-in to the driver as a measure against latch-up in the CMOS circuit
By configuring the OS transistor with a depletion type N channel, the level of the operating power supply is supplied to the driver as it is without the need to boost the gate control voltage for turning on the MOS transistor to a level higher than the operating power supply. Enabled The off state of the MOS transistor is controlled by a negative gate control voltage, but the CMOS
By utilizing the negative voltage generated by the substrate bias voltage generating circuit provided in the circuit, it is possible to suppress an increase in the circuit scale when improving the efficiency of supplying the burn-in operating power supply to the driver.

[0021]

FIG. 5 is a block diagram of a DRAM according to an embodiment of the present invention. Although not particularly limited, the DRAM shown in the figure is formed on one semiconductor substrate such as single crystal silicon by a known CMOS semiconductor integrated circuit manufacturing technique. FIG. 5 representatively shows two memory arrays MARY0 and MARY1.

The DRAM of this embodiment has an external power supply voltage VDD.
And the ground potential VSS such as 0V is received from the external power supply terminal to operate. When the external power supply voltage VDD is 3.3V, the DRAM is in the normal mode, and when the external power supply voltage VDD is 5.0V, the DRAM is in the burn-in mode. In FIG. 5, reference numeral 7 denotes a power supply voltage determination circuit, which detects the power supply voltage VDD to determine the normal mode and the burn-in mode, sets the burn-in signal BIMD to an inactive level (for example, low level) in the normal mode, and burn-in signal in the burn-in mode. BIMD is set to an active level (for example, high level).

The DRAM of this embodiment has MOSs in the memory arrays MARY0 and MARY1 for increasing the storage capacity.
The transistors are miniaturized, which allows them to
The gate oxide film has become thinner as the gate length of transistors has been reduced. Therefore, the memory array MARY
The operating voltage at 0 and MARY1 is lowered, and a step-down voltage VDL such as 2.2 V is used as a basic operating power supply. The step-down voltage VDL is the external power supply voltage VDD
Is generated by the step-down circuit 1 that steps down. In the figure, 5 is a circuit for generating the substrate bias voltage VBB. The substrate bias voltage generating circuit 5 can also be configured by a known circuit. For example, although not shown, it is configured by a capacitor and a diode element, and by receiving a periodic signal of positive polarity, the substrate bias voltage VBB of negative polarity is generated. Form. In FIG. 5, VDDP is an external input terminal for the power supply voltage VDD, and VSSP is an external input terminal for the ground potential VSS.

Each of the memory arrays MARY0 and MARY1 is divided into eight memory mats MMAT0 to MMAT7. Individual memory mats MMAT0 to MMAT7
Includes a large number of one-transistor type dynamic memory cells whose select terminals are connected to word lines and whose data input / output terminals are connected to complementary data lines. Word drivers WD0 to WD7 and row address decoder XD for each memory mat
0 to XD7 are provided. Row address decoder XD0
When the operation is selected, the to XD7 decode the internal complementary row address signal AX to form a word line selection signal, and select one word line corresponding to the internal complementary row address signal AX. The word drivers WD0 to WD7 receive the word line selection signal and drive the word line to be selected by the word line selection signal to the selection level in synchronization with the word line drive timing instructed by the control signal φX.

The word line selection level (word driver operating power supply) output by the word drivers WD0 to WD7 is
In the normal mode, the step-down voltage VDL is changed to the step-up circuit 2
The boosted voltage VPP is boosted by 0, and in the burn-in mode, the power supply voltage VDD is set higher than usual. The operation power supply of the word driver will be described in detail later.

SA01, SA23, SA45, SA67
Is a sense amplifier block, CSW01, CSW23, C
SW45 and CSW67 are column switch circuit blocks, which are arranged between a pair of left and right memory mats and shared by a pair of adjacent left and right memory mats. Sense amplifier blocks SA01, SA23, SA45, SA67 and column switch circuit blocks CSW01, CSW23, CS
A shared data line structure is adopted for the pair of left and right memory mats arranged with the W45 and CSW67 interposed therebetween, and the operation of either one of the memory mats is selected. The operation selection and operation control of the memory mats, such as the operation control of each sense amplifier block and the control of the data line sharing switch circuit (see FIG. 6) between the memory mats sharing the sense amplifier block, are performed by a pair of memory mats. Mat controller MC provided for each
NT01, MCNT23, MCNT45, MCNT67
Do.

Mat controller MCNT01, MCN
T23, MCNT45, and MCNT67 have a mat selection signal MS and sense amplifier control signals φSAN, φSAP2.
φSAP1B is supplied. The mat selection signal MS is a 3-bit signal instructing which one is selected from the eight memory mats MMAT0 to MMAT7. Actually, it corresponds to the information of the upper 3 bits of the row address signal held in the row address buffer RAB. Mat controller MCNT01, MCNT23, MCNT4
5, MCNT 67 decodes the mat selection signal MS,
The operation control of the sense amplifier block and the activation control of the row address decoder are performed so that the memory mat designated by it is operated. For example, when the mat select signal MS designates the memory mat MMAT0, the row address decoder XD0 is activated, the sense amplifier block SA01 is connected to the memory mat MMAT0 via the data line sharing switch circuit, and the memory mat MMAT0 is connected.
A memory cell selection operation is enabled in AT0.
Sense amplifier control signals φSAN, φSAP2, φSAP
Details of 1B will be described later.

Each column switch circuit block CSW
n receives a column selection signal from the column address decoder YD, thereby selecting four sets of complementary data lines from the memory mat, and complementary common data lines CD0-C0.
Conduct to D3. In the read operation, the column address decoder YD is made operable by the timing signal φY which is set to the enable level after the word line selection operation is determined, thereby decoding the internal complementary column address signal AY and generating the column selection signal. .

By the word line selection operation and the column selection operation, four memory cells designated by the mat selection signal MS, the internal complementary row address signal AX, and the internal complementary column address signal AY become complementary common data lines CD0 to CD0. CD
3 is conducted. Although not particularly shown, the memory array MARY1 side is also configured in the same manner as described above, and the memory array MARY
Complementary common data lines CD4 to CD7 are arranged on the first side.

The complementary common data lines CD0 to CD7 are
Although not particularly limited, it is coupled to the data input / output circuit DIO. The data input / output circuit DIO includes a main amplifier, a write amplifier, and a data input / output buffer. When the timing signal φW is set to the enable level, the data input operation for writing is performed, and the timing signal φ
When R is set to the enable level, a data output operation for reading is performed. Dynamic R of this embodiment
In the AM, data is written and read in units of 8 bits, the memory array MARY0 carries the lower 4 bits, and the memory array MARY1 carries the upper 4 bits.

The row address buffer RAB fetches and holds the row address signal input from the external address input terminals A0 to Ai via the address multiplexer AMX. This fetching operation is instructed by the high level of the timing signal φXL supplied from the timing generating circuit TG.

Although not particularly limited, the address multiplexer AMX supplies the disable level timing signal φREF from the timing generation circuit TG when the dynamic RAM is set to the normal operation mode, so that the external terminals A0 to Ai are connected. The row address signal supplied via the row address buffer RAB is transmitted. In addition, the dynamic RAM is CBR (CAS brfore R
AS) When the timing signal φREF is set to the enable level during the refresh cycle, the refresh address signal supplied from the refresh address counter RFC is selected and transmitted to the row address buffer RAB.

The refresh address counter RFC is
Although not particularly limited, when the dynamic RAM is set to the CBR refresh mode, the timing generation circuit TG
From the timing signal φRC supplied every predetermined cycle
A refresh address is generated by performing a counting operation in synchronization with the.

The column address buffer CAB synchronizes the column address signal supplied through the external address input terminals A0 to Ai with the timing when the control signal φYL supplied from the timing generation circuit TG is enabled. Capture and hold.

The timing generation circuit TG uses the row address strobe signal RAS * (the symbol * means that the signal to which it is attached is a row enable signal) and the column address strobe CAS as access control signals from the outside. *, The write enable signal WE *, and the output enable signal OE * are supplied, and the dynamic RAM is based on these levels and change timings.
The operation mode is determined, the various timing signals are formed, and the internal operation of the dynamic RAM is controlled. The row address strobe signal RAS * instructs chip selection by its low level and notifies that the row address signal is valid. According to this, the timing controller TG fetches the row address signal,
Then, the control signals for word line selection operation and memory mat selection are sequentially generated. The column address strobe CAS * is a signal notifying that the column address signal is valid. When it is set to the enable level, the timing controller TG sequentially generates the control signals for fetching the column address signal and the column selecting operation. The write enable signal WE * instructs the DRAM to perform a write operation according to its enable level, and the output enable signal OE * instructs the DRAM to perform a read operation according to its enable level. In the CBR refresh mode, the row address strobe signal RAS is used.
It is specified by setting the column address strobe CAS * to the enable level before * is enabled.

FIG. 6 shows the memory mats MMAT0 and MMAT.
Partial circuit diagrams of the MAT1, the sense amplifier block SA01, and the column switch circuit block CSW01 are shown. Particularly, in the figure, one column selection signal YS00
The circuit portion that receives the signal is typically shown. In this specification, a MOS transistor having a channel (back gate) portion with an arrow is a P-channel type, and is distinguished from an N-channel type MOS transistor without an arrow.

WL0 to W typically shown in FIG.
Li is a word line, and DL0, DL0B and DL1,
DL1B is a complementary data line, and MC is a dynamic memory cell. The dynamic memory cell MC is
A series circuit of the selection MOS transistor Q1 connected to the data line and the storage capacitor SC is connected to the plate potential PL (VDL /
It is connected to 2). Q27 to Q34 are some sharing switch MOS transistors forming a data line sharing switch circuit. Memory mat MMA
Representatively shown sharing switch MOS transistors Q27 to Q30 arranged between T0 and T0 are switch-controlled by a control signal φSHRL, and a memory mat MMA.
The representatively shown sharing switch MOS transistors Q31 to Q34 arranged between T1 and T1 are switch-controlled by a control signal φSHRR. For example, when the mat selection signal MS selects the memory mat MMAT0, the mat controller MCNT01 causes the control signal φSHR.
Control L to high level. When the mat selection signal MS selects the memory mat MMAT1, the mat controller MCNT01 controls the control signal φSHRR to a high level. The sharing switch MOS transistor related to the memory mat not selected by the mat selection signal MS is controlled to the off state by the mat controller corresponding to the memory mat.

N-channel type MOS transistor Q9,
Q10 and P-channel type MOS transistors Q13, Q
The differential amplifier circuit of the static latch type constituted by 14 is one sense amplifier 6, and the sense amplifier 6 is provided for each complementary data line. The operating power of the sense amplifier 6 is supplied via the drive lines SDN and SDP. The drive lines SDN and SDP are common to each sense amplifier 6. Driveline SDN, SD
Control of supply of operating power to P will be described later. Also,
In addition to the sense amplifier 6, each complementary data line is provided with a MOS transistor Q21 for equalizing the complementary data line when the dynamic RAM is on standby. The MOS transistor Q21 is switch-controlled by the control signal φPCSB. In addition, M for equalizing the complementary data lines and supplying a precharge potential to the complementary data lines
OS transistors Q17 and Q18 are provided. The precharge potential is set to a half level of the step-down voltage VDL and is supplied through the wiring HVC. The MOS transistors Q17 and Q18 are switch-controlled by the control signal φPCB. The control signals φPCB and φPCSB are output from the timing controller TG. The precharge voltage VDL / 2 is formed by the precharge voltage forming circuit 4, and is configured by, for example, a resistance voltage dividing circuit that receives the step-down voltage VDL.

In FIG. 6, Q23 and Q24 are complementary data lines DL0 and DL0B and complementary common data line CD0 (cd
0, cd0B), and Q25, Q26 are column switches provided between the complementary data lines DL1, DL1B and the complementary common data line CD1 (cd1, cd1B). A similar column switch is provided for each complementary data line, and four pairs of complementary data lines are used as a set to form four pairs of complementary common data lines CD0 (cd0, c).
d0B), CD1 (cd1, cd1B), CD2 (cd
2, cd2B) and CD3 (cd3, cd3B) are commonly connected.

FIG. 7 shows the drive line S of the sense amplifier 6.
A circuit configuration for supplying operating power to DN and SDP is shown.

The DRAM of this embodiment is, as described above,
The external power supply voltage VDD such as 3.3V is received from the external power supply terminal, but the memory array MAR is used to increase the storage capacity.
Since the MOS transistors in Y0 and MARY1 are miniaturized, and the gate oxide film is thinned in accordance with the reduction in the gate length of those MOS transistors, the operating voltage in the memory arrays MARY0 and MARY1 is lowered, For example, a step-down voltage VDL such as 2.2V is used as a basic operating power supply. At this time, if only the step-down voltage VDL is supplied to the drive line SDP,
Since the operation speed of the sense amplifier 6 becomes slow, the external power supply voltage VDD is applied to the drive line SDP at the beginning of the sense amplifier activation timing, and then the step-down voltage V is applied.
A sense amplifier overdrive technique of applying DL to operate the sense amplifier is applied.

The drive line SDN is an N-channel type M
The drive line SDP is connected to the common drain of the OS transistors Q9 and Q10, and the drive line SDP is connected to the common drain of the P-channel MOS transistors Q13 and Q14.
In the figure, the sense amplifier 6 for one column is shown as a representative, but the drive line SD typically shown in the figure is shown.
N and SDP are generic names of drive lines SDN and SDP for all the sense amplifiers 6 included in the DRAM of this embodiment. The drive line SDN has a control signal φS.
The ground potential VSS is supplied through an N-channel MOS transistor Q40 which is switch-controlled by AN.
An external power supply voltage VDD is supplied to the drive line SDP via a P-channel type MOS transistor Q41 which is switch-controlled by a control signal φSAP1B, and
The step-down voltage VDL is supplied via an N-channel type MOS transistor Q42 which is switch-controlled by the control signal φSAP2.
Is supplied. Control signals φSAN, φSAP1B, φS
AP2 is output from the timing controller TG.

In the activation period of the sense amplifier 6, first, the control signal φSAP1B is at a low level (ground potential VS.
S level), and the power supply voltage VDD is supplied to the drive line SDP via the MOS transistor Q41. As a result, the P-channel type M of the sense amplifier 6
Since the current supplied to the OS transistors Q13 and Q14 is relatively large, the minute potential difference appearing on the complementary data lines DL0 and DL0B due to the memory cell selecting operation is quickly amplified. Then, the control signal φSAP1B is inverted to the high level (the level of the power supply voltage VDD) and the control signal φSAP2 is set to the high level (the level of the boosted voltage VPP), so that the drive line SDP is stepped down via the MOS transistor Q42. The voltage VDL is supplied. The control signal φSAN is set to high level in synchronization with the low level period of the control signal φSAEB. This allows
Regarding the arrival levels of the complementary data lines driven by the sense amplifier 6, one is the ground potential VSS and the other is the step-down voltage VD.
Specified as L. As a result, the sense amplifier 6 can be operated at high speed even when the operating voltage is lowered.

Step-down circuit 1 for forming the step-down voltage VDL
7 includes, as an output terminal Nout, a series connection point of a P-channel type MOS transistor Q50 coupled to the external power supply voltage VDD and a high resistance R1 coupled to the ground potential VSS, as illustrated in FIG. Output terminal Nout
Is fed back to the inverting input terminal (−), and the reference voltage VLR is supplied to the non-inverting input terminal (+) to switch control the MOS transistor Q50.
It is comprised including. The operational amplifier AMP1 increases the conductance of the MOS transistor Q50 (reduces the ON resistance) when the potential of the output terminal Nout is lower than the reference potential VLR, and the MOS transistor Q50 when the potential of the output terminal Nout is higher than the reference potential VLR. Q
Negative feedback control is performed so that the conductance of 50 is decreased (ON resistance is increased) and the voltage of the output terminal Nout is maintained at the reference voltage VLR. In this way, the output terminal Nou
The voltage formed at t is the step-down voltage VDL. Especially M
The value of the resistor R1 is set to a very large value in order to minimize the through current flowing through the series circuit of the OS transistor Q50 and the resistor R1. In the negative feedback control, the current flowing through the high resistance R1 to the output terminal Nout is substantially negligible.

The reference voltage VLR is a control voltage formed by the reference voltage generating circuit 8 and is set to 2.2V, for example. Since the step-down voltage VDL needs to be stable, the reference voltage generating circuit 8 uses the threshold voltage of the MOS transistor to prevent fluctuations in the power supply voltage at least within the allowable range of the normal power supply voltage. Generates an independent reference voltage. Since such a reference voltage generating circuit is known, its illustration is omitted.

FIG. 3 shows an embodiment circuit for generating the operating power supply for the word drivers WD0 to WD7. WDN is a power supply line that supplies the ground potential VSS to the word drivers WD0 to WD7, and WDP is the word drivers WD0 to WD0.
A power supply line for supplying the high potential side operation power supply to the WD 7. Reference numeral 2 is a power supply unit for the normal mode for the word drivers WD0 to WD7, 3 is a power supply unit for the burn-in mode, and the word drivers WD0 to WD0
The high-potential side operating power supply for WD7 is generated.

The power supply unit 2 has a step-down voltage VD.
A booster circuit 20 for boosting L to form a boosted voltage VPP,
N-channel type MOS transistor Q arranged between the output of each booster circuit 20 and the power supply line WDP
62, a booster circuit 21 for boosting the step-down voltage VDL to generate the gate control voltage VPG1 of the MOS transistor Q62, and an oscillating circuit 22 for giving a periodically changed signal to the booster circuits 20, 21. Booster circuits 20, 21
A plurality of MOS transistors Q62 are provided in pairs (typically two in the figure). Boost circuit 20, 2
When the normal mode is designated by the burn-in signal BIMD, the boosting operation 1 is enabled. When the boosted voltage VPP is set to 4.0 V, for example, the gate control voltage VPG1
Is the MOS transistor Q62 with respect to the boosted voltage VPP.
The threshold voltage is higher than the threshold voltage. The booster circuits 20 and 21 are configured by a charge pump circuit that intermittently generates a boosted voltage at the other electrode by receiving a signal that is periodically changed at one electrode, and the booster circuits of both booster circuits 20 and 21 are boosted. The periods are synchronized so that the boosted voltage VPP once supplied to the power supply line WDP does not flow backward during the non-boosting period of the booster circuit 20.

The power supply unit 3 includes an N-channel MOS transistor Q63 arranged between the external power supply voltage VDD and the power supply line WDP, and a power supply voltage VDD.
A boosting circuit 30 for boosting the voltage to form a gate control voltage VPG2, and an oscillating circuit 32 for giving a periodic signal to the boosting circuit 30. The booster circuit 30 and the MOS transistor Q63 form a pair and a plurality of sets (typically two sets in the drawing) are provided. The booster circuit 30 is enabled for boosting operation when the burn-in mode is designated by the burn-in signal BIMD. When the power supply voltage VDD is, for example, 5.0 V in the burn-in mode, the gate control voltage VPG2 is
The power supply voltage VDD is a voltage higher than the threshold voltage of the MOS transistor Q63. Boost circuit 3
0 is configured by a charge pump circuit that intermittently generates a boosted voltage at the other electrode by receiving a signal that is periodically changed at one electrode.

FIG. 1 shows a detailed example of the power supply unit 3 for the burn-in mode. In FIG. 1, the booster circuit 30 includes a 2-input NAND gate 300 and an even number of CMOs.
A series circuit of S inverters 301 to 304 and a capacitive element 305 for pumping is provided, the other electrode of the capacitive element 305 is connected to the gate of the MOS transistor Q63, and between the gate of the MOS transistor Q63 and the power supply voltage VDD. N channel type MOS transistor Q
64 are arranged. A burn-in signal BIMD is supplied to one input of the NAND gate 300, and M
The inverted signal of the burn-in signal BIMD is supplied to the gate of the OS transistor Q64 via the CMOS inverter 306. Four booster circuits 3 typically shown in FIG.
Periodic signals N1 to N4 which are out of phase with each other are separately supplied to the other input of the NAND gate 300 of 0.

In the normal mode in which the power supply voltage VDD is set to the normal power supply voltage, for example, 3.3V, the burn-in signal BIMD is set to the low level. As a result, the boosted voltage VPP such as 4.0 V is supplied from the power supply unit 2 for the normal mode to the power supply line WDP.
Each booster circuit 30 sets the gate potential of the MOS transistor Q63 to the MOS transistor Q6 with respect to the power supply voltage VDD.
It is fixed at a level lower than the threshold voltage of 4 (for example, 2.2 V). The threshold voltages of the MOS transistors Q63 and Q64 are made equal. Therefore, in the normal mode, MOS transistor Q63 is cut off.

In the burn-in mode in which the power supply voltage VDD is higher than the normal power supply voltage, for example, 5.0 V, the burn-in signal BIMD is set to the high level. In the burn-in mode, the power supply unit 2 for the normal mode controls the MOS transistor Q62 in the cutoff state. When the burn-in signal BIMD is set to the high level, in the booster circuit 30, the MOS transistor Q64 is turned off, and the one electrode of the capacitive element 305 receives the periodically changed signal via the NAND gate 300. The boosted voltage is intermittently generated on the other electrode of the capacitive element 305. M during the intermittent boosting period (high-level output period of the inverter 304)
The gate control voltage VPG2 of the OS transistor Q63 is set to a level higher than the threshold voltage of the MOS transistor Q63 with respect to the power supply voltage, and the power supply voltage VDD is supplied to the power supply line WDP.

Here, since the phases of the periodic signals N1 to N4 are shifted from each other, the four boosting circuits 30 are not simultaneously set in the non-boosting period, and any one of the boosting circuits 30 boosts at any time. Since the operation is performed, it is possible to prevent a situation where the voltage of the power supply line is undesirably lowered no matter what time the large load variation occurs in the word drivers WD0 to WD7. If the phases of the periodic signals N1 to N4 are the same as each other, there is a timing in which the four boosting circuits 30 are in the non-boosting period at the same time, and the word drivers WD0 to WD7 receive a sudden load. When the fluctuation occurs, the voltage of the power supply line WDP is undesirably lowered.

In FIG. 1, reference numeral 307 denotes an inverter 301.
Of the delay capacitance element and the ground potential VSS. The capacitive element 307 acts to delay the rising change rate of the output of the inverter 301, relatively lengthen the high level output period of the inverter 304, and lengthen the boosting operation period of the booster circuit 30.

FIG. 2 shows another detailed circuit example of the power supply unit 3 for the burn-in mode. In FIG. 2, two booster circuits 30 are provided, and the periodic signals N1 and N2 are signals whose phases are mutually inverted. Individual boost circuit 30
Is the same as in FIG. In this example as well, since any one of the booster circuits 30 is always performing the boosting operation, the voltage of the power supply line WDP is undesirably lowered no matter how the large load variation occurs in the word drivers WD0 to WD7. Is prevented.

Although not shown in the drawing, the booster circuits 20 and 21 can be formed in the power supply unit 2 for the normal mode with the same logic configuration as that shown in FIG. Similarly, the phases of the periodic signals to be supplied to the plurality of booster circuits 20 are shifted, and the plurality of booster circuits 21 are also provided with the periodic signals whose phases are shifted in the same manner. It is possible to prevent the situation where the voltage of the power supply line WDP is undesirably lowered no matter what time the large load variation occurs in WD0 to WD7.

FIG. 4 shows another example of the burn-in mode power supply unit 3. In this example, the above M
In place of the OS transistor Q63, a depletion type N
A channel MOS transistor Q65 is adopted, and the MOS transistor Q65 is controlled to be turned on by the power supply voltage VDD in the burn-in mode, and the MOS transistor Q65 is controlled to be turned off by the substrate bias voltage VBB in the normal mode.

In FIG. 4, reference numeral 9 is a level conversion circuit for setting the signal amplitude for switch controlling the MOS transistor Q65 within the range between the substrate bias voltage VBB and the power supply voltage VDD. The level conversion circuit 7 is a circuit that receives the burn-in signal BIMD, expands the signal amplitude of the input signal, and transmits it to the output.
A series circuit of an S transistor Q70 and N channel type MOS transistors Q71 and Q72, and a P channel type MO transistor.
A series circuit of an S transistor Q73 and N channel type MOS transistors Q74 and Q75 is arranged in parallel between the power supply voltage VDD and the substrate bias voltage VBB.
A burn-in signal BIMD is supplied to the gates of the MOS transistors Q70 and Q71, and the MOS transistor Q7
The burn-in signal BIMD is CM at the gate of Q3.
It is inverted by the OS inverter 10 and supplied. The connection point of the MOS transistors Q70 and Q71 is at the gate of the MOS transistor Q75, and the MOS transistors Q73 and Q7 are connected.
The connection point of 4 is connected to the gate of the MOS transistor Q72. The signal amplitude of the burn-in signal BIMD is the potential difference between the ground potential VSS and the power supply voltage VDD. When the burn-in signal BIMD is at the ground potential level (normal mode), the MOS transistor Q70 is in the ON state,
The gate of the MOS transistor Q65 is set to the level of the substrate bias voltage VBB depending on the off state of the MOS transistor 73 and the on state of the MOS transistors Q74 and Q75. When the burn-in signal BIMD is set to the level of the ground potential VSS (burn-in mode), the MOS transistor Q70 is turned off, the MOS transistor 71 is turned on, the MOS transistors Q73 and Q72 are turned on, and the MOS transistor Q75 is turned off.
The gate of the OS transistor Q65 is set to the level of the power supply voltage VDD.

With the structure shown in FIG. 4, the power supply line WDP can be supplied with the power supply voltage VDD for burn-in constantly and without using a booster circuit in the burn-in mode. By using the output voltage VBB of the substrate bias voltage generating circuit 5 as a negative voltage for controlling the MOS transistor Q65 in the OFF state, it is possible to suppress the increase in circuit scale as much as possible.

According to the above embodiment, the following operational effects are obtained. [1] A MOS transistor Q63 (Q62) for supplying operating power to the word drivers WD0 to WD7 is configured as an N-channel type to prevent latch-up in the CMOS circuit, and the gate control voltage of the MOS transistor is supplied from the operating power supply. Also, when boosting to a high level, a plurality of boosting circuits 30 (21) that perform boosting operations in synchronization with the cycles of the periodic signals N1 to N4 having mutually different phases are adopted,
A MOS transistor Q63 for supplying operating power for receiving the output of these booster circuits 30 (21) as a gate control voltage.
By providing (Q62) in a one-to-one correspondence with the booster circuit 30 (21), any booster circuit 30
Since (21) performs the boosting operation, the operation power supply operation by the MOS transistor Q63 (Q62) is performed without interruption, and the voltage of the power supply line WDP does not change at any time even if a large load change occurs in the word drivers WD0 to WD7. Can be prevented from being undesirably lowered.

[2] From the above, the external power supply voltage VDD
Can be efficiently supplied as an operating power supply for burn-in to the word drivers WD0 to WD7.

[3] As described above, even if the power supply voltage is set higher than usual due to the burn-in, which is problematic when the word driver is supplied with the operating power supply at the internal boosted voltage similar to the normal mode. In proportion to that, the word line selection level is not increased, and the internal boosted voltage varies relatively large with respect to the power supply voltage for burn-in exceeding the normal power supply voltage, making it impossible to grasp it externally. It is possible to avoid such a situation. Therefore, it is possible to prevent the reliability of burn-in from being deteriorated and to prevent the device under test from being destroyed in vain.

[3] A gate for turning on the MOS transistor Q65 by configuring the MOS transistor Q65 for supplying burn-in operation power to the driver by a depletion type N-channel to prevent latch-up in the CMOS circuit. The level of the high-voltage power supply voltage VDD for burn-in can be directly supplied to the word drivers WD0 to WD7 without the need to boost the control voltage to a level higher than that of the operating power supply. MO concerned
The off state of the S transistor Q65 is performed by a negative gate control voltage, but by utilizing the negative voltage VBB generated by the substrate bias voltage generating circuit 5 provided in the CMOS circuit, the burn-in operating power supply for the word driver is supplied. It is possible to suppress an increase in circuit scale when improving supply efficiency.

Although the invention made by the present inventor has been specifically described based on the embodiments, the present invention is not limited thereto, and needless to say, various modifications can be made without departing from the scope of the invention. Yes. For example,
The drain of the MOS transistor Q64 may be connected to the step-down voltage instead of the power supply voltage. In addition, the inverter 304
The operating power source may be the step-down voltage VDL and the ground potential VSS. Further, in the above embodiment, the case where the sense amplifier is overdriven has been described, but the drive form for the sense amplifier is not limited to overdriving. Also, D
The memory mat structure of the RAM, the logical structure of mat selection, the number of parallel input / output bits of data, etc. are not limited to the above-mentioned embodiment, and can be changed as appropriate. The logical configuration of the booster circuit is shown in FIG.
The boosting circuit is not limited to the above and can be changed as appropriate.

In the above description, the invention made by the present inventor is the field of application behind which DRA is applied.
However, the present invention is not limited to this, and a synchronous DRAM, a pseudo static RAM, which is operated in synchronization with a periodic signal, a data processing LSI such as a microcomputer, and other semiconductor integrated circuits. Can be widely applied to.

[0065]

The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows.

When a MOS transistor for supplying operating power to a driver is formed of an N-channel type for countermeasures against latch-up in a CMOS circuit and the gate control voltage of the MOS transistor is boosted to a level higher than the operating power supply, A plurality of booster circuits that perform boosting operations in synchronism with cycles of periodic signals having mutually different phases are employed, and a MOS transistor for operating power supply that receives the output of these booster circuits as a gate control voltage is paired with the booster circuit. By providing one corresponding one, any booster circuit is always performing a boosting operation, thus preventing a situation where the voltage of the power supply line is undesirably lowered no matter how large a load change occurs in the driver. can do. That is, C
In order to prevent latch-up in a MOS type semiconductor integrated circuit, a MOS transistor for supplying operating power to a driver is composed of an N channel type, and a gate control voltage of the MOS transistor is higher than the operating power supply by a charge pump. The gate control voltage can be formed so as to stabilize the supply of the operating power supply by lengthening the ON operation period of the MOS transistor when boosting the voltage.

As described above, the operating power supply for burn-in to the circuit such as the word driver can be efficiently supplied from the outside.

When the MOS transistor is applied to a structure for supplying a high power supply voltage for burn-in to a word driver, an operating power supply for burn-in is applied to the word driver with an internal boosted voltage similar to that in the normal mode. In this case, even if the power supply voltage is higher than usual due to burn-in, the word line selection level does not increase in proportion to it, and the power supply voltage for burn-in exceeds the normal power supply voltage. On the other hand, it is possible to prevent the internal boosted voltage from fluctuating relatively large, and it becomes impossible to grasp it externally, which may reduce the reliability of the burn-in and further possibly wastefully destroy the device under test.

M for supplying operating power for burn-in to the driver for latch-up countermeasures in the CMOS circuit
By configuring the OS transistor with a depletion type N channel, the level of the operating power supply is supplied to the driver as it is without the need to boost the gate control voltage for turning on the MOS transistor to a level higher than the operating power supply. Enabled The off state of the MOS transistor is controlled by a negative gate control voltage, but the CMOS
By diverting the negative voltage generated by the substrate bias voltage generating circuit provided in the circuit, it is possible to suppress an increase in the circuit scale and improve the efficiency of supplying the burn-in operating power supply to the driver.

[Brief description of drawings]

FIG. 1 is an explanatory diagram of an embodiment of a power supply unit for burn-in mode.

FIG. 2 is an explanatory view of another embodiment of a power supply unit for burn-in mode.

FIG. 3 is an overall circuit diagram of an embodiment for generating an operating power supply for a word driver.

FIG. 4 is a circuit diagram of still another embodiment of the power supply unit for burn-in mode.

FIG. 5 is an overall block diagram of a DRAM according to an embodiment of the present invention.

FIG. 6 is a partial circuit diagram of a memory mat, a sense amplifier block, and a column switch circuit block of the DRAM of this embodiment.

FIG. 7 Drive lines SDN and SDP of sense amplifier
It is an explanatory view of an example of a circuit that supplies operating power to the.

[Explanation of symbols]

MARY0, MARY1 memory array MMAT0 to MMAT7 memory mats SA01, SA23, SA45, SA67 sense amplifier block WD0 to WD7 word driver XD0 to XD7 row address decoder YD column address decoder TG timing controller DL0, DL0B, DL1, DL1B complementary data lines WLi, WL (i-1) Word line MC Dynamic memory cell VDL Step-down voltage VDD External power supply voltage VSS Ground voltage VPP Step-up voltage VBB Substrate bias voltage 1 Step-down circuit 2 Normal mode power supply unit for word driver 20 Step-up circuit Q62 MOS transistor VPG1 Q62 Gate control voltage 21 Booster circuit 22 Oscillator circuit 3 Burn-in mode power supply unit for word driver Q 63 MOS transistor VPG2 Q63 gate control voltage 30 Booster circuit 32 Oscillator circuit Q64 MOS transistor 305 Pumping capacitance element N1 to N4 Period signal 6 Sense amplifier Q65 Depletion type N channel MOS transistor 5 Substrate bias voltage generation circuit

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Yukie Hide Suzuki 2326 Imai, Ome-shi, Tokyo Inside Hitachi Device Development Center (72) Inventor Ryo Saeki 2326 Imai, Ome-shi, Tokyo Hitachi Device Development Center, Ltd. (72) Inventor Shunichi Sukegawa 2350 Kihara, Miura-mura, Inashiki-gun, Ibaraki Japan Textile Instruments Co., Ltd.

Claims (8)

[Claims] 1. A CMOS semiconductor integrated circuit comprising a power supply unit for supplying operating power to a plurality of drivers, wherein the power supply unit is based on an oscillation circuit and an oscillation output of the oscillation circuit. A booster circuit that performs a boosting operation in synchronism with the formed periodic signal and a supply line of an operating power source common to the driver are arranged corresponding to the booster circuit, and the gate receives the output of the corresponding booster circuit. A semiconductor integrated circuit comprising an N-channel MOS transistor for power supply. 2. A power supply circuit for supplying operating power to a plurality of drivers that output a drive signal according to a logical value of a control signal, wherein the power supply circuit includes a power supply line common to the plurality of drivers. A normal mode power supply unit for applying a boosted voltage formed by boosting an internal voltage to the power supply line when the external power supply voltage is lower than a predetermined value; A burn-in mode power supply unit for supplying an external power supply voltage to the power supply line is provided, and the burn-in mode power supply unit includes an oscillation circuit and periodic signals having different phases formed based on the output of the oscillation circuit. A plurality of step-up circuits that perform a step-up operation in synchronism with the step-up circuit, and one-to-one pair with the step-up circuit between the external power supply voltage and the power supply line. In is disposed, M power supply of the N-channel type which receives an output to the gate of the boosting circuit to be associated
A semiconductor integrated circuit comprising an OS transistor. 3. The step-up circuit is turned off when the external power supply voltage is lower than a predetermined value, and is turned on when the external power supply voltage is higher than a predetermined value. Voltage and M for power supply
The N-channel type MOS transistor arranged between the gate of the OS transistor, the capacitive element having one electrode coupled to the gate of the power supply MOS transistor, and the external power supply voltage higher than a predetermined value. A periodic signal that is changed in synchronization with the output of the oscillation circuit is output toward the other electrode of the capacitance element, and a constant voltage signal is output to the other electrode of the capacitance element when the external power supply voltage is lower than a predetermined value. 3. The semiconductor integrated circuit according to claim 2, further comprising a control gate for outputting to the. 4. The power supply unit for the normal mode includes an oscillating circuit and a plurality of first boosting operations that perform a boosting operation in synchronization with periodic signals having different phases formed based on an oscillating output of the oscillating circuit. Booster circuit, and the first booster circuit and 1
One-to-one correspondence with the first booster circuit, and an N-channel type boosted voltage supply MOS transistor arranged on the power supply line in a one-to-one correspondence and receiving the output of the corresponding first booster circuit at its gate. And a second booster circuit that supplies a boosted voltage, which is provided in synchronization with the boosting operation of the corresponding first booster circuit, to the gate of the corresponding boosted voltage supply MOS transistor. The semiconductor integrated circuit according to claim 2, wherein the semiconductor integrated circuit is provided. 5. A power supply circuit for supplying operating power to a plurality of drivers that output a drive signal according to a logical value of a control signal, the power supply circuit including a power supply line common to the plurality of drivers. A normal mode power supply unit for applying a boosted voltage formed by boosting an internal voltage to the power supply line when the external power supply voltage is lower than a predetermined value; A power supply unit for burn-in mode for supplying an external power supply voltage to the power supply line is provided, and the power supply unit for burn-in mode is turned on by the power supply voltage in a state where the external power supply voltage is higher than a predetermined value, A depletion type MOS transistor that is turned off by a negative voltage when the external power supply voltage is lower than a predetermined value. The semiconductor integrated circuit, characterized in that the static those made provided between the external power supply voltage and the power supply line. 6. The semiconductor integrated circuit according to claim 5, further comprising a substrate bias voltage generating circuit, wherein the negative voltage is the substrate bias voltage. 7. The semiconductor according to claim 2, wherein the driver is a word driver for driving a word line connected to a selection terminal of a memory cell to a selection level. Integrated circuit. 8. A step-down circuit for stepping down a power supply voltage supplied from the outside to form a step-down voltage as an internal voltage, a plurality of memory cells having select terminals coupled to a word line, and data of the memory cells. A complementary signal line connected to the input / output terminal, and a differential amplifier circuit that amplifies the potential difference between the complementary signal lines,
A first switching MOS transistor for supplying the power supply voltage to a drive line on the high potential side of the differential amplifier circuit, a second switching MOS transistor for supplying the step-down voltage to the drive line, and the differential amplifier circuit And a means for generating a switching control signal that first supplies a power supply voltage to the drive line via the first switching MOS transistor and then supplies a step-down voltage to the drive line via the second switching MOS transistor in the activation period. 8. The semiconductor integrated circuit according to claim 7, wherein the semiconductor integrated circuit comprises: