JP3694072B2 - Semiconductor device - Google Patents

Description

[0001]
[Industrial application fields]
The present invention relates to a semiconductor memory device having a sense amplifier driven in an overdrive format And even semiconductor devices For example, the present invention relates to a technology that is effective when applied to a DRAM (dynamic random access memory) whose operating voltage is lowered for high integration.
[0002]
[Prior art]
MOS transistors such as memory cell transistors are downsized in order to increase the storage capacity of the DRAM, and as a result, the gate oxide film is made thinner as the gate length of the MOS transistor is reduced, thereby reducing the operating voltage. Is underway. In particular, the DRAM is used when high-level writing (charging operation for the storage capacity of the memory cell) is performed without reducing the high-level read operation efficiency (or relatively increasing the high-level read operation margin). It is effective to raise the selection level of the word line or lower the voltage of the data line to which the data input / output terminal of the memory cell is coupled (the arrival level of the data line by the amplification operation of the sense amplifier). However, when the gate oxide film of the MOS transistor is thinned as the transistor is highly integrated as described above, if the voltage level of the word line is increased unnecessarily, the gate oxide film is easily destroyed and the DRAM is It is not preferable in terms of reliability. Under such circumstances, the voltage of the data line must be lowered. If the voltage of the data line is lowered in this way, it hinders high-speed operation of the sense amplifier. That is, when the voltage of the operating power supply of the sense amplifier is lowered, the current flowing through the sense amplifier is reduced, and the minute potential difference formed on the complementary data line is amplified when the charge information of the memory cell is read to the data line. Speed is reduced.
[0003]
Thus, there is a sense amplifier overdrive technique as a technique for operating the sense amplifier at high speed under a low voltage. For example, when the sense amplifier is configured in a CMOS static latch configuration, the external power supply voltage VDD is applied to the source of the P-channel MOS transistor at the beginning of the sense amplifier activation timing, and then the voltage VDL obtained by stepping down the external power supply voltage VDD is applied. To operate the sense amplifier. One of the sense amplifier overdrive technologies is reported in ISSCC 95 A 29 ns 64 Mb DRAM with Hierachical Arry Architecture / FA 14.2.
[0004]
[Problems to be solved by the invention]
As a result of studying the overdrive technology of the sense amplifier, the present inventor has found the following problems. That is, the source of the P-channel MOS transistor constituting the sense amplifier is supplied with the external power supply voltage VDD via the switch element, and is coupled to the output terminal of the step-down circuit via another switch element. The supply lines for the external power supply voltage VDD and the step-down voltage VDL are shared by many sense amplifiers. When the external power supply voltage VDD is supplied to the sense amplifier, it operates the sense amplifier at a high speed as an operating voltage higher than the step-down voltage VDL. That is, the initial transient response operation in the amplification operation of the sense amplifier is speeded up. Next, the operating power supply of the sense amplifier is switched to the step-down voltage VDL. Since the operation power supply line and data line shared by many sense amplifiers have undesired capacitance components, the external power supply voltage VDD is at the upper limit of the allowable range, and the operation margin is tested. Therefore, in a state where an external power supply voltage of a level higher than normal is supplied, when the operation power supply of the sense amplifier is switched to the step-down voltage VDL, a current flows from the sense amplifier toward the output terminal of the step-down circuit. Is expected to flow backward.
[0005]
At this time, when adopting a circuit in which a high resistance is connected in series to a current source coupled to an external power supply voltage as a step-down circuit and trying to minimize the through current in the step-down circuit, the step-down circuit from the sense amplifier side It has been found by the present inventor that the current flowing backward toward the output terminal is prevented from promptly leaking to the ground potential due to the high resistance, and as a result, the step-down voltage VDL may increase.
[0006]
The undesired level increase of the step-down voltage VDL is disadvantageous in the following points. The increase of the step-down voltage VDL increases the arrival voltage of the data line due to the amplification operation of the sense amplifier, thereby reducing the potential difference between the selection level of the word line and the high level of the data line, and the high level to the memory cell. In writing, the high-level voltage of the data line cannot be applied to the storage capacitor. If the voltage reached by the data line by the sense amplifier is increased due to an undesired level increase of the step-down voltage VDL, the initial level (precharge level) of the data line that is equalized in the chip non-selection period accordingly. When the data written in such a state is read out, the high-level read voltage margin with respect to the precharge level is also reduced. Further, when the booster circuit that forms the word line selection level uses the step-down voltage VDL, an undesired increase in the step-down voltage VDL raises the word line selection level, and the gate oxide film of the memory cell selection transistor May cause damage.
[0007]
An object of the present invention is to reduce the level of the step-down voltage of a step-down circuit that supplies a step-down voltage as a single operation power supply to a differential amplifier circuit such as a sense amplifier driven in an overdrive type. Semiconductor that can be prevented beforehand Body Is to provide a place.
[0008]
The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.
[0009]
[Means for Solving the Problems]
The following is a brief description of an outline of typical inventions disclosed in the present application.
[0010]
That is, when the operating voltage is lowered due to the high integration of the memory array, the differential amplifier circuit (3) such as a sense amplifier is firstly activated at the activation timing of the differential amplifier circuit in order to guarantee the high speed operation of the differential amplifier circuit (3). Overdrive technology in which an external power supply voltage (VDD) is connected to the differential amplifier circuit as an operation power supply, and then a step-down voltage (VDL) formed by the step-down circuit (1) is connected to the differential amplifier circuit as an operation power supply. Is adopted, the step-down circuit is added to the step-down unit (10) that forms the step-down voltage at the series connection point (Nout) of the current source (Q50) and the high resistance (R1). A discharge unit (11) is provided for connecting the series coupling point to the ground potential (VSS) at a predetermined voltage that is equal to or higher than the step-down voltage.
[0011]
In a more detailed aspect of the step-down circuit, when the current source circuit of the step-down unit and the discharge unit is improved in performance, negative feedback control is performed on the current source MOS transistors (Q50, Q51) by the operational amplifiers (AMP1, AMP2). Can be configured. At this time, in order to prevent the discharge operation by the discharge circuit from becoming excessive, after the operation power supply of the differential amplifier circuit is switched from the external power supply voltage to the step-down voltage, the output voltage of the step-down circuit is differentially amplified. Means (TG, Q52) for forcing the current source MOS transistor to an off state may be adopted except for a certain period within a period in which the circuit is supplied as operating power.
[0012]
[Action]
When overdrive technology is adopted as a driving method of a differential amplifier circuit such as a sense amplifier, when the operating power supply of the differential amplifier circuit is switched from the external power supply voltage (VDD) to the step-down voltage (VDL), It is expected that current flows backward from the differential amplifier circuit toward the output terminal of the step-down circuit. When using a circuit in which a high resistance is connected in series to a current source coupled to an external power supply voltage as a step-down circuit, and trying to minimize the through current in the step-down circuit, the output of the step-down circuit from the sense amplifier side Current flowing backward toward the terminal is prevented from promptly leaking to the ground potential by the high resistance. At this time, the discharge unit provided in the step-down circuit allows the backflow current to escape to the ground potential, thereby preventing the step-down voltage from being undesirably increased in level.
[0013]
In addition, the timing at which the discharge unit (11) can operate is changed so that the operation power supply of the differential amplifier circuit is switched from the external power supply voltage to the step-down voltage, and then the output voltage of the step-down circuit is applied to the differential amplifier circuit. Current supply operation via both current source MOS transistors (Q50, Q51) when the negative feedback control is always performed on the step-down unit side and the discharge unit side. By repeating the current extraction operation frequently, it is possible to prevent the power consumption from increasing to a negligible level, and the step-down voltage is made periodic by constantly performing negative feedback control on the step-down unit side and the discharge unit side. The step-down voltage changes periodically even when there is no backflow of current from the differential amplifier circuit. It is possible to prevent the state.
[0014]
【Example】
FIG. 4 is a block diagram of a DRAM according to an embodiment of the present invention. The DRAM shown in the figure is not particularly limited, but is formed on one semiconductor substrate such as single crystal silicon by a known semiconductor integrated circuit manufacturing technique. FIG. 4 typically shows two memory arrays MARY0 and MARY1.
[0015]
The DRAM of this embodiment receives an external power supply voltage VDD such as 3.3V and a ground potential VSS such as 0V from the external power supply terminal. In the DRAM of this embodiment, the MOS transistors in the memory arrays MARY0 and MARY1 are miniaturized in order to increase the storage capacity, whereby the gate oxide film is made thinner as the gate length of the MOS transistors is reduced. For this reason, the operation voltage in the memory arrays MARY0 and MARY1 is lowered, and a step-down voltage VDL such as 2.2V is used as a basic operation power supply. The step-down voltage VDL is generated by the step-down circuit 1 that steps down the external power supply voltage VDD.
[0016]
Each memory array MARY0, MARY1 is divided into eight memory mats MMAT0 to MMAT7. Each of the memory mats MMAT0 to MMAT7 includes a number of one-transistor type dynamic memory cells in which a selection terminal is coupled to a word line and a data input / output terminal is coupled to a complementary data line. For each memory mat, word drivers WD0 to WD7 and row address decoders XD0 to XD7 are provided. When the operation is selected, row address decoders XD0-XD7 decode internal complementary row address signal AX to form a word line selection signal, and select one word line corresponding to internal complementary row address signal AX. . The word drivers WD0 to WD7 receive the word line selection signal and drive the word line to be selected by the word line selection signal to the selection level in synchronization with the word line driving timing instructed by the control signal φX. The word line selection level formed by the word drivers WD0 to WD7 is a boosted voltage VPP having a level higher than the step-down voltage VDL. The boost voltage VPP is generated by the boost circuit 2 that boosts the step-down voltage VDL.
[0017]
SA01, SA23, SA45, and SA67 are sense amplifier blocks, and CSW01, CSW23, CSW45, and CSW67 are column switch circuit blocks that are arranged between a pair of left and right memory mats and are shared by a pair of adjacent left and right memory mats. . The pair of left and right memory mats arranged across the sense amplifier blocks SA01, SA23, SA45, SA67 and the column switch circuit blocks CSW01, CSW23, CSW45, CSW67 employ a shared data line structure. The action is selected. Memory mat operation selection and operation control, such as operation control of each sense amplifier block and control of a data line sharing switch circuit (see FIG. 5) between memory mats sharing the sense amplifier block, form a pair. The mat controllers MCNT01, MCNT23, MCNT45, and MCNT67 are provided for each.
[0018]
A mat selection signal MS and sense amplifier control signals φSAN, φSAP2, and φSAP1B are supplied to the mat controllers MCNT01, MCNT23, MCNT45, and MCNT67. The mat selection signal MS is a 3-bit signal that indicates which one of the eight memory mats MMAT0 to MMAT7 is to be selected. Actually, it corresponds to the information of the upper 3 bits of the row address signal held in the row address buffer RAB. The mat controllers MCNT01, MCNT23, MCNT45, and MCNT67 decode the mat selection signal MS, and control the operation of the sense amplifier block and the activation of the row address decoder so as to operate the memory mat designated by the mat selection signal MS. For example, when the mat selection signal MS designates the memory mat MMAT0, the row address decoder XD0 is activated and the sense amplifier block SA01 is connected to the memory mat MMAT0 via the data line sharing switch circuit. The memory cell selection operation is enabled. Details of the sense amplifier control signals φSAN, φSAP2, and φSAP1B will be described later.
[0019]
Each of the column switch circuit blocks CSWn receives a column selection signal from the column address decoder YD, thereby selecting four sets of complementary data lines from the memory mat and making them conductive to the complementary common data lines CD0 to CD3. The column address decoder YD is enabled by a timing signal φY which is set to an enable level after the word line selection operation is determined in the read operation, thereby decoding the internal complementary column address signal AY to generate a column selection signal. .
[0020]
By the word line selection operation and the column selection operation, four memory cells designated by the mat selection signal MS, the internal complementary row address signal AX, and the internal complementary column address signal AY are conducted to the complementary common data lines CD0 to CD3. Is done. Although not specifically shown, the memory array MARY1 side is also configured in the same manner as described above, and complementary common data lines CD4 to CD7 are arranged on the memory array MARY1 side.
[0021]
The complementary common data lines CD0 to CD7 are not particularly limited, but are coupled to the data input / output circuit DIO. The data input / output circuit DIO includes a main amplifier, a write amplifier, and a data input / output buffer. When the timing signal φW is set to the enable level, the data input operation for writing is performed, and the timing signal φR is set to the enable level. As a result, a data output operation for reading is performed. In the dynamic RAM of this embodiment, data is written and read in units of 8 bits, the memory array MARY0 is responsible for the lower 4 bits, and the memory array MARY1 is responsible for the upper 4 bits.
[0022]
The row address buffer RAB takes in and holds a row address signal input from the external address input terminals A0 to Ai via the address multiplexer AMX. This capture operation is instructed by the high level of the timing signal φXL supplied from the timing generation circuit TG.
[0023]
The address multiplexer AMX is not particularly limited, but is supplied via the external terminals A0 to Ai by being supplied with the disable level timing signal φREF from the timing generation circuit TG when the dynamic RAM is set in the normal operation mode. The row address signal to be transmitted is transmitted to the row address buffer RAB. Further, when the timing signal φREF is set to the enable level when the dynamic RAM is set to a CBR (CAS before RAS) refresh cycle, the refresh address signal supplied from the refresh address counter RFC is selected and used as a row address buffer. Communicate to RAB.
[0024]
The refresh address counter RFC is not particularly limited. When the dynamic RAM is set to the CBR refresh mode, the refresh address counter RFC generates a refresh address by performing a counting operation in synchronization with the timing signal φRC supplied every predetermined cycle from the timing generation circuit TG. To do.
[0025]
The column address buffer CAB captures and holds the column address signal supplied via the external address input terminals A0 to Ai in synchronization with the timing when the control signal φYL supplied from the timing generation circuit TG is enabled. To do.
[0026]
The timing generation circuit TG uses, as an external access control signal, a row address strobe signal RAS * (the symbol * means that a signal to which this is added is a row enable signal), a column address strobe CAS *, a write An enable signal WE * and an output enable signal OE * are supplied. Based on these levels and change timing, the operation mode of the dynamic RAM is determined, and the above various timing signals are formed to control the internal operation of the dynamic RAM. Control. The row address strobe signal RAS * instructs chip selection according to the low level, and notifies that the row address signal is valid. In accordance with this, the timing controller TG sequentially takes in the row address signal and sequentially generates the control signals for the word line selection operation and memory mat selection. The column address strobe CAS * is a signal for notifying that the column address signal is valid. When it is set to the enable level, the timing controller TG sequentially takes in the column address signal and generates the control signal for the column selection operation. The write enable signal WE * instructs the DRAM to perform a write operation according to the enable level, and the output enable signal OE * instructs the DRAM to perform a read operation according to the enable level. The CBR refresh mode is designated by setting the column address strobe CAS * to the enable level before the row address strobe signal RAS * is enabled.
[0027]
FIG. 5 shows a partial circuit diagram of the memory mats MMAT0 and MMAT1, the sense amplifier block SA01, and the column switch circuit block CSW01. In particular, FIG. 2 representatively shows a circuit portion that receives one column selection signal YS00. In the figure, a MOS transistor with an arrow in the channel (back gate) portion is a P-channel type, and is distinguished from an N-channel type MOS transistor without an arrow.
[0028]
WL0 to WLi typically shown in FIG. 5 are word lines, DL0, DL0B, DL1 and DL1B are complementary data lines, and MC is a dynamic memory cell. The dynamic memory cell MC is formed by connecting a series circuit of a selection MOS transistor Q1 connected to a data line and a storage capacitor SC to a plate potential PL (VDL / 2). Q27 to Q34 are some sharing switch MOS transistors constituting the data line sharing switch circuit. The representatively shown sharing switch MOS transistors Q27 to Q30 arranged between the memory mat MMAT0 are switch-controlled by the control signal φSHRL, and are shown representatively arranged between the memory mat MMAT1. The sharing switch MOS transistors Q31 to Q34 are switch-controlled by a control signal φSHRR. For example, when the mat selection signal MS selects the memory mat MMAT0, the mat controller MCNT01 controls the control signal φSHRL to a high level. When the mat selection signal MS selects the memory mat MMAT1, the mat controller MCNT01 controls the control signal φSHRR to high level. The sharing switch MOS transistor related to the memory mat that is not selected by the mat selection signal MS is controlled to be turned off by the mat controller corresponding to the memory mat.
[0029]
A static latch type differential amplifier circuit composed of N-channel MOS transistors Q9 and Q10 and P-channel MOS transistors Q13 and Q14 is one sense amplifier 3, and the sense amplifier 3 is provided for each complementary data line. ing. The operating power of the sense amplifier 3 is supplied via the drive lines SDN and SDP. Drive lines SDN and SDP are common to each sense amplifier 3. The operation power supply control to the drive lines SDN and SDP will be described later. In addition to the sense amplifier 3, each complementary data line includes a MOS transistor Q21 for equalizing the complementary data line when the dynamic RAM is on standby. MOS transistor Q21 is switch-controlled by control signal φPCSB. Further, MOS transistors Q17 and Q18 are provided for equalizing the complementary data lines and supplying a precharge potential to the complementary data lines. The precharge potential is set to a half level of the step-down voltage VDL and is supplied via the wiring HVC. MOS transistors Q17 and Q18 are switch-controlled by a control signal φPCB. The control signals φPCB and φPCSB are output from the timing controller TG. The precharge voltage VDL / 2 is formed by the precharge voltage forming circuit 4 and is constituted by, for example, a resistance voltage dividing circuit that receives the step-down voltage VDL.
[0030]
In FIG. 5, Q23 and Q24 are column switches provided between the complementary data lines DL0 and DL0B and the complementary common data line CD0 (cd0 and cd0B). Q25 and Q26 are complementary data lines DL1 and DL1B and complementary common data. This is a column switch provided between the line CD1 (cd1, cd1B). Similar column switches are provided for each complementary data line, and four pairs of complementary data lines are combined into four pairs of complementary common data lines CD0 (cd0, cd0B), CD1 (cd1, cd1B), CD2 (cd2, cd2B). , CD3 (cd3, cd3B).
[0031]
Next, a circuit configuration for supplying operation power to the drive lines SDN and SDP of the sense amplifier 3 will be described.
[0032]
FIG. 1 shows a circuit for supplying operating power to the drive lines SDN and SDP of the sense amplifier 3. In the figure, the sense amplifiers 3 for one column are representatively shown, but the drive lines SDN and SDP shown representatively in the figure are all of the sense amplifiers 3 included in the DRAM of this embodiment. The drive lines SDN and SDP are generically named. The drive line SDN is supplied with the ground potential VSS via an N-channel MOS transistor Q40 that is switch-controlled by a control signal φSAN. An external power supply voltage VDD is supplied to the drive line SDP via a P-channel MOS transistor Q41 that is switch-controlled by a control signal φSAP1B, and an N-channel MOS transistor Q42 that is switch-controlled by a control signal φSAP2 The step-down voltage VDL is supplied through the via. Control signals φSAN, φSAP1B, and φSAP2 are output from the timing controller TG.
[0033]
As described above, the DRAM of this embodiment receives the external power supply voltage VDD such as 3.3 V from the external power supply terminal, but the MOS transistors in the memory arrays MARY0 and MARY1 are downsized to increase the storage capacity. As the gate length of these MOS transistors is reduced, the gate oxide film is thinned. Therefore, the operating voltage in the memory arrays MARY0 and MARY1 is lowered, and a step-down voltage VDL such as 2.2V is basically used. A typical operating power supply. At this time, if only the step-down voltage VDL is supplied to the drive line SDP, the operation speed of the sense amplifier 3 is slowed down. Therefore, the external power supply voltage VDD is applied to the drive line SDP at the beginning of the sense amplifier activation timing. Next, a sense amplifier overdrive technique is applied in which the sense amplifier is operated by applying a step-down voltage VDL.
[0034]
That is, as shown in FIG. 2, the control signal φSAEB (which is an internal control signal of the timing controller TG and not shown in FIG. 1) that defines the activation period of the sense amplifier 3 is set to the low active level. When changed, first, the control signal φSAP1B is changed to the low level, and the power supply voltage VDD is supplied to the drive line SDP via the MOS transistor Q41. As a result, since the current supplied from the P-channel MOS transistors Q13 and Q14 of the sense amplifier 3 is relatively large, the minute potential difference appearing on the complementary data lines DL0 and DL0B is rapidly amplified by the memory cell selection operation. Next, the control signal φSAP1B is inverted to a high level and the control signal φSAP2 is set to a high level, whereby the step-down voltage VDL is supplied to the drive line SDP via the MOS transistor Q42. The control signal φSAN is set to the high level in synchronization with the low level period of the control signal φSAEB. As a result, the arrival level of the complementary data line driven by the sense amplifier 3 is defined as one of the ground potential VSS and the other as the step-down voltage VDL. In this way, the speed of the amplification operation of the sense amplifier 3 under low voltage driving of the memory cell array is increased.
[0035]
The step-down circuit 1 according to this embodiment includes a step-down unit 10 and a discharge unit 11. The step-down unit 10 includes a series connection point of a P-channel MOS transistor Q50 coupled to the external power supply voltage VDD and a high resistance R1 coupled to the ground potential VSS as an output terminal Nout. Non Inverted input terminal ( + ) , Anti Input terminal ( − ) Is supplied with a reference voltage VLR, and is provided with an operational amplifier AMP1 for controlling the switching of the MOS transistor Q50. The operational amplifier AMP1 increases the conductance of the MOS transistor Q50 (decreases the on-resistance) when the potential of the output terminal Nout is lower than the reference potential VLR, and the MOS transistor when the potential of the output terminal Nout is higher than the reference potential VLR. Negative feedback control is performed so as to reduce the conductance of Q50 (increase the on-resistance) and maintain the voltage at the output terminal Nout at the reference voltage VLR. The voltage formed at the output terminal Nout in this way is the step-down voltage VDL. In particular, the value of the resistor R1 is set to a very large value in order to minimize the through current flowing through the series circuit of the MOS transistor Q50 and the resistor R1. In the negative feedback control, the current flowing to the output terminal Nout via the high resistance R1 is reduced to a level that can be substantially ignored. The reference voltage VLR is a control voltage formed by a known reference voltage generation circuit (not shown), for example, and is 2.2V, for example.
[0036]
Here, the external power supply voltage VDD is set to 3.3 V, for example, but an allowable range of about ± 10% is generally allowed for the available power supply voltage. Therefore, the active period of the control signal φSAP1B is set so that the transient response operation of the sense amplifier 3 can be speeded up even when the lower limit level in the allowable range is supplied as the external power supply voltage VDD. Therefore, when the external power supply voltage VDD supplied on the system is the upper limit level of the allowable range, or when a particularly high external power supply voltage VDD is supplied for an operation margin test on the power supply voltage VDD side, etc. When overdrive for the sense amplifier 3 becomes excessive and the operating power supply of the sense amplifier 3 is switched from the external power supply voltage VDD to the step-down voltage VDL, a current flows from the drive line SDP toward the output terminal Nout of the step-down circuit 1. There is a risk of backflow. The reverse current cannot be expected to be immediately discharged to the ground potential VSS via the high resistance R1 as described above. In the present embodiment, the discharge unit 11 forms a path for discharging the current flowing backward from the drive line SDP.
[0037]
In the discharge unit 11, a series connection point of a high resistance R2 coupled to the external power supply voltage VDD and an N-channel type current source MOS transistor Q51 coupled to the ground potential VSS is coupled to the output terminal Nout, and the output Terminal Nout is Non Inverted input terminal ( + ) , Anti Input terminal ( − ) Is supplied with the reference voltage VLR, and further includes an operational amplifier AMP2 that switches and controls the current source MOS transistor Q51, and further includes an N-channel MOS transistor Q52 that selectively conducts the output of the operational amplifier AMP2 to the ground potential VSS. It consists of
[0038]
The operational amplifier AMP2 reduces the conductance of the MOS transistor Q50 (increases the ON resistance) when the potential of the output terminal Nout is lower than the reference potential, and increases the potential of the MOS transistor Q50 when the potential of the output terminal Nout is higher than the reference potential. When the conductance is increased (ON resistance is decreased) and the voltage at the output terminal Nout exceeds the reference voltage VLR, negative feedback control is performed to form a discharge path to the ground potential VSS via the MOS transistor Q51. . Similar to the step-down unit 10, the value of the resistor R2 is set to a very large value in order to minimize the through current flowing in the series circuit of the MOS transistor Q51 and the resistor R2. The current supplied to the output terminal Nout via the resistor R2 is reduced to be substantially negligible. As described above, the discharge unit 10 forms a path for discharging the current flowing backward from the drive line SDP, so that it is possible to prevent the step-down voltage VDL from rising undesirably.
[0039]
If the discharge unit 11 is not provided, as shown in FIG. 3, the level of the step-down voltage VDL is gradually increased by the backflow current from the drive line SDP, and accordingly, the precharge of the complementary data line is performed. The level (VDL / 2) is increased.
[0040]
The undesired level increase of the step-down voltage VDL is disadvantageous in the following points. The increase of the step-down voltage VDL increases the arrival voltage of the data line due to the amplification operation of the sense amplifier, thereby reducing the potential difference between the selection level of the word line and the high level of the data line, and the high level to the memory cell. In writing, the high-level voltage of the data line cannot be applied to the storage capacitor SC. In addition, if the voltage reached by the data line by the sense amplifier is increased due to an undesired increase in the step-down voltage VDL, the precharge that is the initial level of the data line that is equalized in the chip non-selection period is accordingly generated. When the level also rises and the data written in such a state is read, the high level read voltage margin with respect to the precharge level is also reduced. Further, when the booster circuit 2 forming the word line selection level uses the step-down voltage VDL, an undesired increase in the step-down voltage VDL raises the word line selection level VPP, and the memory cell selection MOS transistor Q1. The gate oxide film may be damaged. Such inconvenience does not occur in the DRAM of this embodiment.
[0041]
A control signal φnode1 for switching the MOS transistor Q52 is formed by the timing controller TG. The control signal φnode1 is low for a certain period within a period in which the step-down voltage VDL is supplied to the sense amplifier 3 as the operation power after the operation power of the sense amplifier 3 is switched from the external power supply voltage VDD to the step-down voltage VDL. To the level. The discharge unit 11 can form a discharge path by the negative feedback control only when the control signal φnode1 is at a low level. The period during which the control signal φnode1 is set to the low level corresponds to the timing at which current backflow from the drive line SDP may occur. In other periods, the substantial discharge operation of the discharge unit 11 is inhibited. As a result, it is possible to eliminate the inconvenience caused by the fact that the direct current through path via the MOS transistors Q50 and Q51 can always be formed. That is, when negative feedback control is always performed on the step-down unit side and the discharge unit side, the current supply operation and the current extraction operation through the MOS transistors Q50 and Q51 are frequently repeated, so that the power consumption increases to a level that cannot be ignored. In addition, the negative feedback control is always performed on the step-down unit side and the discharge side, so that the step-down voltage is periodically fluctuated and the step-down voltage is periodically changed even when the current backflow from the drive line SDP does not occur. It can prevent the situation that changes.
[0042]
Further, in this embodiment, separate operational amplifiers AMP1 and AMP2 are used on the step-down unit side and the discharge unit side, so that excessive discharge is caused by making the circuit characteristics different (for example, making the offset voltages different from each other). It is possible to increase the flexibility of circuit design such as preventing operation.
[0043]
Although the invention made by the present inventor has been specifically described based on the embodiments, it is needless to say that the present invention is not limited thereto and can be variously modified without departing from the gist thereof. For example, the operational amplifier may be shared by the step-down unit 10 and the discharge unit 11. Further, the current source in the step-down unit 10 and the discharge unit 11 is not limited to a configuration in which negative feedback control is performed using an operational amplifier. Further, the memory mat configuration of the DRAM, the logic configuration of the mat selection, the number of parallel input / output bits of data, etc. are not limited to the above embodiment, and can be changed as appropriate.
[0044]
In the above description, the case where the invention made by the present inventor is mainly applied to a DRAM which is a field of use as a background has been described. However, the present invention is not limited to this and is operated synchronously with a clock signal. The present invention can also be applied to a synchronous DRAM, a pseudo static RAM, and those memories on-chip in a data processing LSI such as a microcomputer.
[0045]
【The invention's effect】
The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows.
[0046]
That is, in the flow of lowering the operating voltage accompanying the higher integration of the memory array, when trying to guarantee high-speed operation of a differential amplifier circuit such as a sense amplifier by overdrive technology, the drive line of the differential amplifier circuit Even if a reverse current flows from the current to the step-down circuit, it is possible to prevent the step-down voltage from being undesirably increased in level.
[0047]
Therefore, it is possible to prevent a situation in which the reliability of the circuit aimed at lowering the operating voltage is lowered due to a negative desired increase in the step-down voltage. For example, the voltage difference between the data line selection level and the data line high level is reduced by increasing the voltage reached by the data line by the amplification operation of a differential amplifier circuit such as a sense amplifier as the step-down voltage increases. It is possible to prevent a situation in which the high-level voltage of the data line cannot be applied to the storage capacitor in the high-level writing to the memory cell. If the voltage reached by the data line by the differential amplifier circuit such as the sense amplifier is increased due to an undesired increase in the step-down voltage, the precharge level of the data line to be equalized is increased accordingly. When data written in such a state is read, it is possible to prevent the read voltage margin at the high level relative to the precharge level from being reduced. In addition, when the step-up voltage forming the word line selection level uses the step-down voltage, an undesired level increase of the step-down voltage increases the word line selection level and damages the gate oxide film of the memory cell selection transistor. There is no danger of it.
[Brief description of the drawings]
FIG. 1 is a circuit diagram of an embodiment for supplying operation power to a drive line of a sense amplifier.
FIG. 2 is an operation waveform diagram when a discharge unit is employed in the step-down circuit.
FIG. 3 is an operation waveform diagram showing a comparative example when a discharge unit is not employed in the step-down circuit.
FIG. 4 is an overall block diagram of a DRAM according to an embodiment of the present invention.
FIG. 5 is a partial circuit diagram of a memory mat, a sense amplifier block, and a column switch circuit block of the DRAM of this embodiment.
[Explanation of symbols]
MARY0, MARY1 memory array
MMAT0 to MMAT7 memory mat
SA01, SA23, SA45, SA67 Sense amplifier block
WD0 to WD7 Word driver
XD0 to XD7 row address decoder
YD column address decoder
TG timing controller
DL0, DL0B, DL1, DL1B Complementary data lines
WLi, WL (i-1) Word line
MC dynamic memory cell
Q17, Q18 MOS transistors for precharging
Q21 Equalize MOS transistor
VDL step-down voltage
VDD External power supply voltage
VSS Ground voltage
VPP Word line drive voltage
1 Step-down circuit
10 Step-down unit
AMP1 operational amplifier
Q50 Current source MOS transistor
R1 high resistance
Nout output terminal
11 Discharge unit
AMP2 operational amplifier
Q51 Current source MOS transistor
R2 high resistance
Q52 Discharge MOS transistor
φnode1 control signal
2 Booster circuit
3 Sense amplifier
Q9, Q10 N-channel MOS transistor for sense amplifier configuration
Q13, Q14 P-channel MOS transistor for sense amplifier configuration
SDP, SDN Sense amplifier drive line
Q41, Q42 MOS transistors for operating power supply to SDP
Q40 MOS transistor for supplying power to SDN
φSAP2, φSAP1B, φSAN Sense amplifier control signal
4 Precharge voltage forming circuit

Claims (2)

A plurality of memory cells provided at intersections of a plurality of word lines and a plurality of data lines;
A plurality of sense amplifiers provided corresponding to the plurality of data lines, for amplifying signals read from the plurality of memory cells to a first potential or a second potential lower than the first potential;
First and second drive lines connected to the plurality of sense amplifiers;
A first operating power supply transistor connected to the first drive line;
A second operation power supply transistor connected to the second drive line;
A potential supply node connected to the first operation power supply transistor; and a step-down circuit having a step-down unit and a discharge unit connected to the potential supply node,
The step-down unit is
A first current source MOS transistor coupled to the potential supply node;
A first high resistance coupled to ground potential;
A series connection point of the first current source MOS transistor and the first high resistance is provided as an output terminal, the output terminal is fed back to an inverting input terminal, and a reference voltage is supplied to a non-inverting input terminal. A first operational amplifier for switch-controlling the current source MOS transistor of
The discharge unit is
A second high resistance coupled to the potential supply node;
A second current source MOS transistor coupled to ground potential;
A series connection point of the second high resistance and the second current source MOS transistor is coupled to the output terminal, the output terminal is fed back to an inverting input terminal, and the reference voltage is supplied to a non-inverting input terminal. A second operational amplifier for switch-controlling the second current source MOS transistor;
After the operation power supply of the sense amplifier is switched from the voltage of the potential supply node to the output voltage of the step-down circuit, a predetermined period within a period in which the output voltage of the step-down circuit is supplied to the sense amplifier as the operation power supply. And a means for forcing the second current source MOS transistor to an off state . It said plurality of memory cells, the semiconductor device according to claim 1 Symbol mounting characterized in that it is a dynamic memory cell.

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